diff --git a/Cargo.toml b/Cargo.toml index a36981f..6359fdc 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -1,6 +1,6 @@ [package] name = "risc0-verifier" -version = "0.10.0" +version = "0.11.0" edition = "2021" license = "Apache-2.0" repository = "https://github.com/HorizenLabs/risc0-verifier" @@ -12,11 +12,14 @@ keywords = ["crypto", "no-std", "blockchain", "cryptography", "risc0"] serde = { version = "1.0.217", default-features = false, features = ["derive"] } risc0-core-v1 = { package = "risc0-core", version = "1.2.6", default-features = false } risc0-core-v2 = { package = "risc0-core", version = "2.0.0", default-features = false } +risc0-core-v3 = { package = "risc0-core", version = "3.0.0", default-features = false } risc0-zkp-v1 = { package = "risc0-zkp", version = "1.2.6", default-features = false } risc0-zkp-v2 = { package = "risc0-zkp", version = "2.0.0", default-features = false } +risc0-zkp-v3 = { package = "risc0-zkp", version = "3.0.0", default-features = false } risc0-binfmt-v1 = { package = "risc0-binfmt", version = "1.2.6", default-features = false } risc0-circuit-rv32im-v1 = { package = "risc0-circuit-rv32im", version = "1.2.6", default-features = false } risc0-circuit-rv32im-v2 = { package = "risc0-circuit-rv32im", version = "^3.0.0", default-features = false } +risc0-circuit-rv32im-v4 = { package = "risc0-circuit-rv32im", version = "^4.0.0", default-features = false } anyhow = { version = "1.0.95", default-features = false } hex = { version = "0.4.3", default-features = false, features = ["alloc"] } bytemuck = { version = "1.21.0", default-features = false } diff --git a/benches/base.rs b/benches/base.rs index 7029bca..ca5b3de 100644 --- a/benches/base.rs +++ b/benches/base.rs @@ -20,7 +20,7 @@ fn main() { divan::main(); } -use risc0_verifier::{v1_2, v2_1, Verifier}; +use risc0_verifier::{v1_2, v2_1, v3_0, Verifier}; use utils::*; mod utils; @@ -435,6 +435,136 @@ pub mod poseidon2 { } } } + + mod v_3_0 { + use super::*; + + fn verifier() -> impl Verifier { + v3_0() + } + + #[divan::bench] + fn verify_16() { + let verifier = verifier(); + let case: Case = + read_json("resources/cases/prover_3.0.0/vm_3.0.0/poseidon2_16.json").unwrap(); + let proof = read_bin(case.receipt_path).unwrap(); + + compute( + divan::black_box(&verifier), + divan::black_box(proof), + divan::black_box(case.vk.into()), + divan::black_box(case.journal), + ) + } + + #[divan::bench] + fn verify_22() { + let verifier = verifier(); + let case: Case = + read_json("resources/cases/prover_3.0.0/vm_3.0.0/poseidon2_22.json").unwrap(); + let proof = read_bin(case.receipt_path).unwrap(); + + compute( + divan::black_box(&verifier), + divan::black_box(proof), + divan::black_box(case.vk.into()), + divan::black_box(case.journal), + ) + } + + mod single_full_segment { + use super::*; + + fn path(po2: u32) -> String { + format!("resources/cases/single_full_segment_v3/poseidon2_{po2}.json") + } + + #[divan::bench] + fn verify_16() { + let verifier = verifier(); + let case: Case = read_json(path(16)).unwrap(); + let proof = read_bin(case.receipt_path).unwrap(); + + compute( + divan::black_box(&verifier), + divan::black_box(proof), + divan::black_box(case.vk.into()), + divan::black_box(case.journal), + ) + } + + #[divan::bench] + fn verify_17() { + let verifier = verifier(); + let case: Case = read_json(path(17)).unwrap(); + let proof = read_bin(case.receipt_path).unwrap(); + + compute( + divan::black_box(&verifier), + divan::black_box(proof), + divan::black_box(case.vk.into()), + divan::black_box(case.journal), + ) + } + + #[divan::bench] + fn verify_18() { + let verifier = verifier(); + let case: Case = read_json(path(18)).unwrap(); + let proof = read_bin(case.receipt_path).unwrap(); + + compute( + divan::black_box(&verifier), + divan::black_box(proof), + divan::black_box(case.vk.into()), + divan::black_box(case.journal), + ) + } + + #[divan::bench] + fn verify_19() { + let verifier = verifier(); + let case: Case = read_json(path(19)).unwrap(); + let proof = read_bin(case.receipt_path).unwrap(); + + compute( + divan::black_box(&verifier), + divan::black_box(proof), + divan::black_box(case.vk.into()), + divan::black_box(case.journal), + ) + } + + #[divan::bench] + fn verify_20() { + let verifier = verifier(); + let case: Case = read_json(path(20)).unwrap(); + let proof = read_bin(case.receipt_path).unwrap(); + + compute( + divan::black_box(&verifier), + divan::black_box(proof), + divan::black_box(case.vk.into()), + divan::black_box(case.journal), + ) + } + + #[divan::bench] + fn verify_21() { + let verifier = verifier(); + let case: Case = read_json(path(21)).unwrap(); + let proof = read_bin(case.receipt_path).unwrap(); + + compute( + divan::black_box(&verifier), + divan::black_box(proof), + divan::black_box(case.vk.into()), + divan::black_box(case.journal), + ) + } + } + } } pub mod succinct { @@ -515,4 +645,42 @@ pub mod succinct { ) } } + + mod v_3_0 { + use super::*; + + fn verifier() -> impl Verifier { + v3_0() + } + + #[divan::bench] + fn verify_16() { + let verifier = verifier(); + let case: Case = + read_json("resources/cases/prover_3.0.0/vm_3.0.0/succinct_16.json").unwrap(); + let proof = read_bin(case.receipt_path).unwrap(); + + compute( + divan::black_box(&verifier), + divan::black_box(proof), + divan::black_box(case.vk.into()), + divan::black_box(case.journal), + ) + } + + #[divan::bench] + fn verify_22() { + let verifier = verifier(); + let case: Case = + read_json("resources/cases/prover_3.0.0/vm_3.0.0/succinct_22.json").unwrap(); + let proof = read_bin(case.receipt_path).unwrap(); + + compute( + divan::black_box(&verifier), + divan::black_box(proof), + divan::black_box(case.vk.into()), + divan::black_box(case.journal), + ) + } + } } diff --git a/generate_proofs/host/Cargo.toml b/generate_proofs/host/Cargo.toml index d815e7d..996352f 100644 --- a/generate_proofs/host/Cargo.toml +++ b/generate_proofs/host/Cargo.toml @@ -4,8 +4,8 @@ version = "0.1.0" edition = "2021" [dependencies] -risc0-zkvm = { version = "2.3.0", features = ["prove"] } -risc0-zkp = { version = "2.0.0" } +risc0-zkvm = { version = "3.0.0", features = ["prove"] } +risc0-zkp = { version = "3.0.0" } tracing-subscriber = { version = "0.3", features = ["env-filter"] } serde_json = "1.0.133" ciborium = "0.2.2" diff --git a/generate_proofs/host/method-3.0.0/info.txt b/generate_proofs/host/method-3.0.0/info.txt new file mode 100644 index 0000000..eff39c8 --- /dev/null +++ b/generate_proofs/host/method-3.0.0/info.txt @@ -0,0 +1 @@ +7f423b2f1095359fe3305c5328e9f5cc3eba01c9f9559bfbf6a3a59d73cc77ae diff --git a/generate_proofs/host/method-3.0.0/method b/generate_proofs/host/method-3.0.0/method new file mode 100644 index 0000000..8744c61 Binary files /dev/null and b/generate_proofs/host/method-3.0.0/method differ diff --git a/generate_proofs/methods/Cargo.toml b/generate_proofs/methods/Cargo.toml index c826587..c52ac90 100644 --- a/generate_proofs/methods/Cargo.toml +++ b/generate_proofs/methods/Cargo.toml @@ -4,7 +4,7 @@ version = "0.1.0" edition = "2021" [build-dependencies] -risc0-build = { version = "2.1.2" } +risc0-build = { version = "3.0.0" } [package.metadata.risc0] methods = ["guest"] diff --git a/generate_proofs/methods/guest/Cargo.toml b/generate_proofs/methods/guest/Cargo.toml index 1013646..a14eec2 100644 --- a/generate_proofs/methods/guest/Cargo.toml +++ b/generate_proofs/methods/guest/Cargo.toml @@ -6,10 +6,10 @@ edition = "2021" [workspace] [dependencies] -risc0-zkvm = { version = "2.3.0", default-features = false, features = [ +risc0-zkvm = { version = "3.0.0", default-features = false, features = [ 'std', ] } -risc0-zkp = { version = "2.0.0", default-features = false } +risc0-zkp = { version = "3.0.0", default-features = false } [package.metadata.cargo-machete] # Used to fix the version diff --git a/resources/cases/prover_3.0.0/vm_3.0.0/poseidon2_16.json b/resources/cases/prover_3.0.0/vm_3.0.0/poseidon2_16.json new file mode 100644 index 0000000..8744a40 --- /dev/null +++ b/resources/cases/prover_3.0.0/vm_3.0.0/poseidon2_16.json @@ -0,0 +1,25 @@ +{ + "receipt_path": "./resources/receipts/3.0.0-3.0.0/poseidon2_16.bin", + "journal": { + "bytes": [ + 58, + 64, + 0, + 0, + 0, + 0, + 0, + 0 + ] + }, + "vk": [ + 792412799, + 2671088912, + 1398550755, + 3438668072, + 3372333630, + 4221261305, + 2644878326, + 2927086707 + ] +} \ No newline at end of file diff --git a/resources/cases/prover_3.0.0/vm_3.0.0/poseidon2_22.json b/resources/cases/prover_3.0.0/vm_3.0.0/poseidon2_22.json new file mode 100644 index 0000000..e115414 --- /dev/null +++ b/resources/cases/prover_3.0.0/vm_3.0.0/poseidon2_22.json @@ -0,0 +1,25 @@ +{ + "receipt_path": "./resources/receipts/3.0.0-3.0.0/poseidon2_22.bin", + "journal": { + "bytes": [ + 34, + 0, + 60, + 0, + 0, + 0, + 0, + 0 + ] + }, + "vk": [ + 792412799, + 2671088912, + 1398550755, + 3438668072, + 3372333630, + 4221261305, + 2644878326, + 2927086707 + ] +} \ No newline at end of file diff --git a/resources/cases/prover_3.0.0/vm_3.0.0/succinct_16.json b/resources/cases/prover_3.0.0/vm_3.0.0/succinct_16.json new file mode 100644 index 0000000..46c6079 --- /dev/null +++ b/resources/cases/prover_3.0.0/vm_3.0.0/succinct_16.json @@ -0,0 +1,25 @@ +{ + "receipt_path": "./resources/receipts/3.0.0-3.0.0/succinct_16.bin", + "journal": { + "bytes": [ + 58, + 64, + 0, + 0, + 0, + 0, + 0, + 0 + ] + }, + "vk": [ + 792412799, + 2671088912, + 1398550755, + 3438668072, + 3372333630, + 4221261305, + 2644878326, + 2927086707 + ] +} \ No newline at end of file diff --git a/resources/cases/prover_3.0.0/vm_3.0.0/succinct_22.json b/resources/cases/prover_3.0.0/vm_3.0.0/succinct_22.json new file mode 100644 index 0000000..889667f --- /dev/null +++ b/resources/cases/prover_3.0.0/vm_3.0.0/succinct_22.json @@ -0,0 +1,25 @@ +{ + "receipt_path": "./resources/receipts/3.0.0-3.0.0/succinct_22.bin", + "journal": { + "bytes": [ + 34, + 0, + 60, + 0, + 0, + 0, + 0, + 0 + ] + }, + "vk": [ + 792412799, + 2671088912, + 1398550755, + 3438668072, + 3372333630, + 4221261305, + 2644878326, + 2927086707 + ] +} \ No newline at end of file diff --git a/resources/cases/single_full_segment_v3/poseidon2_16.json b/resources/cases/single_full_segment_v3/poseidon2_16.json new file mode 100644 index 0000000..64c0fcb --- /dev/null +++ b/resources/cases/single_full_segment_v3/poseidon2_16.json @@ -0,0 +1,25 @@ +{ + "receipt_path": "./resources/receipts/single_full_segment_v3/poseidon2_16.bin", + "journal": { + "bytes": [ + 58, + 64, + 0, + 0, + 0, + 0, + 0, + 0 + ] + }, + "vk": [ + 792412799, + 2671088912, + 1398550755, + 3438668072, + 3372333630, + 4221261305, + 2644878326, + 2927086707 + ] +} \ No newline at end of file diff --git a/resources/cases/single_full_segment_v3/poseidon2_17.json b/resources/cases/single_full_segment_v3/poseidon2_17.json new file mode 100644 index 0000000..4230756 --- /dev/null +++ b/resources/cases/single_full_segment_v3/poseidon2_17.json @@ -0,0 +1,25 @@ +{ + "receipt_path": "./resources/receipts/single_full_segment_v3/poseidon2_17.bin", + "journal": { + "bytes": [ + 12, + 0, + 1, + 0, + 0, + 0, + 0, + 0 + ] + }, + "vk": [ + 792412799, + 2671088912, + 1398550755, + 3438668072, + 3372333630, + 4221261305, + 2644878326, + 2927086707 + ] +} \ No newline at end of file diff --git a/resources/cases/single_full_segment_v3/poseidon2_18.json b/resources/cases/single_full_segment_v3/poseidon2_18.json new file mode 100644 index 0000000..d01db67 --- /dev/null +++ b/resources/cases/single_full_segment_v3/poseidon2_18.json @@ -0,0 +1,25 @@ +{ + "receipt_path": "./resources/receipts/single_full_segment_v3/poseidon2_18.bin", + "journal": { + "bytes": [ + 8, + 0, + 2, + 0, + 0, + 0, + 0, + 0 + ] + }, + "vk": [ + 792412799, + 2671088912, + 1398550755, + 3438668072, + 3372333630, + 4221261305, + 2644878326, + 2927086707 + ] +} \ No newline at end of file diff --git a/resources/cases/single_full_segment_v3/poseidon2_19.json b/resources/cases/single_full_segment_v3/poseidon2_19.json new file mode 100644 index 0000000..c117cec --- /dev/null +++ b/resources/cases/single_full_segment_v3/poseidon2_19.json @@ -0,0 +1,25 @@ +{ + "receipt_path": "./resources/receipts/single_full_segment_v3/poseidon2_19.bin", + "journal": { + "bytes": [ + 0, + 0, + 4, + 0, + 0, + 0, + 0, + 0 + ] + }, + "vk": [ + 792412799, + 2671088912, + 1398550755, + 3438668072, + 3372333630, + 4221261305, + 2644878326, + 2927086707 + ] +} \ No newline at end of file diff --git a/resources/cases/single_full_segment_v3/poseidon2_20.json b/resources/cases/single_full_segment_v3/poseidon2_20.json new file mode 100644 index 0000000..fa88fff --- /dev/null +++ b/resources/cases/single_full_segment_v3/poseidon2_20.json @@ -0,0 +1,25 @@ +{ + "receipt_path": "./resources/receipts/single_full_segment_v3/poseidon2_20.bin", + "journal": { + "bytes": [ + 54, + 0, + 12, + 0, + 0, + 0, + 0, + 0 + ] + }, + "vk": [ + 792412799, + 2671088912, + 1398550755, + 3438668072, + 3372333630, + 4221261305, + 2644878326, + 2927086707 + ] +} \ No newline at end of file diff --git a/resources/cases/single_full_segment_v3/poseidon2_21.json b/resources/cases/single_full_segment_v3/poseidon2_21.json new file mode 100644 index 0000000..e90bc40 --- /dev/null +++ b/resources/cases/single_full_segment_v3/poseidon2_21.json @@ -0,0 +1,25 @@ +{ + "receipt_path": "./resources/receipts/single_full_segment_v3/poseidon2_21.bin", + "journal": { + "bytes": [ + 76, + 0, + 28, + 0, + 0, + 0, + 0, + 0 + ] + }, + "vk": [ + 792412799, + 2671088912, + 1398550755, + 3438668072, + 3372333630, + 4221261305, + 2644878326, + 2927086707 + ] +} \ No newline at end of file diff --git a/resources/cases/single_full_segment_v3/poseidon2_22.json b/resources/cases/single_full_segment_v3/poseidon2_22.json new file mode 100644 index 0000000..34616f4 --- /dev/null +++ b/resources/cases/single_full_segment_v3/poseidon2_22.json @@ -0,0 +1,25 @@ +{ + "receipt_path": "./resources/receipts/single_full_segment_v3/poseidon2_22.bin", + "journal": { + "bytes": [ + 34, + 0, + 60, + 0, + 0, + 0, + 0, + 0 + ] + }, + "vk": [ + 792412799, + 2671088912, + 1398550755, + 3438668072, + 3372333630, + 4221261305, + 2644878326, + 2927086707 + ] +} \ No newline at end of file diff --git a/resources/receipts/3.0.0-3.0.0/poseidon2_16.bin b/resources/receipts/3.0.0-3.0.0/poseidon2_16.bin new file mode 100644 index 0000000..8c4f616 Binary files /dev/null and b/resources/receipts/3.0.0-3.0.0/poseidon2_16.bin differ diff --git a/resources/receipts/3.0.0-3.0.0/poseidon2_22.bin b/resources/receipts/3.0.0-3.0.0/poseidon2_22.bin new file mode 100644 index 0000000..b05c50d Binary files /dev/null and b/resources/receipts/3.0.0-3.0.0/poseidon2_22.bin differ diff --git a/resources/receipts/3.0.0-3.0.0/succinct_16.bin b/resources/receipts/3.0.0-3.0.0/succinct_16.bin new file mode 100644 index 0000000..846f671 Binary files /dev/null and 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0000000..bb2c8c0 Binary files /dev/null and b/resources/receipts/single_full_segment_v3/poseidon2_18.bin differ diff --git a/resources/receipts/single_full_segment_v3/poseidon2_19.bin b/resources/receipts/single_full_segment_v3/poseidon2_19.bin new file mode 100644 index 0000000..49a4700 Binary files /dev/null and b/resources/receipts/single_full_segment_v3/poseidon2_19.bin differ diff --git a/resources/receipts/single_full_segment_v3/poseidon2_20.bin b/resources/receipts/single_full_segment_v3/poseidon2_20.bin new file mode 100644 index 0000000..d036c89 Binary files /dev/null and b/resources/receipts/single_full_segment_v3/poseidon2_20.bin differ diff --git a/resources/receipts/single_full_segment_v3/poseidon2_21.bin b/resources/receipts/single_full_segment_v3/poseidon2_21.bin new file mode 100644 index 0000000..f2d6103 Binary files /dev/null and b/resources/receipts/single_full_segment_v3/poseidon2_21.bin differ diff --git a/resources/receipts/single_full_segment_v3/poseidon2_22.bin b/resources/receipts/single_full_segment_v3/poseidon2_22.bin new file mode 100644 index 0000000..e4bb09f Binary files /dev/null and b/resources/receipts/single_full_segment_v3/poseidon2_22.bin differ diff --git a/src/circuit.rs b/src/circuit.rs index a597cee..7dab469 100644 --- a/src/circuit.rs +++ b/src/circuit.rs @@ -37,6 +37,17 @@ impl< { } +pub trait CircuitCoreDefV3: + risc0_zkp_v3::adapter::CircuitCoreDef + 'static +{ +} + +impl< + T: risc0_zkp_v3::adapter::CircuitCoreDef + 'static, + > CircuitCoreDefV3 for T +{ +} + pub mod v1_0; pub mod v1_1; @@ -50,3 +61,5 @@ pub mod v2_1; pub mod v2_2; pub mod v2_3; + +pub mod v3_0; diff --git a/src/circuit/v3_0.rs b/src/circuit/v3_0.rs new file mode 100644 index 0000000..1f8930a --- /dev/null +++ b/src/circuit/v3_0.rs @@ -0,0 +1,98 @@ +// Copyright Copyright 2024, Horizen Labs, Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +use risc0_core_v3::field::baby_bear::BabyBear; +use risc0_zkp_v3::{ + adapter::{CircuitCoreDef, CircuitInfo, ProtocolInfo}, + taps::TapSet, +}; + +mod poly_ext; +mod taps; + +pub const CIRCUIT: crate::circuit::v3_0::CircuitImpl = crate::circuit::v3_0::CircuitImpl::new(); +pub struct CircuitImpl; + +impl crate::circuit::v3_0::CircuitImpl { + const fn new() -> Self { + crate::circuit::v3_0::CircuitImpl + } +} + +impl risc0_zkp_v3::adapter::TapsProvider for crate::circuit::v3_0::CircuitImpl { + fn get_taps(&self) -> &'static TapSet<'static> { + crate::circuit::v3_0::taps::TAPSET + } +} + +impl CircuitInfo for crate::circuit::v3_0::CircuitImpl { + #[rustfmt::skip] + const CIRCUIT_INFO: ProtocolInfo = ProtocolInfo(*b"RV32IM:v2rev2___"); + + #[rustfmt::skip] + const OUTPUT_SIZE: usize = 90; + + #[rustfmt::skip] + const MIX_SIZE: usize = 36; +} + +impl CircuitCoreDef for crate::circuit::v3_0::CircuitImpl {} + +pub mod recursive { + use risc0_zkp_v3::{ + adapter::{CircuitCoreDef, CircuitInfo, ProtocolInfo, TapsProvider}, + field::baby_bear::BabyBear, + taps::TapSet, + }; + + #[allow(dead_code)] + pub mod control_id; + mod poly_ext; + mod taps; + + /// This struct implements traits that are defined by code generated by the + /// circuit definition. + pub struct CircuitImpl; + + impl crate::circuit::v3_0::recursive::CircuitImpl { + const fn new() -> Self { + crate::circuit::v3_0::recursive::CircuitImpl + } + } + + impl TapsProvider for crate::circuit::v3_0::recursive::CircuitImpl { + fn get_taps(&self) -> &'static TapSet<'static> { + self::taps::TAPSET + } + } + + pub const CIRCUIT: crate::circuit::v3_0::recursive::CircuitImpl = + crate::circuit::v3_0::recursive::CircuitImpl::new(); + + impl CircuitInfo for crate::circuit::v3_0::recursive::CircuitImpl { + #[rustfmt::skip] + const CIRCUIT_INFO: ProtocolInfo = ProtocolInfo(*b"RECURSION:rev1v1"); + + #[rustfmt::skip] + const OUTPUT_SIZE: usize = 32; + + #[rustfmt::skip] + const MIX_SIZE: usize = 20; + } + + impl CircuitCoreDef for crate::circuit::v3_0::recursive::CircuitImpl {} +} diff --git a/src/circuit/v3_0/poly_ext.rs b/src/circuit/v3_0/poly_ext.rs new file mode 100644 index 0000000..d0b4067 --- /dev/null +++ b/src/circuit/v3_0/poly_ext.rs @@ -0,0 +1,20246 @@ +// Copyright Copyright 2024, Horizen Labs, Inc. +// Copyright Copyright 2024 RISC Zero, Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +// This code is automatically generated + +use risc0_zkp_v3::{ + adapter::{MixState, PolyExt, PolyExtStep, PolyExtStepDef}, + field::baby_bear::{BabyBear, BabyBearElem, BabyBearExtElem}, +}; + +use super::CircuitImpl; + +#[allow(missing_docs)] +#[rustfmt::skip] +pub const DEF: PolyExtStepDef = PolyExtStepDef { + block: &[PolyExtStep::Const(0), // loc(unknown) +PolyExtStep::Const(1), // loc(unknown) +PolyExtStep::Const(7), // loc(unknown) +PolyExtStep::Const(6), // loc(unknown) +PolyExtStep::Const(5), // loc(unknown) +PolyExtStep::Const(4), // loc(unknown) +PolyExtStep::Const(3), // loc(unknown) +PolyExtStep::Const(2), // loc(unknown) +PolyExtStep::Const(12), // loc(unknown) +PolyExtStep::Const(11), // loc(unknown) +PolyExtStep::Const(10), // loc(unknown) +PolyExtStep::Const(9), // loc(unknown) +PolyExtStep::Const(8), // loc(unknown) +PolyExtStep::Const(48), // loc(unknown) +PolyExtStep::Const(16384), // loc(unknown) +PolyExtStep::Const(49151), // loc(unknown) +PolyExtStep::Const(65535), // loc(unknown) +PolyExtStep::Const(2013265920), // loc(unknown) +PolyExtStep::Const(61440), // loc(unknown) +PolyExtStep::Const(64), // loc(unknown) +PolyExtStep::Const(256), // loc(unknown) +PolyExtStep::Const(1024), // loc(unknown) +PolyExtStep::Const(4096), // loc(unknown) +PolyExtStep::Const(16), // loc(unknown) +PolyExtStep::Const(32), // loc(unknown) +PolyExtStep::Const(128), // loc(unknown) +PolyExtStep::Const(512), // loc(unknown) +PolyExtStep::Const(2048), // loc(unknown) +PolyExtStep::Const(8192), // loc(unknown) +PolyExtStep::Const(32768), // loc(unknown) +PolyExtStep::Const(1073725440), // loc(unknown) +PolyExtStep::Const(1073725472), // loc(unknown) +PolyExtStep::Const(51), // loc(unknown) +PolyExtStep::Const(65536), // loc(unknown) +PolyExtStep::Const(13), // loc(unknown) +PolyExtStep::Const(14), // loc(unknown) +PolyExtStep::Const(15), // loc(unknown) +PolyExtStep::Const(1006632961), // loc(unknown) +PolyExtStep::Const(19), // loc(unknown) +PolyExtStep::Const(99), // loc(unknown) +PolyExtStep::Const(65520), // loc(unknown) +PolyExtStep::Const(111), // loc(unknown) +PolyExtStep::Const(103), // loc(unknown) +PolyExtStep::Const(55), // loc(unknown) +PolyExtStep::Const(23), // loc(unknown) +PolyExtStep::Const(115), // loc(unknown) +PolyExtStep::Const(131070), // loc(unknown) +PolyExtStep::Const(131072), // loc(unknown) +PolyExtStep::Const(16777216), // loc(unknown) +PolyExtStep::Const(2013235201), // loc(unknown) +PolyExtStep::Const(65280), // loc(unknown) +PolyExtStep::Const(35), // loc(unknown) +PolyExtStep::Const(1073725457), // loc(unknown) +PolyExtStep::Const(40), // loc(unknown) +PolyExtStep::Const(1140850688), // loc(unknown) +PolyExtStep::Const(1073741824), // loc(unknown) +PolyExtStep::Const(1342177281), // loc(unknown) +PolyExtStep::Const(22), // loc(unknown) +PolyExtStep::ConstExt(0,0,0,0), // loc(unknown) +PolyExtStep::Const(17), // loc(unknown) +PolyExtStep::Const(18), // loc(unknown) +PolyExtStep::Const(21), // loc(unknown) +PolyExtStep::Const(1073725450), // loc(unknown) +PolyExtStep::Const(1509949441), // loc(unknown) +PolyExtStep::Const(1073725451), // loc(unknown) +PolyExtStep::Const(1073725452), // loc(unknown) +PolyExtStep::Const(1073725453), // loc(unknown) +PolyExtStep::ConstExt(1,0,0,0), // loc(unknown) +PolyExtStep::Const(24), // loc(unknown) +PolyExtStep::Const(30719), // loc(unknown) +PolyExtStep::Const(30720), // loc(unknown) +PolyExtStep::Const(1761607681), // loc(unknown) +PolyExtStep::Const(4194304), // loc(unknown) +PolyExtStep::Const(25), // loc(unknown) +PolyExtStep::Const(262278199), // loc(unknown) +PolyExtStep::Const(127253399), // loc(unknown) +PolyExtStep::Const(314968988), // loc(unknown) +PolyExtStep::Const(246143118), // loc(unknown) +PolyExtStep::Const(157582794), // loc(unknown) +PolyExtStep::Const(118043943), // loc(unknown) +PolyExtStep::Const(454905424), // loc(unknown) +PolyExtStep::Const(815798990), // loc(unknown) +PolyExtStep::Const(1004040026), // loc(unknown) +PolyExtStep::Const(1773108264), // loc(unknown) +PolyExtStep::Const(1066694495), // loc(unknown) +PolyExtStep::Const(1930780904), // loc(unknown) +PolyExtStep::Const(1180307149), // loc(unknown) +PolyExtStep::Const(1464793095), // loc(unknown) +PolyExtStep::Const(1660766320), // loc(unknown) +PolyExtStep::Const(1389166148), // loc(unknown) +PolyExtStep::Const(343354132), // loc(unknown) +PolyExtStep::Const(1307439985), // loc(unknown) +PolyExtStep::Const(638242172), // loc(unknown) +PolyExtStep::Const(525458520), // loc(unknown) +PolyExtStep::Const(1964135730), // loc(unknown) +PolyExtStep::Const(1751797115), // loc(unknown) +PolyExtStep::Const(1421525369), // loc(unknown) +PolyExtStep::Const(831813382), // loc(unknown) +PolyExtStep::Const(989176635), // loc(unknown) +PolyExtStep::Const(241306552), // loc(unknown) +PolyExtStep::Const(1507936940), // loc(unknown) +PolyExtStep::Const(1687379185), // loc(unknown) +PolyExtStep::Const(1150912935), // loc(unknown) +PolyExtStep::Const(1917549072), // loc(unknown) +PolyExtStep::Const(1201063290), // loc(unknown) +PolyExtStep::Const(395622276), // loc(unknown) +PolyExtStep::Const(1997503974), // loc(unknown) +PolyExtStep::Const(716894289), // loc(unknown) +PolyExtStep::Const(897025192), // loc(unknown) +PolyExtStep::Const(1282239129), // loc(unknown) +PolyExtStep::Const(1737016378), // loc(unknown) +PolyExtStep::Const(686842369), // loc(unknown) +PolyExtStep::Const(622609176), // loc(unknown) +PolyExtStep::Const(1339793538), // loc(unknown) +PolyExtStep::Const(1518763784), // loc(unknown) +PolyExtStep::Const(1989924532), // loc(unknown) +PolyExtStep::Const(1170029417), // loc(unknown) +PolyExtStep::Const(1917861751), // loc(unknown) +PolyExtStep::Const(1333667262), // loc(unknown) +PolyExtStep::Const(540703332), // loc(unknown) +PolyExtStep::Const(1845603984), // loc(unknown) +PolyExtStep::Const(695835963), // loc(unknown) +PolyExtStep::Const(862495875), // loc(unknown) +PolyExtStep::Const(447555988), // loc(unknown) +PolyExtStep::Const(1910423126), // loc(unknown) +PolyExtStep::Const(1099252725), // loc(unknown) +PolyExtStep::Const(1584033957), // loc(unknown) +PolyExtStep::Const(1079030649), // loc(unknown) +PolyExtStep::Const(1622328571), // loc(unknown) +PolyExtStep::Const(1908416316), // loc(unknown) +PolyExtStep::Const(1549062383), // loc(unknown) +PolyExtStep::Const(623051854), // loc(unknown) +PolyExtStep::Const(162510541), // loc(unknown) +PolyExtStep::Const(1608853840), // loc(unknown) +PolyExtStep::Const(538103555), // loc(unknown) +PolyExtStep::Const(1424297384), // loc(unknown) +PolyExtStep::Const(552696906), // loc(unknown) +PolyExtStep::Const(946500736), // loc(unknown) +PolyExtStep::Const(1215259350), // loc(unknown) +PolyExtStep::Const(855276054), // loc(unknown) +PolyExtStep::Const(1664590951), // loc(unknown) +PolyExtStep::Const(217046702), // loc(unknown) +PolyExtStep::Const(142102402), // loc(unknown) +PolyExtStep::Const(1257820264), // loc(unknown) +PolyExtStep::Const(27129487), // loc(unknown) +PolyExtStep::Const(1147522062), // loc(unknown) +PolyExtStep::Const(1291790245), // loc(unknown) +PolyExtStep::Const(1781980094), // loc(unknown) +PolyExtStep::Const(273790406), // loc(unknown) +PolyExtStep::Const(1239734761), // loc(unknown) +PolyExtStep::Const(1221257987), // loc(unknown) +PolyExtStep::Const(51256176), // loc(unknown) +PolyExtStep::Const(172614232), // loc(unknown) +PolyExtStep::Const(306391314), // loc(unknown) +PolyExtStep::Const(1647670797), // loc(unknown) +PolyExtStep::Const(53007114), // loc(unknown) +PolyExtStep::Const(1269493554), // loc(unknown) +PolyExtStep::Const(1338899225), // loc(unknown) +PolyExtStep::Const(1740472809), // loc(unknown) +PolyExtStep::Const(1454563174), // loc(unknown) +PolyExtStep::Const(204228775), // loc(unknown) +PolyExtStep::Const(588764636), // loc(unknown) +PolyExtStep::Const(1718628547), // loc(unknown) +PolyExtStep::Const(427731030), // loc(unknown) +PolyExtStep::Const(825405577), // loc(unknown) +PolyExtStep::Const(342857858), // loc(unknown) +PolyExtStep::Const(1290028279), // loc(unknown) +PolyExtStep::Const(608401422), // loc(unknown) +PolyExtStep::Const(1587822577), // loc(unknown) +PolyExtStep::Const(128479034), // loc(unknown) +PolyExtStep::Const(1040977421), // loc(unknown) +PolyExtStep::Const(1792450386), // loc(unknown) +PolyExtStep::Const(1470845646), // loc(unknown) +PolyExtStep::Const(1363837384), // loc(unknown) +PolyExtStep::Const(1878280202), // loc(unknown) +PolyExtStep::Const(434078361), // loc(unknown) +PolyExtStep::Const(1946596189), // loc(unknown) +PolyExtStep::Const(875839332), // loc(unknown) +PolyExtStep::Const(463976218), // loc(unknown) +PolyExtStep::Const(976057819), // loc(unknown) +PolyExtStep::Const(48375137), // loc(unknown) +PolyExtStep::Const(1549779579), // loc(unknown) +PolyExtStep::Const(1679178250), // loc(unknown) +PolyExtStep::Const(530151394), // loc(unknown) +PolyExtStep::Const(1629316321), // loc(unknown) +PolyExtStep::Const(1854174607), // loc(unknown) +PolyExtStep::Const(720724951), // loc(unknown) +PolyExtStep::Const(14387587), // loc(unknown) +PolyExtStep::Const(1883820770), // loc(unknown) +PolyExtStep::Const(205609311), // loc(unknown) +PolyExtStep::Const(1136469704), // loc(unknown) +PolyExtStep::Const(1439947916), // loc(unknown) +PolyExtStep::Const(723038058), // loc(unknown) +PolyExtStep::Const(53041581), // loc(unknown) +PolyExtStep::Const(150307788), // loc(unknown) +PolyExtStep::Const(755691969), // loc(unknown) +PolyExtStep::Const(1715719711), // loc(unknown) +PolyExtStep::Const(1545325389), // loc(unknown) +PolyExtStep::Const(989618631), // loc(unknown) +PolyExtStep::Const(1401020792), // loc(unknown) +PolyExtStep::Const(930036496), // loc(unknown) +PolyExtStep::Const(238616145), // loc(unknown) +PolyExtStep::Const(1006235079), // loc(unknown) +PolyExtStep::Const(942439428), // loc(unknown) +PolyExtStep::Const(1649953458), // loc(unknown) +PolyExtStep::Const(1647665372), // loc(unknown) +PolyExtStep::Const(708123747), // loc(unknown) +PolyExtStep::Const(925018226), // loc(unknown) +PolyExtStep::Const(78845751), // loc(unknown) +PolyExtStep::Const(1889603648), // loc(unknown) +PolyExtStep::Const(993455846), // loc(unknown) +PolyExtStep::Const(140621810), // loc(unknown) +PolyExtStep::Const(117294666), // loc(unknown) +PolyExtStep::Const(790726260), // loc(unknown) +PolyExtStep::Const(1213686459), // loc(unknown) +PolyExtStep::Const(390340387), // loc(unknown) +PolyExtStep::Const(714957516), // loc(unknown) +PolyExtStep::Const(1209164052), // loc(unknown) +PolyExtStep::Const(1827572010), // loc(unknown) +PolyExtStep::Const(1507649755), // loc(unknown) +PolyExtStep::Const(1042892522), // loc(unknown) +PolyExtStep::Const(760115692), // loc(unknown) +PolyExtStep::Const(1841795381), // loc(unknown) +PolyExtStep::Const(457372011), // loc(unknown) +PolyExtStep::Const(1748789933), // loc(unknown) +PolyExtStep::Const(1478577620), // loc(unknown) +PolyExtStep::Const(76770019), // loc(unknown) +PolyExtStep::Const(1293938517), // loc(unknown) +PolyExtStep::Const(1150410028), // loc(unknown) +PolyExtStep::Const(1065075039), // loc(unknown) +PolyExtStep::Const(1198261138), // loc(unknown) +PolyExtStep::Const(59510015), // loc(unknown) +PolyExtStep::Const(1402624179), // loc(unknown) +PolyExtStep::Const(158646617), // loc(unknown) +PolyExtStep::Const(890243564), // loc(unknown) +PolyExtStep::Const(1463323727), // loc(unknown) +PolyExtStep::Const(1080533265), // loc(unknown) +PolyExtStep::Const(192082241), // loc(unknown) +PolyExtStep::Const(1891637550), // loc(unknown) +PolyExtStep::Const(1950429111), // loc(unknown) +PolyExtStep::Const(1663353317), // loc(unknown) +PolyExtStep::Const(1567618575), // loc(unknown) +PolyExtStep::Const(1380248020), // loc(unknown) +PolyExtStep::Const(1608891156), // loc(unknown) +PolyExtStep::Const(1672219447), // loc(unknown) +PolyExtStep::Const(1262312258), // loc(unknown) +PolyExtStep::Const(162506101), // loc(unknown) +PolyExtStep::Const(809508074), // loc(unknown) +PolyExtStep::Const(1303271640), // loc(unknown) +PolyExtStep::Const(1393671120), // loc(unknown) +PolyExtStep::Const(641665156), // loc(unknown) +PolyExtStep::Const(1090783436), // loc(unknown) +PolyExtStep::Const(1111203133), // loc(unknown) +PolyExtStep::Const(1296144415), // loc(unknown) +PolyExtStep::Const(202271745), // loc(unknown) +PolyExtStep::Const(459826664), // loc(unknown) +PolyExtStep::Const(781141772), // loc(unknown) +PolyExtStep::Const(1832911930), // loc(unknown) +PolyExtStep::Const(228520958), // loc(unknown) +PolyExtStep::Const(813674331), // loc(unknown) +PolyExtStep::Const(1889898), // loc(unknown) +PolyExtStep::Const(1124078057), // loc(unknown) +PolyExtStep::Const(738091882), // loc(unknown) +PolyExtStep::Const(1003792297), // loc(unknown) +PolyExtStep::Const(1896271507), // loc(unknown) +PolyExtStep::Const(1206940496), // loc(unknown) +PolyExtStep::Const(497520322), // loc(unknown) +PolyExtStep::Const(1930103076), // loc(unknown) +PolyExtStep::Const(1052077299), // loc(unknown) +PolyExtStep::Const(1540960371), // loc(unknown) +PolyExtStep::Const(924863639), // loc(unknown) +PolyExtStep::Const(1365519753), // loc(unknown) +PolyExtStep::Const(1726563304), // loc(unknown) +PolyExtStep::Const(440300254), // loc(unknown) +PolyExtStep::Const(1891545577), // loc(unknown) +PolyExtStep::Const(822033215), // loc(unknown) +PolyExtStep::Const(1111544260), // loc(unknown) +PolyExtStep::Const(308575117), // loc(unknown) +PolyExtStep::Const(1708681573), // loc(unknown) +PolyExtStep::Const(1240419708), // loc(unknown) +PolyExtStep::Const(1199068823), // loc(unknown) +PolyExtStep::Const(1186174623), // loc(unknown) +PolyExtStep::Const(1551596046), // loc(unknown) +PolyExtStep::Const(1886977120), // loc(unknown) +PolyExtStep::Const(1327682690), // loc(unknown) +PolyExtStep::Const(1210751726), // loc(unknown) +PolyExtStep::Const(1810596765), // loc(unknown) +PolyExtStep::Const(1083257840), // loc(unknown) +PolyExtStep::Const(375892129), // loc(unknown) +PolyExtStep::Const(111593398), // loc(unknown) +PolyExtStep::Const(1867716110), // loc(unknown) +PolyExtStep::Const(658182609), // loc(unknown) +PolyExtStep::Const(51866717), // loc(unknown) +PolyExtStep::Const(1928969209), // loc(unknown) +PolyExtStep::Const(1942928017), // loc(unknown) +PolyExtStep::Const(1558116381), // loc(unknown) +PolyExtStep::Const(20525701), // loc(unknown) +PolyExtStep::Const(1188752902), // loc(unknown) +PolyExtStep::Const(106789798), // loc(unknown) +PolyExtStep::Const(1389833583), // loc(unknown) +PolyExtStep::Const(98371040), // loc(unknown) +PolyExtStep::Const(1001081699), // loc(unknown) +PolyExtStep::Const(1792686146), // loc(unknown) +PolyExtStep::Const(801504236), // loc(unknown) +PolyExtStep::Const(1997365680), // loc(unknown) +PolyExtStep::Const(1461037801), // loc(unknown) +PolyExtStep::Const(65998480), // loc(unknown) +PolyExtStep::Const(1974912880), // loc(unknown) +PolyExtStep::Const(606789471), // loc(unknown) +PolyExtStep::Const(13683276), // loc(unknown) +PolyExtStep::Const(918610824), // loc(unknown) +PolyExtStep::Const(1073725454), // loc(unknown) +PolyExtStep::Const(33), // loc(unknown) +PolyExtStep::Const(34), // loc(unknown) +PolyExtStep::Const(47), // loc(unknown) +PolyExtStep::Const(36), // loc(unknown) +PolyExtStep::Const(1073725445), // loc(unknown) +PolyExtStep::Const(1073725447), // loc(unknown) +PolyExtStep::Const(41), // loc(unknown) +PolyExtStep::ConstExt(128,0,0,0), // loc(unknown) +PolyExtStep::ConstExt(16384,0,0,0), // loc(unknown) +PolyExtStep::ConstExt(256,0,0,0), // loc(unknown) +PolyExtStep::Const(1140850680), // loc(unknown) +PolyExtStep::Const(1073725592), // loc(unknown) +PolyExtStep::Const(1073725593), // loc(unknown) +PolyExtStep::Const(1073725594), // loc(unknown) +PolyExtStep::Const(1073725595), // loc(unknown) +PolyExtStep::Const(1073725596), // loc(unknown) +PolyExtStep::Const(1073725597), // loc(unknown) +PolyExtStep::Const(1073725598), // loc(unknown) +PolyExtStep::Const(1073725599), // loc(unknown) +PolyExtStep::Const(1073726464), // loc(unknown) +PolyExtStep::Const(1073725568), // loc(unknown) +PolyExtStep::Const(12320), // loc(unknown) +PolyExtStep::Const(1073725584), // loc(unknown) +PolyExtStep::Const(1073725585), // loc(unknown) +PolyExtStep::Const(1073725586), // loc(unknown) +PolyExtStep::Const(1073725587), // loc(unknown) +PolyExtStep::Const(1073725588), // loc(unknown) +PolyExtStep::Const(1073725589), // loc(unknown) +PolyExtStep::Const(1073725590), // loc(unknown) +PolyExtStep::Const(1073725591), // loc(unknown) +PolyExtStep::Const(1140850681), // loc(unknown) +PolyExtStep::Const(1140850682), // loc(unknown) +PolyExtStep::Const(1140850683), // loc(unknown) +PolyExtStep::Const(1140850684), // loc(unknown) +PolyExtStep::Const(1140850685), // loc(unknown) +PolyExtStep::Const(1140850686), // loc(unknown) +PolyExtStep::Const(1140850687), // loc(unknown) +PolyExtStep::Const(1073725504), // loc(unknown) +PolyExtStep::Const(1073725505), // loc(unknown) +PolyExtStep::Const(1073725506), // loc(unknown) +PolyExtStep::Const(1073725507), // loc(unknown) +PolyExtStep::Const(1073725572), // loc(unknown) +PolyExtStep::Const(1073725573), // loc(unknown) +PolyExtStep::Const(1875997790), // loc(unknown) +PolyExtStep::ConstExt(0,1,0,0), // loc(unknown) +PolyExtStep::True, // All Constraints +PolyExtStep::Get(143), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :47:34) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(1, 357), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :47:34) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(357, 358), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :47:34) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 359), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :47:34) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Get(140), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :50:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(360, 2), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :50:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::AndEqz(0, 361), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :50:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Get(120), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :51:9) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(0, 362), // loc(callsite( Reg ( :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :51:9) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2, 363), // loc(callsite( Reg ( :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :51:9) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(1, 357, 3), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :49:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Get(121), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :53:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(364, 1), // loc(callsite( builtin Add at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :53:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(365, 362), // loc(callsite( Reg ( :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :53:9) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(0, 366), // loc(callsite( Reg ( :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :53:9) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(4, 358, 5), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :49:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Get(136), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :56:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(358, 367), // loc(callsite( builtin Mul at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :56:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(138), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :57:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(358, 369), // loc(callsite( builtin Mul at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :57:34) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(358, 360), // loc(callsite( builtin Mul at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :60:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(142), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :62:60) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(358, 372), // loc(callsite( builtin Mul at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :62:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(373, 357), // loc(callsite( builtin Add at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :62:61) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(144), // loc(callsite( builtin NondetReg at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :66:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(145), // loc(callsite( builtin NondetReg at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :67:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(146), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 377), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(377, 378), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6, 379), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(147), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 380), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(380, 381), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(7, 382), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(148), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 383), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(383, 384), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(8, 385), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(149), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 386), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(386, 387), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(9, 388), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(150), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 389), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(389, 390), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(10, 391), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(151), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 392), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(392, 393), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(11, 394), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(152), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 395), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(395, 396), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(12, 397), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(153), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 398), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(398, 399), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(13, 400), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(377, 380), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(401, 383), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(402, 386), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(403, 389), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(404, 392), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(405, 395), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(406, 398), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(407, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(14, 408), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(383, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(386, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(389, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(392, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(395, 3), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(398, 2), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(380, 409), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(415, 410), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(416, 411), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(417, 412), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(418, 413), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(419, 414), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(420, 376), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(15, 421), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( InstInput ( zirgen/circuit/rv32im/v2/dsl/inst.zir :14:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :70:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Get(122), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 422), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(422, 423), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(16, 424), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(123), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 425), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(425, 426), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(17, 427), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(124), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 428), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(428, 429), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(18, 430), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(125), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 431), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(431, 432), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(19, 433), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(126), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 434), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(434, 435), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(20, 436), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(127), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 437), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(437, 438), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(21, 439), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(128), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 440), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(440, 441), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(22, 442), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(129), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 443), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(443, 444), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(23, 445), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(130), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 446), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(446, 447), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(24, 448), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(131), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 449), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(449, 450), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(25, 451), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(132), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 452), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(452, 453), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(26, 454), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(133), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 455), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(455, 456), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(27, 457), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(134), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 458), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(458, 459), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(28, 460), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(422, 425), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(461, 428), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(462, 431), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(463, 434), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(464, 437), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(465, 440), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(466, 443), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(467, 446), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(468, 449), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(469, 452), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(470, 455), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(471, 458), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(472, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(29, 473), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(428, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(431, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(434, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(437, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(440, 3), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(443, 2), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(446, 12), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(449, 11), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(452, 10), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(455, 9), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(458, 8), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(425, 474), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(485, 475), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(486, 476), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(487, 477), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(488, 478), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(489, 479), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(490, 480), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(491, 481), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(492, 482), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(493, 483), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(494, 484), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(495, 375), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(30, 496), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(371, 13), // loc(callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :7:21) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(374, 16), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 374), // loc(callsite( builtin Sub at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:41) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(499, 15), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:49) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(498, 500), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:31) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(501, 370), // loc(callsite( builtin Sub at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:53) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(370, 14), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :73:12) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(374, 30), // loc(callsite( builtin Mul at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:22) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(499, 31), // loc(callsite( builtin Mul at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:63) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(504, 505), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:44) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(368, 5), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( SimpleOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :78:20) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :91:12) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :33:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(507, 377), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(507, 380), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(507, 383), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(507, 386), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(507, 389), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(507, 392), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(507, 395), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(507, 398), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(508, 509), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(516, 510), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(517, 511), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(518, 512), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(519, 513), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(520, 514), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(521, 515), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(370, 377), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(370, 380), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(370, 383), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(370, 386), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(370, 389), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(370, 392), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(370, 395), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(370, 398), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(523, 524), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(531, 525), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(532, 526), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(533, 527), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(534, 528), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(535, 529), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(536, 530), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(347), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :19:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(359), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :20:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(362, 7), // loc(callsite( builtin Mul at callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:17) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(538, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 541), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(540, 1), // loc(callsite( builtin Add at callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:19) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(539, 542), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(32, 543), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :30:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(33, 497), // loc(callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :7:21) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Get(461), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 544), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(544, 545), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 544), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(546, 547), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 544), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(548, 549), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(34, 550), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(467), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(473), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(551, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(35, 553), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(552, 502), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(36, 554), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Get(479), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(485), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :11:20) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 555), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(555, 557), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(37, 558), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(370, 556), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(559, 557), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(38, 560), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(555, 370), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(39, 561), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(555, 556), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(40, 562), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(41, 555), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:19) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(491), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(497), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(563, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(42, 565), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(564, 5), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:4) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(566, 544), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:12) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(567, 368), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(43, 568), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(503, 564), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :73:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(44, 544), // loc(callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :29:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(509), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(503), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :26:28) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(515), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(521), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(527), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(533), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(539), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(545), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(551), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(570, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(45, 579), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(575, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(46, 580), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(576, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(47, 581), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(48, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(571, 569), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(49, 582), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(573, 577), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(50, 583), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(574, 578), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(51, 584), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(576, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(585, 572), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(556), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :54:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(561), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(587, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(52, 589), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(588, 586), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(53, 590), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(365), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 591), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(591, 592), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(54, 593), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(371), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 594), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(594, 595), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 594), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(596, 597), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 594), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(598, 599), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(55, 600), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(377), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 601), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(601, 602), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 601), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(603, 604), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 601), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(605, 606), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(56, 607), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(383), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 608), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(608, 609), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 608), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(610, 611), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 608), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(612, 613), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(57, 614), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(389), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 615), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(615, 616), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 615), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(617, 618), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 615), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(619, 620), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(58, 621), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(395), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 622), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(622, 623), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 622), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(624, 625), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 622), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(626, 627), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(59, 628), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(401), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 629), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(629, 630), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(60, 631), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(407), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 632), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(632, 633), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 632), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(634, 635), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 632), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(636, 637), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(61, 638), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(413), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 639), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(639, 640), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 639), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(641, 642), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 639), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(643, 644), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(62, 645), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(419), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 646), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(646, 647), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(63, 648), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(425), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 649), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(649, 650), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(64, 651), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(431), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 652), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(652, 653), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 652), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(654, 655), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 652), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(656, 657), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(65, 658), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(437), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 659), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(659, 660), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 659), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(661, 662), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 659), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(663, 664), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(66, 665), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(443), // loc(callsite( builtin NondetReg at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :56:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 666), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(666, 667), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 666), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(668, 669), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 666), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(670, 671), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(67, 672), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(449), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 673), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(673, 674), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(68, 675), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(455), // loc(callsite( builtin NondetReg at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :34:30) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(591, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(594, 28), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(677, 678), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(601, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(679, 680), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(608, 26), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(681, 682), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(615, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(683, 684), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(622, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(685, 686), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(629, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(687, 688), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(632, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(689, 690), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(691, 639), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(578, 692), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(69, 693), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(646, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(649, 14), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(694, 695), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(652, 22), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(696, 697), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(659, 21), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(698, 699), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(666, 20), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(700, 701), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(673, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(702, 703), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(704, 676), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(577, 705), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(70, 706), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(632, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(639, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(707, 708), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(709, 646), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(615, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(622, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(711, 712), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(713, 629), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(659, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:17) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(666, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:30) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(715, 716), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(717, 673), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:39) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(594, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(601, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:38) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(719, 720), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(721, 608), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:47) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(591, 19), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(723, 722), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(649, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(725, 652), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(591, 18), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(724, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:45) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(727, 728), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:36) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(729, 714), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:53) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(591, 16), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:63) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Get(676), // loc(callsite( builtin NondetReg at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :47:28) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 732), // loc(callsite( builtin Sub at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :49:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(732, 733), // loc(callsite( builtin Mul at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :49:4) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(71, 734), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :49:36) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(710, 714), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :52:18) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(506, 710), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 735), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :52:18) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(681), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(736, 737), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(73, 738), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Get(566), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(571), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :26:28) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(576), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(581), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(586), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(591), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(596), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(601), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(606), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(739, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(74, 748), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(744, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(75, 749), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(745, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(76, 750), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(77, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(740, 737), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(78, 751), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(742, 746), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(79, 752), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(743, 747), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(80, 753), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(745, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(754, 741), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(656), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :54:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Get(661), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Sub(756, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(81, 758), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(757, 755), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(82, 759), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(611), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(83, 760), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(636), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(84, 761), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(666), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(85, 762), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(72, 732, 86), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(506, 714), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 738), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(88, 748), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(89, 749), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(90, 750), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(91, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(92, 751), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(93, 752), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(94, 753), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(95, 758), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(96, 759), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(686), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(763, 764), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(97, 765), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Get(616), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :26:28) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(621), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(626), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(631), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(641), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(646), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(651), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(760, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(98, 773), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(761, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(99, 774), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(770, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(100, 775), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(101, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(766, 764), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(102, 776), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(768, 771), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(103, 777), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(769, 772), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(104, 778), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(770, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(779, 767), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(671), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Sub(762, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(105, 782), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(781, 780), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(106, 783), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(87, 733, 107), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(601), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(784, 732), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(784, 733), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(785, 786), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(606), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(788, 732), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(788, 733), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(789, 790), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(646), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(792, 733), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(785, 793), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(651), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(795, 733), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(789, 796), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(691), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(787, 798), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(108, 799), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(696), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(791, 800), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(109, 801), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(701), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(794, 802), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(110, 803), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(706), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(797, 804), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(111, 805), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :10:33) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :31:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(676, 32), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :90:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :33:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 806), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :90:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :33:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(113, 726), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :90:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :33:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(114, 724), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :90:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :33:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(154), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(115, 807), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(158), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(116, 808), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(162), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(117, 809), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(166), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(118, 810), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(173), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(119, 811), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(112, 377, 120), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(724, 24), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSUB ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :95:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(114, 812), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSUB ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :95:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :34:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(122, 807), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(123, 808), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(124, 809), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(125, 810), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(126, 811), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(121, 380, 127), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(726, 5), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(113, 813), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(129, 724), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :100:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(711), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 814), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(814, 815), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(130, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(712), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 817), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(817, 818), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(131, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(713), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 820), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(820, 821), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(132, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(714), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 823), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(823, 824), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(133, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(715), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 826), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(826, 827), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(134, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(716), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 829), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(829, 830), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(135, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(717), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 832), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(832, 833), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(136, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(718), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 835), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(835, 836), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(137, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(719), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 838), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(838, 839), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(138, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(720), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 841), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(841, 842), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(139, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(721), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 844), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(844, 845), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(140, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(722), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 847), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(847, 848), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(141, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(723), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 850), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(850, 851), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(142, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(724), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 853), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(853, 854), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(143, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(725), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 856), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(856, 857), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(144, 858), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(726), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 859), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(859, 860), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(145, 861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(817, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(820, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(823, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(826, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(829, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(832, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(835, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(838, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(841, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(844, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(847, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(850, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(853, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(856, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(859, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(814, 862), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(877, 863), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(878, 864), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(879, 865), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(880, 866), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(881, 867), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(882, 868), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(883, 869), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(884, 870), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(885, 871), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(886, 872), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(887, 873), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(888, 874), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(889, 875), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(890, 876), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(798, 891), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(146, 892), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Get(727), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 893), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(893, 894), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(147, 895), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(728), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 896), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(896, 897), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(148, 898), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(729), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 899), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(899, 900), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(149, 901), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(730), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 902), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(902, 903), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(150, 904), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(731), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 905), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(905, 906), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(151, 907), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(732), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 908), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(908, 909), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(152, 910), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(733), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 911), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(911, 912), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(153, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(734), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 914), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(914, 915), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(154, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(735), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 917), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(917, 918), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(155, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(736), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 920), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(920, 921), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(156, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(737), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 923), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(923, 924), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(157, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(738), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 926), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(926, 927), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(158, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(739), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 929), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(929, 930), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(159, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(740), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 932), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(932, 933), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(160, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(741), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 935), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(935, 936), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(161, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(742), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 938), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(938, 939), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(162, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(896, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(899, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(902, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(905, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(908, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(911, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(914, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(917, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(920, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(923, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(926, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(929, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(932, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(935, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(938, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(893, 941), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(956, 942), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(957, 943), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(958, 944), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(959, 945), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(960, 946), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(961, 947), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(962, 948), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(963, 949), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(964, 950), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(965, 951), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(966, 952), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(967, 953), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(968, 954), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(969, 955), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(802, 970), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(163, 971), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Get(743), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 972), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(972, 973), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(164, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(744), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 975), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(975, 976), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(165, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(745), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 978), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(978, 979), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(166, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(746), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 981), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(981, 982), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(167, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(747), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 984), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(984, 985), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(168, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(748), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 987), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(987, 988), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(169, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(749), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 990), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(990, 991), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(170, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(750), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 993), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(993, 994), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(171, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(751), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 996), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(996, 997), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(172, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(752), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 999), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(999, 1000), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(173, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(753), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1002), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1002, 1003), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(174, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(754), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1005), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1005, 1006), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(175, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(755), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1008), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1008, 1009), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(176, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(756), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1011), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1011, 1012), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(177, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(757), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1014), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1014, 1015), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(178, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(758), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1017), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1017, 1018), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(179, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(975, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(978, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(981, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(984, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(987, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(990, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(993, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(996, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(999, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1002, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1005, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1008, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1011, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1014, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1017, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(972, 1020), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1035, 1021), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1036, 1022), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1037, 1023), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1038, 1024), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1039, 1025), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1040, 1026), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1041, 1027), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1042, 1028), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1043, 1029), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1044, 1030), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1045, 1031), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1046, 1032), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1047, 1033), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1048, 1034), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(800, 1049), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(180, 1050), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Get(759), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1051), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1051, 1052), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(181, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(760), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1054), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1054, 1055), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(182, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(761), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1057), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1057, 1058), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(183, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(762), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1060), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1060, 1061), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(184, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(763), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1063), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1063, 1064), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(185, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(764), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1066), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1066, 1067), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(186, 1068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(765), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1069), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1069, 1070), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(187, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(766), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1072), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1072, 1073), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(188, 1074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(767), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1075), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1075, 1076), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(189, 1077), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(768), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1078), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1078, 1079), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(190, 1080), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(769), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1081), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1081, 1082), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(191, 1083), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(770), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1084), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1084, 1085), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(192, 1086), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(771), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1087), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1087, 1088), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(193, 1089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(772), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1090), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1090, 1091), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(194, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(773), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1093), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1093, 1094), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(195, 1095), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(774), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1, 1096), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::Mul(1096, 1097), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))))) +PolyExtStep::AndEqz(196, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(1054, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1057, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1060, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1063, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1066, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1069, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1072, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1075, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1078, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1081, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1084, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1087, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1090, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1093, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1096, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1051, 1099), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1114, 1100), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1115, 1101), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1116, 1102), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1117, 1103), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1118, 1104), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1119, 1105), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1120, 1106), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1121, 1107), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1122, 1108), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1123, 1109), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1124, 1110), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1125, 1111), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1126, 1112), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1127, 1113), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:20) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(804, 1128), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(197, 1129), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(198, 807), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(199, 808), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(200, 809), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(201, 810), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(202, 811), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(128, 383, 203), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(726, 3), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(113, 1130), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(205, 724), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :105:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(206, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(207, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(208, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(209, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(210, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(211, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(212, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(213, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(214, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(215, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(216, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(217, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(218, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(219, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(220, 858), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(221, 861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(222, 892), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(223, 895), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(224, 898), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(225, 901), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(226, 904), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(227, 907), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(228, 910), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(229, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(230, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(231, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(232, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(233, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(234, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(235, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(236, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(237, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(238, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(239, 971), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(240, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(241, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(242, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(243, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(244, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(245, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(246, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(247, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(248, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(249, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(250, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(251, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(252, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(253, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(254, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(255, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(256, 1050), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(257, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(258, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(259, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(260, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(261, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(262, 1068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(263, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(264, 1074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(265, 1077), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(266, 1080), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(267, 1083), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(268, 1086), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(269, 1089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(270, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(271, 1095), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(272, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(273, 1129), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(274, 807), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(275, 808), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(276, 809), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(277, 810), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(278, 811), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(204, 386, 279), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(726, 2), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(113, 1131), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(281, 724), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :110:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(282, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(283, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(284, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(285, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(286, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(287, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(288, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(289, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(290, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(291, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(292, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(293, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(294, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(295, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(296, 858), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(297, 861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(298, 892), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(299, 895), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(300, 898), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(301, 901), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(302, 904), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(303, 907), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(304, 910), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(305, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(306, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(307, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(308, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(309, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(310, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(311, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(312, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(313, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(314, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(315, 971), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(316, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(317, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(318, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(319, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(320, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(321, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(322, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(323, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(324, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(325, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(326, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(327, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(328, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(329, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(330, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(331, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(332, 1050), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(333, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(334, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(335, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(336, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(337, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(338, 1068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(339, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(340, 1074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(341, 1077), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(342, 1080), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(343, 1083), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(344, 1086), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(345, 1089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(346, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(347, 1095), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(348, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(349, 1129), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpAND ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :111:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :37:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(350, 807), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(351, 808), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(352, 809), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(353, 810), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(354, 811), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(280, 389, 355), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(726, 7), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(798, 33), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:19) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1133, 802), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:31) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(800, 16), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:44) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1135, 804), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:55) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(113, 1132), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(357, 724), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :115:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(156), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(807, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(358, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(359, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(814, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1139, 1137), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1134, 1140), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(360, 1141), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1136, 814), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Get(160), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(808, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(361, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(362, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(817, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1145, 1143), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1142, 1146), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(363, 1147), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(364, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(164), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(809, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(365, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(820, 29), // loc(callsite( builtin Mul at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:13) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1148, 37), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1150, 1151), // loc(callsite( builtin Add at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:22) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(800, 1152), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(366, 1153), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(367, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(167), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(810, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(368, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(823, 29), // loc(callsite( builtin Mul at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:13) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1154, 37), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1156, 1157), // loc(callsite( builtin Add at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:22) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(804, 1158), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(369, 1159), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(370, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(179), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(811, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(371, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(826, 29), // loc(callsite( builtin Mul at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:13) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1160, 37), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1162, 1163), // loc(callsite( builtin Add at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:22) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1143, 1164), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(372, 1165), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(820, 824), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:20) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1166, 827), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:32) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(821, 823), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:54) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1168, 826), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:58) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1167, 1169), // loc(callsite( builtin Add at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:43) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1170, 829), // loc(callsite( Reg ( :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:19) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(373, 1171), // loc(callsite( Reg ( :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:19) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(829, 826), // loc(callsite( builtin Add at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:31) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(829, 7), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:47) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1173, 826), // loc(callsite( builtin Mul at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:51) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1172, 1174), // loc(callsite( builtin Sub at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:42) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1175, 832), // loc(callsite( Reg ( :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:30) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(374, 1176), // loc(callsite( Reg ( :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:30) at callsite( OpSLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :116:22) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :38:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(356, 392, 375), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(726, 6), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :121:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(113, 1177), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :121:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(377, 724), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :121:20) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(378, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :122:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(379, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :122:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(380, 1141), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :122:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(381, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :122:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(382, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :122:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(383, 1147), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :122:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(384, 809), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(385, 810), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(386, 811), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(376, 395, 387), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(676, 38), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpADDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :127:18) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :40:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 1178), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpADDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :127:18) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :40:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(389, 726), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpADDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :127:18) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :40:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(390, 807), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(391, 808), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(392, 809), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(393, 810), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(394, 811), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(388, 398, 395), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(798, 802), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :91:26) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :33:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1179, 377), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1134, 380), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(711), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(712), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(713), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(714), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(715), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(716), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(717), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(718), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(719), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(720), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(721), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(722), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(723), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(724), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(725), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(726), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(727), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(728), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(729), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(730), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(731), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(732), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(733), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(734), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(735), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(736), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(737), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(738), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(739), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(740), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(741), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(742), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(1182, 1198), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1183, 1199), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1184, 1200), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1185, 1201), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1186, 1202), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1187, 1203), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1188, 1204), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1189, 1205), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1190, 1206), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1191, 1207), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1192, 1208), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1193, 1209), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1194, 1210), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1195, 1211), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1196, 1212), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1197, 1213), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1215, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1216, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1217, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1218, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1219, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1220, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1221, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1222, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1223, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1224, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1225, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1226, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1227, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1228, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1229, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1214, 1230), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1245, 1231), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1246, 1232), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1247, 1233), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1248, 1234), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1249, 1235), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1250, 1236), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1251, 1237), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1252, 1238), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1253, 1239), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1254, 1240), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1255, 1241), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1256, 1242), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1257, 1243), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1258, 1244), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1259, 7), // loc(callsite( builtin Mul at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:27) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1179, 1260), // loc(callsite( builtin Sub at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:21) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1261, 383), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1179, 1259), // loc(callsite( builtin Sub at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :160:21) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1263, 386), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1259, 389), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1188, 392), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1, 1183), // loc(callsite( builtin Sub at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :120:27) at callsite( OpSLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :122:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :39:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1267, 395), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(798, 730), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( OpADDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :128:26) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :40:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1269, 398), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1180, 1181), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1271, 1262), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1272, 1264), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1273, 1265), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1274, 1266), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1275, 1268), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1276, 1270), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(800, 804), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( OpADD ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :91:26) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :33:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1278, 377), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1136, 380), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(743), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(744), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(745), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(746), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(747), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(748), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(749), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(750), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(751), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(752), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(753), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(754), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(755), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(756), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(757), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(758), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(759), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(760), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(761), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(762), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(763), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(764), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(765), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(766), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(767), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(768), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(769), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(770), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(771), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(772), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(773), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(774), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(1281, 1297), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1282, 1298), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1283, 1299), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1284, 1300), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1285, 1301), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1286, 1302), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1287, 1303), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1288, 1304), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1289, 1305), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1290, 1306), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1291, 1307), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1292, 1308), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1293, 1309), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1294, 1310), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1295, 1311), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1296, 1312), // loc(callsite( builtin Mul at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :148:38) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1314, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1315, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1316, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1317, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1318, 24), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1319, 19), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1320, 25), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1321, 20), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1322, 26), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1323, 21), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1324, 27), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1325, 22), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1326, 28), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1327, 14), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1328, 29), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1313, 1329), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1344, 1330), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1345, 1331), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1346, 1332), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1347, 1333), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1348, 1334), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1349, 1335), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1350, 1336), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1351, 1337), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1352, 1338), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1353, 1339), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1354, 1340), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1355, 1341), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1356, 1342), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1357, 1343), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :149:21) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1358, 7), // loc(callsite( builtin Mul at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:59) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1278, 1359), // loc(callsite( builtin Sub at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:52) at callsite( OpXOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :101:37) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :35:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1360, 383), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1278, 1358), // loc(callsite( builtin Sub at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :160:50) at callsite( OpOR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :106:36) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :36:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1362, 386), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1358, 389), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(800, 731), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( OpADDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :128:26) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :40:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1365, 398), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1279, 1280), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1367, 1361), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1368, 1363), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1369, 1364), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1370, 1366), // loc(callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :32:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(185), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(191), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1372, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(396, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(197), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1375), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1375, 1376), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(397, 1377), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1375, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1378, 1373), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1277, 1379), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(398, 1380), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1371, 1375), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(203), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(209), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1382, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(399, 1384), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(215), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1385), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1385, 1386), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(400, 1387), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1385, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1388, 1383), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1381, 1389), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(401, 1390), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(221), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(227), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1391, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(402, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(233), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1394), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1394, 1395), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(403, 1396), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1394, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1397, 1392), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(522, 1398), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(404, 1399), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(537, 1394), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(239), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(245), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1401, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(405, 1403), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(251), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1404), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1404, 1405), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(406, 1406), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1404, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1407, 1402), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1400, 1408), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(407, 1409), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(257), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Get(263), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :11:20) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1410), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1410, 1412), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(408, 1413), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(718, 1411), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1414, 1412), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(409, 1415), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1410, 718), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(410, 1416), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1410, 1411), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(411, 1417), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1412, 407), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :72:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1418, 718), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:11) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 1418), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:90) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1420, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:102) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(506, 1421), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:85) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1422, 1419), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:106) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(269), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1423, 1424), // loc(callsite( Reg ( :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(412, 1425), // loc(callsite( Reg ( :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(281), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(275), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :26:28) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(287), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(305), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :25:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(311), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(317), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(323), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(1426, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(413, 1433), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1429, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(414, 1434), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1430, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(415, 1435), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(416, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1427, 1424), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(417, 1436), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1430, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1437, 1428), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(329), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :54:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(335), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1439, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(418, 1441), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1440, 1438), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(419, 1442), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1431, 1373), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(420, 1443), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1432, 1383), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(421, 1444), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(31, 422, 422), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(673, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:45) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(727, 1445), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:36) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(722, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:61) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1446, 1447), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:53) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1448, 715), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:72) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1449, 716), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :68:86) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :47:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(389, 813), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :132:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(424, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(425, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(426, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(427, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(428, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(429, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(430, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(431, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(432, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(433, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(434, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(435, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(436, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(437, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(438, 858), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(439, 861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(440, 892), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(441, 895), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(442, 898), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(443, 901), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(444, 904), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(445, 907), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(446, 910), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(447, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(448, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(449, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(450, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(451, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(452, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(453, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(454, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(455, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(456, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(730, 970), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(457, 1451), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(458, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(459, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(460, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(461, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(462, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(463, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(464, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(465, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(466, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(467, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(468, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(469, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(470, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(471, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(472, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(473, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(474, 1050), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(475, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(476, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(477, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(478, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(479, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(480, 1068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(481, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(482, 1074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(483, 1077), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(484, 1080), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(485, 1083), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(486, 1086), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(487, 1089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(488, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(489, 1095), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(490, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(731, 1128), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(491, 1452), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :164:24) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(492, 807), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(493, 808), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(494, 809), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(495, 810), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(496, 811), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(112, 377, 497), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(389, 1130), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :137:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(499, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(500, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(501, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(502, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(503, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(504, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(505, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(506, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(507, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(508, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(509, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(510, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(511, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(512, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(513, 858), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(514, 861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(515, 892), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(516, 895), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(517, 898), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(518, 901), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(519, 904), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(520, 907), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(521, 910), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(522, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(523, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(524, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(525, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(526, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(527, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(528, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(529, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(530, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(531, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(532, 1451), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(533, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(534, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(535, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(536, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(537, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(538, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(539, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(540, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(541, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(542, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(543, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(544, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(545, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(546, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(547, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(548, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(549, 1050), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(550, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(551, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(552, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(553, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(554, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(555, 1068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(556, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(557, 1074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(558, 1077), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(559, 1080), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(560, 1083), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(561, 1086), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(562, 1089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(563, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(564, 1095), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(565, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(566, 1452), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :159:24) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(567, 807), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(568, 808), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(569, 809), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(570, 810), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(571, 811), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(498, 380, 572), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(389, 1131), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :142:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(574, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(575, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(576, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(577, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(578, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(579, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(580, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(581, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(582, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(583, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(584, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(585, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(586, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(587, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(588, 858), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(589, 861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(590, 892), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(591, 895), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(592, 898), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(593, 901), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(594, 904), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(595, 907), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(596, 910), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(597, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(598, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(599, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(600, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(601, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(602, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(603, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(604, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(605, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(606, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(607, 1451), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:24) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(608, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(609, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(610, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(611, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(612, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(613, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(614, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(615, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(616, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(617, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(618, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(619, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(620, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(621, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(622, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(623, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :144:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(624, 1050), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :145:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(625, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(626, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(627, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(628, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(629, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(630, 1068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(631, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(632, 1074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(633, 1077), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(634, 1080), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(635, 1083), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(636, 1086), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(637, 1089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(638, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(639, 1095), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(640, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :146:24) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(641, 1452), // loc(callsite( BitwiseAndU16 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :147:6) at callsite( BitwiseAnd ( zirgen/circuit/rv32im/v2/dsl/u32.zir :155:53) at callsite( OpANDI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :143:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :51:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(642, 807), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(643, 808), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(644, 809), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(645, 810), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(646, 811), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(573, 383, 647), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1133, 730), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:31) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1135, 731), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:55) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:31) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(389, 1132), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :147:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(649, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(650, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1453, 1140), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(651, 1455), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1454, 814), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(652, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(653, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1456, 1146), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(654, 1457), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(655, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(656, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(657, 1153), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(658, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(659, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(731, 1158), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(660, 1458), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(661, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(662, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(663, 1165), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(664, 1171), // loc(callsite( Reg ( :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:19) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(665, 1176), // loc(callsite( Reg ( :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:30) at callsite( OpSLTI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :148:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :52:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(648, 386, 666), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(389, 1177), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :153:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(668, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :154:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(669, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :154:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(670, 1455), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :154:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(671, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :154:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(672, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :154:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(673, 1457), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpSLTIU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :154:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :53:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(674, 809), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(675, 810), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(676, 811), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(667, 389, 677), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(676, 39), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(798, 802), // loc(callsite( builtin Sub at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:25) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(800, 804), // loc(callsite( builtin Sub at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(0, 1459), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(679, 726), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :159:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(680, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1460, 817), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1462, 815), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(681, 1463), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(814, 1460), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(682, 1464), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(814, 817), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(683, 1465), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(684, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1461, 823), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1466, 821), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(685, 1467), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(820, 1461), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(686, 1468), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(820, 823), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(687, 1469), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(814, 820), // loc(callsite( builtin Mul at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :114:27) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1470, 826), // loc(callsite( Reg ( :6:7) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :114:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(688, 1471), // loc(callsite( Reg ( :6:7) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :114:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :160:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(689, 807), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(690, 808), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(691, 809), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(692, 810), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(693, 811), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(678, 392, 694), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(726, 1), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :165:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(679, 1472), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :165:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(696, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(697, 1463), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(698, 1464), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(699, 1465), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :112:22) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(700, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(701, 1467), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(702, 1468), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(703, 1469), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :113:23) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(704, 1471), // loc(callsite( Reg ( :6:7) at callsite( CmpEqual ( zirgen/circuit/rv32im/v2/dsl/u32.zir :114:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :166:19) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(705, 807), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(706, 808), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(707, 809), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(708, 810), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(709, 811), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(695, 395, 710), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(679, 813), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :171:18) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(712, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(713, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(714, 1141), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(715, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(716, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(717, 1147), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(718, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(719, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(720, 1153), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(721, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(722, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(723, 1159), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(724, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(725, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(726, 1165), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(727, 1171), // loc(callsite( Reg ( :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:19) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(728, 1176), // loc(callsite( Reg ( :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:30) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :172:22) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(711, 398, 729), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1269, 1260), // loc(callsite( builtin Sub at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:21) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1473, 377), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1269, 1259), // loc(callsite( builtin Sub at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :160:21) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1475, 380), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1259, 383), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1188, 386), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1267, 389), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1474, 1476), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1480, 1477), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1481, 1478), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1482, 1479), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1365, 1359), // loc(callsite( builtin Sub at callsite( BitwiseXor ( zirgen/circuit/rv32im/v2/dsl/u32.zir :165:52) at callsite( OpXORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :133:37) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :49:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1484, 377), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1365, 1358), // loc(callsite( builtin Sub at callsite( BitwiseOr ( zirgen/circuit/rv32im/v2/dsl/u32.zir :160:50) at callsite( OpORI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :138:36) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :50:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1486, 380), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1358, 383), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1485, 1487), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1489, 1488), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(368, 1450), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :84:12) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1186, 1491), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1186), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1493, 507), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1492, 1494), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1495, 392), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1493, 1491), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :167:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1493), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :167:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1498, 507), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :167:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1497, 1499), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :167:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1500, 395), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1188, 1491), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :173:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1188), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :173:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1503, 507), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :173:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1502, 1504), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :173:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1505, 398), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(519, 1496), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1507, 1501), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1508, 1506), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(370, 731), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :84:12) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1186, 1510), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1493, 370), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1511, 1512), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBEQ ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :161:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :54:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1513, 392), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1493, 1510), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :167:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1498, 370), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :167:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1515, 1516), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBNE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :167:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :55:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1517, 395), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1188, 1510), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :173:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1503, 370), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :173:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1519, 1520), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLT ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :173:9) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :56:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1521, 398), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(534, 1514), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1523, 1518), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1524, 1522), // loc(callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :48:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(730, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(731, 1377), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1483, 1379), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(732, 1526), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1490, 1375), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(733, 1384), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(734, 1387), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1527, 1389), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(735, 1528), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(736, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(737, 1396), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1509, 1398), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(738, 1529), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1525, 1394), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(739, 1403), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(740, 1406), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1530, 1408), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(741, 1531), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(742, 1413), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(743, 1415), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(744, 1416), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(745, 1417), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1412, 404), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :72:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1532, 718), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:11) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 1532), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:90) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1534, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:102) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(506, 1535), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:85) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1536, 1533), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:106) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1537, 1424), // loc(callsite( Reg ( :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(746, 1538), // loc(callsite( Reg ( :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(747, 1433), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(748, 1434), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(749, 1435), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(750, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(751, 1436), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(752, 1441), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(753, 1442), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(754, 1443), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(755, 1444), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc1 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :58:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :75:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(423, 425, 756), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(386, 389), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1539, 392), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1540, 395), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(511, 512), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(526, 527), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(368, 398), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(726, 22), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(694, 1545), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(629, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1546, 1547), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:33) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1548, 1447), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:51) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1549, 711), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:70) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1550, 712), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :71:85) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(591, 40), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :72:7) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1552, 690), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :72:17) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1553, 639), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :72:36) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MiscInput ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :9:32) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :63:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(726, 4), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(679, 1555), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :177:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(758, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(759, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(760, 1141), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(761, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(762, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(763, 1147), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :133:24) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(764, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(765, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(766, 1153), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :134:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(767, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(768, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(769, 1159), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :135:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(770, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :125:24) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(771, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :126:34) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(772, 1165), // loc(callsite( GetSignU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :127:11) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :136:20) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(773, 1171), // loc(callsite( Reg ( :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :138:19) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(774, 1176), // loc(callsite( Reg ( :6:7) at callsite( CmpLessThan ( zirgen/circuit/rv32im/v2/dsl/u32.zir :140:30) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :178:22) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(112, 377, 775), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(679, 1130), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :183:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(777, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(778, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(779, 1141), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(780, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(781, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(782, 1147), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :184:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(783, 809), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(784, 810), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(785, 811), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(776, 380, 786), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(679, 1131), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :189:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(788, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(789, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(790, 1141), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(791, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(792, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(793, 1147), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :190:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(794, 809), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(795, 810), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(796, 811), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(787, 383, 797), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(676, 41), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :91:19) at callsite( OpJAL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :195:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :68:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 1556), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :91:19) at callsite( OpJAL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :195:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :68:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(799, 807), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(800, 808), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(801, 809), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(802, 810), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(803, 811), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(798, 386, 804), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(676, 42), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpJALR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :202:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :69:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 1557), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpJALR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :202:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :69:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(806, 726), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpJALR ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :202:18) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :69:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(807, 807), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(808, 808), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(809, 809), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(810, 810), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(811, 811), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(805, 389, 812), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(676, 43), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :91:19) at callsite( OpLUI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :209:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :70:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 1558), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :91:19) at callsite( OpLUI ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :209:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :70:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(814, 807), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(815, 808), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(816, 809), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(817, 810), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(818, 811), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(813, 392, 819), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(676, 44), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :91:19) at callsite( OpAUIPC ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :214:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 1559), // loc(callsite( VerifyOpcode ( zirgen/circuit/rv32im/v2/dsl/inst.zir :91:19) at callsite( OpAUIPC ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :214:16) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(821, 807), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(822, 808), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(823, 809), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(824, 810), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(825, 811), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(820, 395, 826), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(676, 45), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpECALL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :220:20) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 1560), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpECALL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :220:20) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(828, 726), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpECALL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :220:20) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(829, 724), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpECALL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :220:20) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :72:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(830, 807), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(831, 808), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(832, 809), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(833, 810), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(834, 811), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(827, 398, 835), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(698, 392), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(368, 698), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( OpAUIPC ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :215:26) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1562, 395), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1542, 1561), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1564, 1563), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(578, 392), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(370, 578), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( OpAUIPC ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :215:26) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :71:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1567, 395), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1543, 1566), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1569, 1568), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1503, 1491), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :179:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1503), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :179:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1572, 507), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :179:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1571, 1573), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :179:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1574, 377), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1267, 1491), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :185:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1267), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :185:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1577, 507), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :185:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1576, 1578), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :185:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1579, 380), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1577, 1491), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :191:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1577), // loc(callsite( builtin Sub at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:24) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :191:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1582, 507), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:32) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :191:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1581, 1583), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :101:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :191:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1584, 383), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(368, 1551), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( OpJAL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :198:12) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :68:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1586, 386), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1269, 389), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1575, 1580), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1589, 1585), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1590, 1587), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1591, 1588), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1592, 513), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1593, 514), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1594, 1544), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1503, 1510), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :179:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1572, 370), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :179:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1596, 1597), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGE ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :179:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :65:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1598, 377), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1267, 1510), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :185:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1577, 370), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :185:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1600, 1601), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBLTU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :185:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :66:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1602, 380), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1577, 1510), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:8) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :191:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1582, 370), // loc(callsite( builtin Mul at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:33) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :191:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1604, 1605), // loc(callsite( builtin Add at callsite( CondDenormed ( zirgen/circuit/rv32im/v2/dsl/u32.zir :102:17) at callsite( CmpOp ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :83:26) at callsite( OpBGEU ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :191:9) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :67:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1606, 383), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(370, 1554), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( OpJAL ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :198:12) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :68:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1608, 386), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1365, 389), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1599, 1603), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1611, 1607), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1612, 1609), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1613, 1610), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1614, 528), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1615, 529), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(1616, 530), // loc(callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :64:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(836, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(837, 1377), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1565, 1379), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(838, 1618), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1570, 1375), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(839, 1384), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(840, 1387), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1619, 1389), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(841, 1620), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :23:30) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(842, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(843, 1396), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1595, 1398), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(844, 1621), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1617, 1394), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(845, 1403), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(846, 1406), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1622, 1408), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(847, 1623), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(848, 1413), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(849, 1415), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(850, 1416), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(851, 1417), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1412, 1541), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :72:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1624, 718), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:11) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 1624), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:90) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1626, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:102) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(506, 1627), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:85) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1628, 1625), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:106) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1629, 1424), // loc(callsite( Reg ( :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(852, 1630), // loc(callsite( Reg ( :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(853, 1433), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(854, 1434), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(855, 1435), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(856, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(857, 1436), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(858, 1441), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(859, 1442), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(860, 1443), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(861, 1444), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :25:11) at callsite( Misc2 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :74:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :76:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(757, 428, 862), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Sub(539, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 1631), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(594, 542), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(864, 1632), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :23:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(865, 497), // loc(callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :8:21) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(1, 552), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(552, 1633), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 552), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1634, 1635), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 552), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1636, 1637), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(866, 1638), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(555, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(867, 1639), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(556, 502), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(868, 1640), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 563), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(563, 1641), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(869, 1642), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(370, 564), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1643, 1641), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(870, 1644), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(563, 370), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(871, 1645), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(563, 564), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(872, 1646), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(873, 563), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:19) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(571, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(874, 1647), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(570, 5), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:4) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1648, 552), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:12) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1649, 368), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(875, 1650), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(503, 570), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :73:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(876, 552), // loc(callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :29:17) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(573, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(877, 1652), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(577, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(878, 1653), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(578, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(879, 1654), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(880, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(572, 1651), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(881, 1655), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(575, 587), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(882, 1656), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(576, 588), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(883, 1657), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(578, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1658, 574), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(739, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(884, 1660), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(740, 1659), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(885, 1661), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(886, 603), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(887, 614), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(888, 621), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(889, 628), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7, 629), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(631, 1662), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 629), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1663, 1664), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(890, 1665), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(891, 638), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(892, 641), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7, 646), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(648, 1666), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 646), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1667, 1668), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(893, 1669), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7, 649), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(651, 1670), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 649), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1671, 1672), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(894, 1673), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(895, 654), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(896, 661), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(897, 672), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7, 673), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(675, 1674), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 673), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1675, 1676), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(898, 1677), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 676), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(676, 1678), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 676), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1679, 1680), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 676), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1681, 1682), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(899, 1683), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(900, 546), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(601, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(608, 28), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1684, 1685), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(615, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1686, 1687), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(622, 26), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1688, 1689), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(629, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1690, 1691), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(632, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1692, 1693), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(639, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1694, 1695), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(646, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1696, 1697), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1698, 649), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(588, 1699), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(901, 1700), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(652, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(659, 14), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1701, 1702), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(666, 22), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1703, 1704), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(673, 21), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1705, 1706), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(676, 20), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1707, 1708), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(544, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1709, 1710), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1711, 551), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(587, 1712), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(902, 1713), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(646, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(649, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1714, 1715), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1716, 652), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(629, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(632, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1718, 1719), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1720, 639), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(673, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:17) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(676, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:30) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1722, 1723), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1724, 544), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:39) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(608, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(615, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:38) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1726, 1727), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1728, 622), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:47) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(601, 19), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1730, 1729), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(659, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1732, 666), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :10:32) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 764), // loc(callsite( builtin Sub at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :49:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(764, 1734), // loc(callsite( builtin Mul at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :49:4) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(903, 1735), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :49:36) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1717, 1721), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :52:18) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(506, 1717), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 1736), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :52:18) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1737, 798), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(905, 1738), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(741, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(906, 1739), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(746, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(907, 1740), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(747, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(908, 1741), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(909, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(742, 798), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(910, 1742), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(744, 760), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(911, 1743), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(745, 766), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(912, 1744), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(747, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(1745, 743), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(913, 782), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(781, 1746), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(914, 1747), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(915, 767), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(916, 771), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(917, 732), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(904, 764, 918), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(506, 1721), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 1738), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(920, 1739), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(921, 1740), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(922, 1741), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(923, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(924, 1742), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(925, 1743), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(926, 1744), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(927, 782), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(928, 1747), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(1748, 800), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(929, 1749), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(767, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(930, 1750), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(771, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(931, 1751), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(772, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(932, 1752), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(933, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(768, 800), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(934, 1753), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(761, 756), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(935, 1754), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(770, 757), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(936, 1755), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(772, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(1756, 769), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(732, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(937, 1758), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(737, 1757), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(938, 1759), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(919, 1734, 939), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(611), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(1760, 764), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1760, 1734), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1761, 1762), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(616), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(1764, 764), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1764, 1734), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1765, 1766), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(656), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(1768, 1734), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1761, 1769), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(661), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(1771, 1734), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1765, 1772), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1763, 802), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(940, 1774), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1767, 804), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(941, 1775), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1770, 814), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(942, 1776), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1773, 817), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(943, 1777), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( MulInput ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :11:33) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(551, 32), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1733, 1), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 1778), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(945, 1779), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(946, 1731), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :49:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(947, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(948, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(949, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(950, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(951, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(823, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(826, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(829, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(832, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(820, 1780), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1784, 1781), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1785, 1782), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1786, 1783), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(952, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1137, 24), // loc(callsite( builtin Mul at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:4) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1788, 1787), // loc(callsite( builtin Add at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:16) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1789, 814), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(953, 1790), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(820, 7), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :42:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1791, 821), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :42:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(823, 1792), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1793, 5), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(824, 1792), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1794, 1795), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(826, 1796), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1797, 23), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(827, 1796), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1798, 1799), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1800, 835), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(954, 1801), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(829, 835), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1802, 20), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(830, 835), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1803, 1804), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(833, 1805), // loc(callsite( builtin Mul at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:27) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1806, 838), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(955, 1807), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(832, 1805), // loc(callsite( builtin Mul at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:22) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1808, 841), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(956, 1809), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :50:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1375, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(957, 1810), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1383, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(958, 1811), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(959, 1393), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1394, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(960, 1812), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1402, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(961, 1813), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(962, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1385, 20), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:17) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1382, 1814), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:12) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(802, 1815), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(963, 1816), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1404, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:18) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1392, 1817), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(844, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1818, 1819), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(804, 1820), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(964, 1821), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1404, 37), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:9) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(844, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1822, 1823), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1401, 1824), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(965, 1825), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1410, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(966, 1826), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1424, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(967, 1827), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1426, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(968, 1828), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(293), // loc(callsite( builtin NondetReg at callsite( ArgU8 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :9:29) at callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :18:16) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(299), // loc(callsite( builtin NondetReg at callsite( ArgU8 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :10:27) at callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :18:16) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1829, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(969, 1831), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(970, 1434), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(971, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1427, 20), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:17) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1411, 1832), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:12) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(838, 1833), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(972, 1834), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1430, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:18) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1428, 1835), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(847, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1836, 1837), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(841, 1838), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(973, 1839), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1430, 37), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:9) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(847, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1840, 1841), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1830, 1842), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(974, 1843), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(975, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(976, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(850, 29), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:13) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1143, 37), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:30) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1844, 1845), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:21) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1846), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(977, 1847), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1382, 1411), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1382, 1427), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1385, 1411), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:36) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1849, 1850), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1851, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:8) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1848, 1852), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(978, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1431, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(979, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(980, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(981, 858), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(856, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1855, 853), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1856, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1432, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1857, 1858), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1859, 1148), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1853, 1860), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(982, 1861), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1856, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1862, 1432), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1382, 1428), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1863, 1864), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :134:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1385, 1427), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:27) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1865, 1866), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1392, 1411), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:43) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1867, 1868), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1382, 1830), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1385, 1428), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:36) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1870, 1871), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1392, 1427), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:52) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1872, 1873), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:44) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1401, 1411), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:68) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1874, 1875), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:60) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1876, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:8) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1869, 1877), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(983, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(984, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(985, 861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(986, 895), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(893, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1879, 859), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1880, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1440, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1881, 1882), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1883, 1154), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1878, 1884), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(987, 1885), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1880, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1886, 1440), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1887, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1385, 1830), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1888, 1889), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1392, 1428), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:27) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1890, 1891), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1401, 1427), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:43) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1892, 1893), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1392, 1830), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1401, 1428), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:36) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1895, 1896), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1897, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:8) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1894, 1898), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(988, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(341), // loc(callsite( builtin NondetReg at callsite( ArgU8 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :9:29) at callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :18:16) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1900, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(989, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(990, 898), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(991, 901), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(899, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1902, 896), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1903, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(538, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1904, 1905), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1906, 1160), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1899, 1907), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(992, 1908), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1903, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1909, 538), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1910, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1401, 1830), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :153:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1911, 1912), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(993, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1913, 1373), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1914, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(994, 904), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(995, 907), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(905, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1916, 902), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(1915, 1917), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(996, 1918), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(944, 377, 997), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(551, 38), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 1919), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(999, 1779), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1000, 1731), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :56:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1001, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1002, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1003, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1004, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1005, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1006, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1789, 1721), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1007, 1920), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1008, 1801), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1009, 1807), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1010, 1809), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :57:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1011, 1810), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1012, 1811), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1013, 1393), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1014, 1812), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1015, 1813), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1016, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1017, 1816), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1018, 1821), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1019, 1825), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1020, 1826), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1021, 1827), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1022, 1828), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1023, 1831), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1024, 1434), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1025, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1026, 1834), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1027, 1839), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1028, 1843), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1029, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1030, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1031, 1847), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1032, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1033, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1034, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1035, 858), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1036, 1861), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1037, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1038, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1039, 861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1040, 895), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1041, 1885), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1042, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1043, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1044, 898), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1045, 901), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1046, 1908), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1047, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1048, 904), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1049, 907), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1050, 1918), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLLI ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :58:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :27:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(998, 380, 1051), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1731, 1), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(945, 1733), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1053, 1921), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :63:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1054, 1810), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1055, 1811), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1056, 1393), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1057, 1812), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1058, 1813), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1059, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1060, 1816), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1818, 1150), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(804, 1922), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1061, 1923), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(820, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1822, 1924), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1401, 1925), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1062, 1926), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1063, 1826), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1064, 1827), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1065, 1828), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1066, 1831), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1067, 1434), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1068, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(814, 1833), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1069, 1927), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1836, 1156), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(817, 1928), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1070, 1929), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(823, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1840, 1930), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1830, 1931), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1071, 1932), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1072, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1073, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1137, 37), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:30) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1162, 1933), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:21) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1934), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1074, 1935), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1075, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1076, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1077, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1078, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(832, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1936, 829), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1937, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1938, 1858), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1939, 1143), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1853, 1940), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1079, 1941), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1937, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1942, 1432), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1943, 1864), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :134:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1944, 1866), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1945, 1868), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1946, 1877), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1080, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1081, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1082, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1083, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(838, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1948, 835), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1949, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1950, 1882), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1951, 1148), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1947, 1952), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1084, 1953), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1949, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1954, 1440), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1955, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1956, 1889), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1957, 1891), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1958, 1893), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1959, 1898), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1085, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1086, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1087, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1088, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(844, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1961, 841), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1962, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1963, 1905), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1964, 1154), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1960, 1965), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1089, 1966), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1962, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1967, 538), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1968, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1969, 1912), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1090, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1970, 1160), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1971, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1091, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1092, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(850, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1973, 847), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(1972, 1974), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1093, 1975), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1094, 1372), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(1052, 383, 1095), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(946, 1921), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :69:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1097, 1810), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1098, 1811), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1099, 1393), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1100, 1812), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1101, 1813), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1102, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1103, 1816), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1104, 1923), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1105, 1926), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1106, 1826), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1107, 1827), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1108, 1828), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1109, 1831), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1110, 1434), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1111, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1112, 1927), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1113, 1929), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1114, 1932), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1115, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1116, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1117, 1935), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1118, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1119, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1120, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1121, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1122, 1941), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1123, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1124, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1125, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1126, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1127, 1953), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1815, 823), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:40) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1956, 1976), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:8) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1833, 820), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:75) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1977, 1978), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:47) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1979, 1889), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1980, 1891), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1981, 1893), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1982, 1898), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1128, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1129, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1130, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1131, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1983, 1965), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1132, 1984), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1401, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:30) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1392, 1985), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:22) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1986, 823), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:40) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1969, 1987), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:8) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1830, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:65) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1428, 1989), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:57) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1990, 820), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:75) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1988, 1991), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:47) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1992, 1912), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1133, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1993, 1160), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1994, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1134, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1135, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(1995, 1974), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1136, 1996), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1137, 1372), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(1096, 386, 1138), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1733, 7), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(945, 1997), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1140, 1921), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :75:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1141, 1810), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1142, 1811), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1143, 1393), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1144, 1812), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1145, 1813), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1146, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1147, 1816), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1148, 1923), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1149, 1926), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1150, 1826), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1151, 1827), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1152, 1828), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1153, 1831), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1154, 1434), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1155, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1156, 1927), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1157, 1929), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1158, 1932), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1159, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1160, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1161, 1935), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1162, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1163, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1164, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1165, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1166, 1941), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1167, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1168, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1169, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1170, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1171, 1953), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1956, 1978), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:47) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1998, 1889), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1999, 1891), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2000, 1893), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2001, 1898), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1172, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1173, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1174, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1175, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(2002, 1965), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1176, 2003), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1969, 1991), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:47) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2004, 1912), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1177, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2005, 1160), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2006, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1178, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1179, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(2007, 1974), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1180, 2008), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHSU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :76:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :30:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1181, 1372), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(1139, 389, 1182), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1733, 6), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(945, 2009), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1184, 1921), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :81:20) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1185, 1810), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1186, 1811), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1187, 1393), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1188, 1812), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1189, 1813), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1190, 822), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1191, 1816), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1192, 1923), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1193, 1926), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1194, 1826), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1195, 1827), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1196, 1828), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1197, 1831), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1198, 1434), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1199, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1200, 1927), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1201, 1929), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1202, 1932), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1203, 828), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1204, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1205, 1935), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1206, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1207, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1208, 831), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1209, 834), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1210, 1941), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1211, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1212, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1213, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1214, 840), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1215, 1953), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1216, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1217, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1218, 843), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1219, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1220, 1966), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1221, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1222, 849), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1223, 852), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1224, 1975), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULHU ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :82:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :31:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1225, 1372), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(1183, 392, 1226), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(0, 17), // loc(callsite( IllegalMulOp ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :18:6) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :32:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(1228, 807), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1229, 808), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1230, 809), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1231, 810), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1232, 811), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1233, 1372), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1234, 1375), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1235, 1383), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1236, 1391), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1237, 1394), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1238, 1402), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1239, 1410), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1240, 1424), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1241, 1426), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1242, 1829), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1243, 1429), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1244, 1431), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1245, 1439), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1246, 1900), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(1227, 395, 1247), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(1248, 398, 1247), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(164), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpSLL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :51:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(2010, 377), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(2010, 380), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(160), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMUL ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :64:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :28:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(2013, 383), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(167), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(2015, 386), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(2015, 389), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(2015, 392), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2011, 2012), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2019, 2014), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2020, 2016), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2021, 2017), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2022, 2018), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(2015, 377), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(2015, 380), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(2010, 383), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(179), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoMul ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :42:29) at callsite( OpMULH ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :70:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2027, 386), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(2027, 389), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(2027, 392), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2024, 2025), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2031, 2026), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2032, 2028), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2033, 2029), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2034, 2030), // loc(callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1249, 910), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1725, 911), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2036, 909), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1250, 2037), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(908, 1725), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1251, 2038), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(908, 911), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1252, 2039), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(909, 1725), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:11) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 909), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:90) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(2041, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:102) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(506, 2042), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:85) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2043, 2040), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:106) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(2044, 914), // loc(callsite( Reg ( :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1253, 2045), // loc(callsite( Reg ( :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(920, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1254, 2046), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(932, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1255, 2047), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(935, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1256, 2048), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1257, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(917, 914), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1258, 2049), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(935, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2050, 923), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(975, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1259, 2052), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(978, 2051), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1260, 2053), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(938, 2023), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1261, 2054), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(972, 2035), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1262, 2055), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(981, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1263, 2056), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1264, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(987, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2057, 984), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(507, 2058), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(1265, 2059), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(370, 987), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(990, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1266, 2061), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1267, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(996, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2062, 993), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(2060, 2063), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(1268, 2064), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mul0 ( zirgen/circuit/rv32im/v2/dsl/inst_mul.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :77:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(863, 431, 1269), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Sub(555, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 2065), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(563, 542), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(1271, 2066), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :23:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(1272, 497), // loc(callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :8:21) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(1, 743), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(743, 2067), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 743), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2068, 2069), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 743), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2070, 2071), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1273, 2072), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1274, 749), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(745, 502), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1275, 2073), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 746), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(746, 2074), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1276, 2075), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(370, 747), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2076, 2074), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1277, 2077), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(746, 370), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1278, 2078), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(746, 747), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1279, 2079), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1280, 746), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:19) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(760, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1281, 2080), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(766, 5), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:4) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2081, 743), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:12) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2082, 368), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1282, 2083), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(503, 766), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :73:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1283, 743), // loc(callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :29:17) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(768, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1284, 2085), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1285, 1751), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1286, 1752), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1287, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(767, 2084), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1288, 2086), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1289, 1754), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1290, 1755), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1291, 782), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(781, 1757), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1292, 2087), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 564), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(564, 2088), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1293, 2089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 571), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(571, 2090), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 571), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2091, 2092), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 571), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2093, 2094), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1294, 2095), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 570), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(570, 2096), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 570), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2097, 2098), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 570), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2099, 2100), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1295, 2101), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 572), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(572, 2102), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 572), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2103, 2104), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 572), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2105, 2106), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1296, 2107), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 573), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(573, 2108), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 573), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2109, 2110), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 573), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2111, 2112), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1297, 2113), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 574), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(574, 2114), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 574), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2115, 2116), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 574), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2117, 2118), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1298, 2119), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 575), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(575, 2120), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1299, 2121), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 576), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(576, 2122), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 576), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2123, 2124), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 576), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2125, 2126), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1300, 2127), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 577), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(577, 2128), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 577), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2129, 2130), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 577), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2131, 2132), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1301, 2133), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 578), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(578, 2134), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1302, 2135), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 587), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(587, 2136), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1303, 2137), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 588), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(588, 2138), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 588), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2139, 2140), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 588), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2141, 2142), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1304, 2143), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 739), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(739, 2144), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 739), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2145, 2146), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 739), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2147, 2148), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1305, 2149), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 740), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(740, 2150), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 740), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2151, 2152), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 740), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2153, 2154), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1306, 2155), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 741), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(741, 2156), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1307, 2157), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(564, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(571, 28), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2158, 2159), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(570, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2160, 2161), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(572, 26), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2162, 2163), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(573, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2164, 2165), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(574, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2166, 2167), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(575, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2168, 2169), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(576, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2170, 2171), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2172, 577), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(757, 2173), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1308, 2174), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(578, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(587, 14), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2175, 2176), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(588, 22), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2177, 2178), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(739, 21), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2179, 2180), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(740, 20), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2181, 2182), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(741, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2183, 2184), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2185, 742), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(756, 2186), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1309, 2187), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(576, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(577, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2188, 2189), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2190, 578), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(573, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(574, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2192, 2193), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2194, 575), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(739, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:17) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(740, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:30) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2196, 2197), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2198, 741), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:39) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(571, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2200, 1648), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2201, 572), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:47) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(564, 19), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2203, 2202), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(587, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2205, 588), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :10:32) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1310, 861), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :49:36) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(2191, 2195), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :52:18) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(506, 2191), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 2207), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :52:18) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(2208, 893), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1312, 2209), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(732, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1313, 2210), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(802, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1314, 2211), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(804, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1315, 2212), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1316, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(737, 893), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1317, 2213), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(798, 814), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1318, 2214), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(800, 817), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1319, 2215), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(804, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(2216, 764), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(847, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1320, 2218), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(850, 2217), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1321, 2219), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1322, 820), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1323, 835), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1324, 853), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(1311, 859, 1325), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(506, 2195), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 2209), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1327, 2210), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1328, 2211), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1329, 2212), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1330, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1331, 2213), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1332, 2214), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1333, 2215), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1334, 2218), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1335, 2219), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(2220, 896), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1336, 2221), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(820, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1337, 2222), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(835, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1338, 2223), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(838, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1339, 2224), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1340, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(823, 896), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1341, 2225), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(829, 841), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1342, 2226), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(832, 844), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1343, 2227), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(838, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(2228, 826), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(853, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1344, 2230), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(856, 2229), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1345, 2231), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(1326, 860, 1346), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1182, 859), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1182, 860), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2232, 2233), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1183, 859), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1183, 860), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2235, 2236), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1191, 860), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2232, 2238), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1192, 860), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2235, 2240), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(2234, 899), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1347, 2242), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2237, 902), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1348, 2243), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2239, 905), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1349, 2244), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2241, 908), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1350, 2245), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( DivInput ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :11:33) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :24:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(742, 32), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :134:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(2206, 4), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :134:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(902, 29), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :106:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(0, 2246), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :134:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1352, 2247), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :134:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1353, 2204), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :134:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1354, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1355, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1356, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1357, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1358, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(914, 7), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(917, 5), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(920, 12), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(923, 23), // loc(callsite( builtin Mul at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(911, 2249), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2253, 2250), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2254, 2251), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2255, 2252), // loc(callsite( builtin Add at callsite( FromBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :29:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :39:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1359, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1788, 2256), // loc(callsite( builtin Add at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:16) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2257, 905), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1360, 2258), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(911, 7), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :42:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2259, 912), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :42:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(914, 2260), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2261, 5), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(915, 2260), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2262, 2263), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :43:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(917, 2264), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2265, 23), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(918, 2264), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2266, 2267), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:21) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2268, 926), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1361, 2269), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(920, 926), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:4) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2270, 20), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:11) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(921, 926), // loc(callsite( builtin Mul at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2271, 2272), // loc(callsite( builtin Add at callsite( CondMul ( zirgen/circuit/rv32im/v2/dsl/po2.zir :33:16) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :45:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(924, 2273), // loc(callsite( builtin Mul at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2274, 929), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1362, 2275), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(923, 2273), // loc(callsite( builtin Mul at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:22) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2276, 932), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1363, 2277), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :135:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1364, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1365, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :57:27) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1366, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1367, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1368, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(353), // loc(callsite( builtin NondetReg at callsite( ArgU8 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :9:29) at callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :18:16) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(2278, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1369, 2279), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(591, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1370, 2280), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1371, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1440, 20), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:17) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1432, 2281), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:12) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(935, 2282), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1372, 2283), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(594, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:18) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(538, 2284), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(972, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2285, 2286), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(938, 2287), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1373, 2288), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(594, 37), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:9) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(972, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2289, 2290), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(539, 2291), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1374, 2292), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(601, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1375, 2293), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(615, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1376, 2294), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(629, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1377, 2295), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(639, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1378, 2296), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(649, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1379, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1380, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(622, 20), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:17) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(608, 2298), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:12) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(929, 2299), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1381, 2300), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(652, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:18) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(632, 2301), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(975, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2302, 2303), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(932, 2304), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1382, 2305), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(652, 37), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:9) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(975, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2306, 2307), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(646, 2308), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1383, 2309), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1384, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1385, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(978, 29), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2310, 1157), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:21) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1148, 2311), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1386, 2312), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1432, 608), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1143, 2313), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :127:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1432, 622), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1440, 608), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:36) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2315, 2316), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2317, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :129:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2314, 2318), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1387, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(659, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1388, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1389, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1390, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(984, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(2321, 981), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2322, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(666, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2323, 2324), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2325, 1160), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2319, 2326), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1391, 2327), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2322, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2328, 666), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1148, 2329), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :133:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1432, 632), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2330, 2331), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :134:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1440, 622), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:27) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2332, 2333), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(538, 608), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:43) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2334, 2335), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1432, 646), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1440, 632), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:36) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2337, 2338), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(538, 622), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:52) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2339, 2340), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:44) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(539, 608), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:68) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2341, 2342), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:60) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2343, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :136:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2336, 2344), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1392, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(673, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1393, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1394, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1395, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(990, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(2347, 987), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2348, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(676, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2349, 2350), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2351, 1373), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2345, 2352), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1396, 2353), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2348, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2354, 676), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2355, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1440, 646), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2356, 2357), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(538, 632), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:27) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2358, 2359), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(539, 622), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:43) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2360, 2361), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(538, 646), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(539, 632), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:36) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2363, 2364), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2365, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :145:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2362, 2366), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1397, 1810), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(544, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1398, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1399, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1400, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(996, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(2369, 993), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2370, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(551, 33), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2371, 2372), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2373, 1382), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2367, 2374), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1401, 2375), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2370, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2376, 551), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2377, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(539, 646), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :153:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2378, 2379), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1402, 1811), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2380, 1385), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2381, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1403, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1404, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(1002, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(2383, 999), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(2382, 2384), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1405, 2385), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1160, 899), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1406, 2386), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1373, 902), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1407, 2387), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1408, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:30) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1005, 16), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:36) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1382, 2388), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1409, 2389), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1385, 2388), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1410, 2390), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1411, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :69:26) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1008, 29), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:25) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(902, 2391), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:18) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2392, 7), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:40) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1412, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1392, 2393), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1413, 2394), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1414, 1812), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1415, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1011, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2395, 1401), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(929, 2396), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1416, 2397), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(932, 1011), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1417, 1813), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1418, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1014, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2399, 1404), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2398, 2400), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1419, 2401), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1420, 1826), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1421, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1017, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2402, 1411), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1143, 2403), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1422, 2404), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1148, 1017), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1423, 1827), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1424, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1051, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2406, 1427), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2405, 2407), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1425, 2408), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1426, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:26) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1427, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:38) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1411, 33), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:19) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2409, 1401), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:31) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1427, 16), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:44) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2411, 1404), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:55) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1428, 1828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1429, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1060, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2413, 1428), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2410, 2414), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1430, 2415), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2412, 1060), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1431, 1831), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1432, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1063, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2417, 1830), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2416, 2418), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1433, 2419), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1055, 1057), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:37) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1143, 899), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1148, 902), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(935, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(938, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(0, 929), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :100:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1435, 932), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :100:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1436, 2421), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1437, 2422), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1438, 2423), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1439, 2424), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(1434, 1054, 1440), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(929, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(932, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(938, 29), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1228, 899), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :106:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1442, 2248), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :106:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1443, 2425), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1444, 2426), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1445, 935), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1446, 2427), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1447, 1143), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :109:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1448, 1148), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :109:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(1441, 1057, 1449), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1064, 1), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:22) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 1005), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :112:17) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1451, 2428), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:22) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(1450, 2420, 1452), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRL ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :136:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :26:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1453, 1429), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(1351, 377, 1454), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(2204, 24), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :140:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(16, 899), // loc(callsite( builtin Sub at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:14) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(16, 902), // loc(callsite( builtin Sub at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:14) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1353, 2429), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :140:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1456, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1457, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1458, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1459, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1460, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1461, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1462, 2258), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1463, 2269), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1464, 2275), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1465, 2277), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :141:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1466, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :119:26) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :142:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1467, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :120:24) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :142:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(935, 29), // loc(callsite( builtin Mul at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:24) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :142:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1845, 2432), // loc(callsite( builtin Add at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:20) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :142:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(902, 2433), // loc(callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:11) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :142:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1468, 2434), // loc(callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:11) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :142:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(935, 2430), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:4) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(936, 899), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:39) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2435, 2436), // loc(callsite( builtin Add at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:24) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(935, 2431), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:4) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(936, 902), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:39) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2438, 2439), // loc(callsite( builtin Add at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:24) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1469, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1470, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :57:27) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1471, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1472, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1473, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1474, 2279), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1475, 2280), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1476, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(938, 2282), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1477, 2441), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2285, 2303), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(972, 2442), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1478, 2443), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2289, 2307), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(539, 2444), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1479, 2445), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1480, 2293), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1481, 2294), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1482, 2295), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1483, 2296), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1484, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1485, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1486, 2300), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2302, 2310), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(932, 2446), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1487, 2447), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(978, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2306, 2448), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(646, 2449), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1488, 2450), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1489, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1490, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(981, 29), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2451, 1163), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:21) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1154, 2452), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1491, 2453), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1148, 2313), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :127:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2454, 2318), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1492, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1493, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1494, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1495, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(987, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(2456, 984), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2457, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2458, 2324), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2459, 1373), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2455, 2460), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1496, 2461), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2457, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2462, 666), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1154, 2463), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :133:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2464, 2331), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :134:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2465, 2333), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2466, 2335), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2467, 2344), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1497, 1810), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1498, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1499, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1500, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(993, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(2469, 990), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2470, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2471, 2350), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2472, 1382), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2468, 2473), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1501, 2474), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2470, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2475, 676), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2476, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2477, 2357), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2478, 2359), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2479, 2361), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2480, 2366), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1502, 1811), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1503, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1504, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1505, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(999, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(2482, 996), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2483, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2484, 2372), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2485, 1385), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2481, 2486), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1506, 2487), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2483, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2488, 551), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2489, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2490, 2379), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1507, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2491, 1392), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2492, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1508, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1509, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(1005, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(2494, 1002), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(2493, 2495), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1510, 2496), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1373, 2437), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1511, 2497), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1382, 2440), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1512, 2498), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1513, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:30) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1008, 16), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:36) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1385, 2499), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1514, 2500), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1392, 2499), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1515, 2501), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1516, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :69:26) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1011, 29), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:25) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2440, 2502), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2503, 7), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:40) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1517, 1812), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1401, 2504), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1518, 2505), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1519, 1813), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1520, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(929, 2400), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1521, 2506), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(932, 1014), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1522, 1826), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1523, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2507, 2403), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1524, 2508), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1525, 1827), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1526, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1148, 2407), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1527, 2509), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1154, 1051), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1528, 1828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1529, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1054, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2511, 1428), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2510, 2512), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1530, 2513), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1531, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:26) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1532, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:38) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1427, 33), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:19) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2514, 1404), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:31) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1428, 16), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:44) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2516, 1411), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:55) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1533, 1831), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1534, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(2515, 2418), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1535, 2518), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2517, 1063), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1536, 1434), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1537, 1068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1066, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2520, 1430), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2519, 2521), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1538, 2522), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1058, 1060), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:37) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1148, 2437), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1154, 2440), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(972, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1436, 2524), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1540, 2525), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1541, 2424), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1542, 2526), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(1539, 1057, 1543), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(2440, 29), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :106:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(972, 29), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1228, 2437), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :106:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1545, 2527), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :106:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1546, 2425), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1547, 2426), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1548, 938), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1549, 2528), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1550, 1148), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :109:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1551, 1154), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :109:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(1544, 1060, 1552), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1067, 1), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:22) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 1008), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :112:17) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1554, 2529), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:22) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(1553, 2523, 1555), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :143:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(1455, 380, 1556), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(742, 38), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :148:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 2530), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :102:19) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :148:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1558, 2247), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :148:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1559, 2204), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :148:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1560, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1561, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1562, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1563, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1564, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1565, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2257, 2195), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1566, 2531), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1567, 2269), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1568, 2275), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1569, 2277), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :149:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1570, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1571, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :57:27) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1572, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1573, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1574, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1575, 2279), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1576, 2280), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1577, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1578, 2283), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1579, 2288), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1580, 2292), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1581, 2293), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1582, 2294), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1583, 2295), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1584, 2296), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1585, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1586, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1587, 2300), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1588, 2305), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1589, 2309), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1590, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1591, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1592, 2312), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1593, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1594, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1595, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1596, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1597, 2327), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1598, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1599, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1600, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1601, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1602, 2353), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1603, 1810), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1604, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1605, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1606, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1607, 2375), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1608, 1811), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1609, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1610, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1611, 2385), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1612, 2386), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1613, 2387), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1614, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:30) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1615, 2389), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1616, 2390), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1617, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :69:26) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1618, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1619, 2394), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1620, 1812), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1621, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1622, 2397), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1623, 1813), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1624, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1625, 2401), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1626, 1826), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1627, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1628, 2404), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1629, 1827), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1630, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1631, 2408), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1632, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:26) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1633, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:38) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1634, 1828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1635, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1636, 2415), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1637, 1831), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1638, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1639, 2419), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(1640, 1054, 1440), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(1641, 1057, 1449), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(1642, 2420, 1452), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRLI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :150:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :28:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1643, 1429), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(1557, 383, 1644), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1559, 2429), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :154:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1646, 913), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1647, 916), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1648, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1649, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1650, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ToBits ( zirgen/circuit/rv32im/v2/dsl/po2.zir :24:31) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :38:21) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1651, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :40:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1652, 2531), // loc(callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :41:30) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1653, 2269), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :44:13) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1654, 2275), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :46:14) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1655, 2277), // loc(callsite( Reg ( :6:7) at callsite( DynPo2 ( zirgen/circuit/rv32im/v2/dsl/po2.zir :47:15) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :155:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1656, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :119:26) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1657, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :120:24) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1658, 2434), // loc(callsite( TopBit ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :121:11) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :156:18) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1659, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1660, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :57:27) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1661, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1662, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1663, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1664, 2279), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1665, 2280), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1666, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1667, 2441), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1668, 2443), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1669, 2445), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1670, 2293), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1671, 2294), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1672, 2295), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1673, 2296), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1674, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1675, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1676, 2300), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1677, 2447), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1678, 2450), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1679, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1680, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1681, 2453), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1682, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1683, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1684, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1685, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1686, 2461), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1687, 1810), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1688, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1689, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1690, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1691, 2474), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1692, 1811), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1693, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1694, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1695, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1696, 2487), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1697, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1698, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1699, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1700, 2496), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1701, 2497), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1702, 2498), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1703, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:30) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1704, 2500), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1705, 2501), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1706, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :69:26) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1707, 1812), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1708, 2505), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1709, 1813), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1710, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1711, 2506), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1712, 1826), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1713, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1714, 2508), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1715, 1827), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1716, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1717, 2509), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1718, 1828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1719, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1720, 2513), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1721, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:26) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1722, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:38) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1723, 1831), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1724, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1725, 2518), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1726, 1434), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1727, 1068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1728, 2522), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(1729, 1057, 1543), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(1730, 1060, 1552), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(1731, 2523, 1555), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpSRAI ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :157:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :29:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(1645, 386, 1732), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(2206, 5), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :162:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(2204, 1), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :162:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(33, 905), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(16, 908), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :77:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(905, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(908, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1352, 2532), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :162:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1734, 2533), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :162:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1735, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1736, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :57:27) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1737, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1738, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1739, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1740, 2279), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1741, 2280), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1742, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(911, 2282), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1743, 2538), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(917, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2285, 2539), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(914, 2540), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1744, 2541), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(917, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2289, 2542), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(539, 2543), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1745, 2544), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1746, 2293), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1747, 2294), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1748, 2295), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1749, 2296), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1750, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1751, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(905, 2299), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1752, 2545), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(920, 29), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:40) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2302, 2546), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(908, 2547), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1753, 2548), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(920, 25), // loc(callsite( builtin Mul at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2306, 2549), // loc(callsite( builtin Add at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:24) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(646, 2550), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1754, 2551), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1755, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1756, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(923, 29), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2552, 1151), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:21) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1143, 2553), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1757, 2554), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1137, 2313), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :127:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2555, 2318), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :128:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1758, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1759, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1760, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1761, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(929, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(2557, 926), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2558, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2559, 2324), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2560, 1154), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2556, 2561), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1762, 2562), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2558, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2563, 666), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1143, 2564), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :133:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2565, 2331), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :134:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2566, 2333), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2567, 2335), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2568, 2344), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :135:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1763, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1764, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1765, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1766, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(935, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(2570, 932), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2571, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2572, 2350), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2573, 1160), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2569, 2574), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1767, 2575), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2571, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2576, 676), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(923, 16), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2577, 2578), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :141:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2579, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2282, 920), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:40) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2580, 2581), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2299, 917), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:75) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2582, 2583), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:47) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2584, 2357), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2585, 2359), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2586, 2361), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2587, 2366), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1768, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1769, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1770, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1771, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(972, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(2589, 938), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2590, 48), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2591, 2372), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:21) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2592, 1373), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:45) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2588, 2593), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1772, 2594), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2590, 20), // loc(callsite( builtin Mul at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:20) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2595, 551), // loc(callsite( builtin Add at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :102:33) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2596, 2578), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :150:16) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2597, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(539, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:30) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(538, 2599), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:22) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2600, 920), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:40) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2598, 2601), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(646, 20), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:65) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(632, 2603), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:57) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2604, 917), // loc(callsite( builtin Mul at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:75) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2602, 2605), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:47) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2606, 2379), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1773, 1810), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2607, 1382), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2608, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1774, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1775, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(978, 7), // loc(callsite( builtin Mul at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:4) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(2610, 975), // loc(callsite( builtin Add at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :66:11) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(2609, 2611), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1776, 2612), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1154, 899), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1777, 2613), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1160, 902), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1778, 2614), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1779, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:30) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(981, 16), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:36) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1373, 2615), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1780, 2616), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1382, 2615), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1781, 2617), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1782, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :69:26) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(984, 29), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:25) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(902, 2618), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:18) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2619, 7), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:40) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1783, 1811), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1385, 2620), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1784, 2621), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(920, 2534), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:6) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(921, 905), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:54) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2622, 2623), // loc(callsite( builtin Add at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :76:37) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(920, 2535), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :77:6) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(921, 908), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :77:54) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2625, 2626), // loc(callsite( builtin Add at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :77:37) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1785, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1786, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2057, 1392), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2624, 2628), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1787, 2629), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2627, 987), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1788, 1812), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1789, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(990, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2631, 1401), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2630, 2632), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1790, 2633), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(33, 1137), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:16) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(984, 2634), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:6) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(985, 1137), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:48) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2635, 2636), // loc(callsite( builtin Add at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :81:33) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(16, 1143), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :82:16) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(984, 2638), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :82:6) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(985, 1143), // loc(callsite( builtin Mul at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :82:48) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2639, 2640), // loc(callsite( builtin Add at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :82:33) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1791, 1813), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1792, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(993, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2642, 1404), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2637, 2643), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1793, 2644), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2641, 993), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1794, 1826), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1795, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2062, 1411), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2645, 2646), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1796, 2647), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1797, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:26) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1798, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:38) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1404, 33), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:19) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2648, 1392), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:31) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1411, 16), // loc(callsite( builtin Add at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:44) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2650, 1401), // loc(callsite( builtin Sub at callsite( SubU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :33:55) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1799, 1827), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1800, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1005, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2652, 1427), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2649, 2653), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1801, 2654), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2651, 1005), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1802, 1828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1803, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1008, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2656, 1428), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2655, 2657), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1804, 2658), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1000, 1002), // loc(callsite( builtin Sub at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:37) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1137, 899), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1143, 902), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(911, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(914, 16), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(0, 905), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :100:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1806, 908), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :100:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1807, 2660), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1808, 2661), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :101:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1809, 2662), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1810, 2663), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :102:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(1805, 999, 1811), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(914, 29), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(0, 899), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :106:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1813, 2248), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :106:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1814, 2536), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1815, 2537), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1816, 911), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1817, 2664), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1818, 1137), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :109:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1819, 1143), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :109:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(1812, 1002, 1820), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(981, 984), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :112:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1009, 1), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:22) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 2665), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :112:17) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1822, 2666), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:22) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(1821, 2659, 1823), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpDIV ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :163:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :30:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1824, 1829), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1825, 1429), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(1733, 389, 1826), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1353, 2533), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :167:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1828, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1829, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :57:27) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1830, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1831, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1832, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1833, 2279), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1834, 2280), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1835, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1836, 2538), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1837, 2541), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1838, 2544), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1839, 2293), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1840, 2294), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1841, 2295), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1842, 2296), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1843, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1844, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1845, 2545), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1846, 2548), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1847, 2551), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1848, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1849, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1850, 2554), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1851, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1852, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1853, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1854, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1855, 2562), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1856, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1857, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1858, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1859, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1860, 2575), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2577, 47), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :142:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2667, 2357), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :143:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2668, 2359), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2669, 2361), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:35) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2670, 2366), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :144:51) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1861, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1862, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1863, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1864, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(2671, 2593), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1865, 2672), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2596, 46), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :151:42) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2673, 2379), // loc(callsite( builtin Add at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :152:82) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1866, 1810), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2674, 1382), // loc(callsite( builtin Sub at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2675, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:41) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1867, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1868, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(2676, 2611), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1869, 2677), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1870, 2613), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1871, 2614), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1872, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:30) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1873, 2616), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1874, 2617), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1875, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :69:26) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1876, 1811), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1877, 2621), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1878, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1879, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(905, 2628), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1880, 2678), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(908, 987), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1881, 1812), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1882, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2679, 2632), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1883, 2680), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1884, 1813), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1885, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1137, 2643), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1886, 2681), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1143, 993), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1887, 1826), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1888, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2682, 2646), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1889, 2683), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1890, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:26) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1891, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:38) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1892, 1827), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1893, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1894, 2654), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1895, 1828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1896, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1897, 2658), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(1898, 999, 1811), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1443, 2536), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1900, 2537), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :107:17) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1901, 911), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1902, 2664), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :108:17) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1903, 1137), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :109:17) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1904, 1143), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :109:17) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(1899, 1002, 1905), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 981), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :112:17) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1907, 2666), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :113:22) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(1906, 2659, 1908), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpDIVU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :168:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :31:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1909, 1829), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1910, 1429), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(1827, 392, 1911), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(2206, 3), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :172:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1352, 2684), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :172:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1913, 2533), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :172:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1914, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1915, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :57:27) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1916, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1917, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1918, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1919, 2279), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1920, 2280), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1921, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1922, 2538), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1923, 2541), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1924, 2544), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1925, 2293), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1926, 2294), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1927, 2295), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1928, 2296), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1929, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1930, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1931, 2545), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1932, 2548), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1933, 2551), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1934, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1935, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1936, 2554), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1937, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1938, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1939, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1940, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1941, 2562), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1942, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1943, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1944, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1945, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1946, 2575), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1947, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1948, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1949, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1950, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1951, 2594), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1952, 1810), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1953, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1954, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(1955, 2612), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1956, 2613), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1957, 2614), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1958, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:30) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1959, 2616), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1960, 2617), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1961, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :69:26) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1962, 1811), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1963, 2621), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1964, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1965, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1966, 2629), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1967, 1812), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1968, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1969, 2633), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1970, 1813), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1971, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1972, 2644), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1973, 1826), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1974, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1975, 2647), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1976, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:26) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1977, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:38) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1978, 1827), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1979, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1980, 2654), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(1981, 1828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1982, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(1983, 2658), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(1984, 999, 1811), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(1985, 1002, 1820), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(1986, 2659, 1823), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1987, 1829), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1988, 1429), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(1912, 395, 1989), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(2206, 2), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :177:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1352, 2685), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :103:18) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :177:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1991, 2533), // loc(callsite( VerifyOpcodeF3F7 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :104:18) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :177:20) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(1992, 1138), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1993, 1144), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :57:27) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(1994, 1854), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1995, 1441), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1996, 1901), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1997, 2279), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1998, 2280), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(1999, 919), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2000, 2538), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2001, 2541), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2002, 2544), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :119:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2003, 2293), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :51:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2004, 2294), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :52:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2005, 2295), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :53:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2006, 2296), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :54:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2007, 2297), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :60:31) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2008, 922), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :61:26) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2009, 2545), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :63:10) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2010, 2548), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :64:11) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2011, 2551), // loc(callsite( ExpandU32 ( zirgen/circuit/rv32im/v2/dsl/mult.zir :68:7) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :120:19) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2012, 925), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :122:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2013, 1149), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :123:31) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2014, 2554), // loc(callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :124:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2015, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2016, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2017, 928), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(2018, 931), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(2019, 2562), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :126:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2020, 1161), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2021, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2022, 934), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(2023, 937), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(2024, 2575), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :132:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2025, 1374), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :98:30) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2026, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :99:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2027, 940), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(2028, 974), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :100:35) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(2029, 2672), // loc(callsite( SplitTotal ( zirgen/circuit/rv32im/v2/dsl/mult.zir :101:6) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :140:20) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2030, 1810), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :154:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2031, 977), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :64:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(2032, 980), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NondetFakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :65:24) at callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :76:28) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::AndEqz(2033, 2677), // loc(callsite( FakeTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :77:8) at callsite( MultiplyAccumulate ( zirgen/circuit/rv32im/v2/dsl/mult.zir :155:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :62:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2034, 2613), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2035, 2614), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :64:15) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2036, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :66:30) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2037, 2616), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :106:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2038, 2617), // loc(callsite( AssertEqU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :107:11) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :67:15) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2039, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :69:26) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2040, 1811), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2041, 2621), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :71:10) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2042, 1393), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2043, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2044, 2678), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2045, 1812), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2046, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2047, 2680), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :75:28) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2048, 1813), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2049, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2050, 2681), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2051, 1826), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2052, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2053, 2683), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :80:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2054, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :90:26) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2055, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :91:38) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2056, 1827), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2057, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2058, 2654), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2059, 1828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2060, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2061, 2658), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( CmpLessThanUnsigned ( zirgen/circuit/rv32im/v2/dsl/u32.zir :119:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :96:29) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(2062, 999, 1811), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(2063, 1002, 1905), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(2064, 2659, 1908), // loc(callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :97:66) at callsite( OpREMU ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :178:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :33:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2065, 1829), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2066, 1429), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(1990, 398, 2067), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1212, 377), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(16, 1213), // loc(callsite( builtin Sub at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:14) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1212, 2687), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:4) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1212), // loc(callsite( builtin Sub at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:29) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2689, 1213), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:39) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2688, 2690), // loc(callsite( builtin Add at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:24) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:18) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2691, 380), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1212, 383), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(2691, 386), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1204, 389), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1204, 392), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(156), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( DoDiv ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :56:27) at callsite( OpREM ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :173:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :32:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(2697, 395), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(2697, 398), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2686, 2692), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2700, 2693), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2701, 2694), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2702, 2695), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2703, 2696), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2704, 2698), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2705, 2699), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1213, 377), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(16, 1281), // loc(callsite( builtin Sub at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:14) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1212, 2708), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:4) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2689, 1281), // loc(callsite( builtin Mul at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:39) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2709, 2710), // loc(callsite( builtin Add at callsite( FlipU16 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :126:24) at callsite( FlipU32 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :130:42) at callsite( OpSRA ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :144:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :27:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2711, 380), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1213, 383), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(2711, 386), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1205, 389), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1205, 392), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(2013, 395), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(2013, 398), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2707, 2712), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2719, 2713), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2720, 2714), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2721, 2715), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2722, 2716), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2723, 2717), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2724, 2718), // loc(callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :25:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2068, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2199, 1072), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2726, 1070), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2069, 2727), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1069, 2199), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2070, 2728), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1069, 1072), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2071, 2729), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1070, 2199), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 1070), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:90) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(2731, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:102) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(506, 2732), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:85) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2733, 2730), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:106) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(2734, 1075), // loc(callsite( Reg ( :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2072, 2735), // loc(callsite( Reg ( :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(775), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(776), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1081, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2073, 2738), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1093, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2074, 2739), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1096, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2075, 2740), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2076, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1078, 1075), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2077, 2741), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1096, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2742, 1084), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Get(777), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :54:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Get(778), // loc(callsite( builtin NondetReg at callsite( CycleArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :55:29) at callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :60:19) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(2744, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2078, 2746), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2745, 2743), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2079, 2747), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2736, 2706), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2080, 2748), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(2737, 2725), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2081, 2749), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :35:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(779), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Get(780), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2750, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2082, 2752), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(781), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 2753), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2753, 2754), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2083, 2755), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2753, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2756, 2751), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(507, 2757), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2084, 2758), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(370, 2753), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(782), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :33:29) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Get(783), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2760, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2085, 2762), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(784), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 2763), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2763, 2764), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2086, 2765), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2763, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2766, 2761), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(2759, 2767), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2087, 2768), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(1270, 434, 2088), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Sub(1160, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 2769), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(1373, 542), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2090, 2770), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :50:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2091, 497), // loc(callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :8:21) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(1, 1829), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1829, 2771), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 1829), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2772, 2773), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 1829), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2774, 2775), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2092, 2776), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :63:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1830, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2093, 2777), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1429, 502), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2094, 2778), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :65:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1430), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1430, 2779), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2095, 2780), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(370, 1431), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2781, 2779), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2096, 2782), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1430, 370), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2097, 2783), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1430, 1431), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2098, 2784), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2099, 1430), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :67:19) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1432, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2100, 2785), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :69:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1439, 5), // loc(callsite( builtin Mul at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:4) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2786, 1829), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:12) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2787, 368), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2101, 2788), // loc(callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :71:21) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(503, 1439), // loc(callsite( builtin Add at callsite( AddrDecompose ( zirgen/circuit/rv32im/v2/dsl/u32.zir :73:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :27:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2102, 1829), // loc(callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :29:17) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1900, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2103, 2790), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2104, 2280), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(594, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2105, 2791), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2106, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1440, 2789), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2107, 2792), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2278, 601), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2108, 2793), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(539, 608), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2109, 2794), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(594, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2795, 538), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2110, 2294), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(622, 2796), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2111, 2797), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :31:27) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2112, 1377), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :15:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 1382), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1382, 2798), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 1382), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2799, 2800), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 1382), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2801, 2802), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2113, 2803), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :16:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 1383), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1383, 2804), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 1383), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2805, 2806), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 1383), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2807, 2808), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2114, 2809), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :17:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7, 1385), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1387, 2810), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 1385), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2811, 2812), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2115, 2813), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :18:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 1391), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1391, 2814), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 1391), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2815, 2816), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 1391), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2817, 2818), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2116, 2819), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :19:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 1392), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1392, 2820), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 1392), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2821, 2822), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 1392), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2823, 2824), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2117, 2825), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :20:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2118, 1396), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :21:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 1401), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1401, 2826), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 1401), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2827, 2828), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 1401), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2829, 2830), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2119, 2831), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :22:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 1402), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1402, 2832), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 1402), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2833, 2834), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 1402), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2835, 2836), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2120, 2837), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :23:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2121, 1406), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :24:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2122, 1413), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :25:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 1411), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1411, 2838), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 1411), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2839, 2840), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 1411), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2841, 2842), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2123, 2843), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :26:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 1424), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1424, 2844), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 1424), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2845, 2846), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 1424), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2847, 2848), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2124, 2849), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :27:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 1427), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:11) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1427, 2850), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:4) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(7, 1427), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:23) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2851, 2852), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:18) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(6, 1427), // loc(callsite( builtin Sub at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:35) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2853, 2854), // loc(callsite( builtin Mul at callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:30) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2125, 2855), // loc(callsite( AssertTwit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :38:44) at callsite( NondetTwitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :57:14) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :28:27) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 1426), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1426, 2856), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2126, 2857), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :29:25) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1375, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1382, 28), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2858, 2859), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1383, 27), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2860, 2861), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :38:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1385, 26), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2862, 2863), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :39:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1391, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2864, 2865), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :40:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1392, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2866, 2867), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :41:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1394, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2868, 2869), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :42:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1401, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:16) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2870, 2871), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :43:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2872, 1402), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :44:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(608, 2873), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2127, 2874), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :37:14) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1404, 29), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1410, 14), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2875, 2876), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1411, 22), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2877, 2878), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :47:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1424, 21), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2879, 2880), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :48:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2881, 1832), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :49:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1426, 25), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:15) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2882, 2883), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :50:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2884, 1428), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :51:24) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(601, 2885), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2128, 2886), // loc(callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :46:13) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1401, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1402, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2887, 2888), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2889, 1404), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :55:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1391, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:18) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1392, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2891, 2892), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2893, 1394), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :56:42) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1424, 12), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:17) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1427, 7), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:30) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2895, 2896), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2897, 1426), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :57:39) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1382, 23), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:23) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1383, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:38) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2899, 2900), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:32) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2901, 1385), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :58:47) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1375, 19), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2903, 2902), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :59:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1410, 5), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:20) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2905, 1411), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :60:28) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1375, 18), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:26) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2904, 24), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:45) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2907, 2908), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:36) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2909, 2894), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:53) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1375, 16), // loc(callsite( builtin Mul at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :66:63) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :10:32) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(506, 2890), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2912, 551), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2129, 2913), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(632, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2130, 2914), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(652, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2131, 2915), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(659, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2132, 2916), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2133, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(629, 551), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2134, 2917), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(646, 666), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2135, 2918), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(649, 673), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2136, 2919), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2320, 639), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(676, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2137, 2921), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(544, 2920), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2138, 2922), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :11:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(666, 2910), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:35) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(673, 2911), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:35) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(552, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2139, 2925), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 556), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(556, 2926), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2140, 2927), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(556, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2928, 555), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2923, 2929), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2141, 2930), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2924, 556), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2142, 565), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2143, 2091), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(571, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2932, 564), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2931, 2933), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2144, 2934), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :12:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2145, 2097), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :81:31) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2146, 2103), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(572, 7), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:19) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2935, 570), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:26) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(501, 564), // loc(callsite( builtin Sub at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:53) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(573, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2147, 2938), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(574, 2937), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2148, 2939), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2149, 2121), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(564, 576), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2940, 2120), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2150, 2941), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(575, 564), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2151, 2942), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(575, 576), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2152, 2943), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2153, 575), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:19) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2154, 1653), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(578, 5), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:4) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2944, 2936), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:12) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2945, 555), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2155, 2946), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(564, 14), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:19) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2947, 578), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:30) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :13:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(588, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2156, 2949), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(742, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2157, 2950), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(743, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2158, 2951), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2159, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(587, 2948), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2160, 2952), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(740, 744), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2161, 2953), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(741, 745), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2162, 2954), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(743, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2955, 739), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2163, 1740), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(747, 2956), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2164, 2957), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemLoadInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :14:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :51:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1428, 6), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :86:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(572, 745), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :87:24) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(2102, 744), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :87:69) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2959, 2960), // loc(callsite( builtin Add at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :87:42) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 2958), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :86:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2166, 2906), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :86:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2167, 1138), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2168, 1144), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1143, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2962, 1137), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2961, 2963), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2169, 2964), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :88:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(570, 1143), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :89:23) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(2096, 1137), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :89:64) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2965, 2966), // loc(callsite( builtin Add at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :89:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 760), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :90:27) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(760, 2968), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :90:27) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2170, 2969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :90:27) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2171, 1149), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :91:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(760, 25), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :92:11) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2970, 1151), // loc(callsite( builtin Add at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :92:21) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(2967, 2971), // loc(callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :92:9) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2172, 2972), // loc(callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :92:9) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2173, 810), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2165, 377, 2174), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(2906, 1), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :97:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2166, 2973), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :97:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2176, 570), // loc(callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :98:20) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2177, 2969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :100:27) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2178, 1155), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :101:27) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(760, 29), // loc(callsite( builtin Mul at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :102:12) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2974, 1157), // loc(callsite( builtin Add at callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :102:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(2961, 2975), // loc(callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :102:10) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2179, 2976), // loc(callsite( OpLH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :102:10) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :54:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2180, 807), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2181, 808), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2182, 809), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2175, 380, 2183), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(2906, 7), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :107:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :55:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2166, 2977), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :107:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :55:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2185, 570), // loc(callsite( OpLW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :108:20) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :55:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2186, 572), // loc(callsite( OpLW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :109:20) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :55:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2187, 807), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2188, 808), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2189, 809), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2190, 810), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2184, 383, 2191), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(2906, 5), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLBU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :114:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :56:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2166, 2978), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLBU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :114:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :56:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2193, 1138), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( OpLBU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :116:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :56:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2194, 1144), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( OpLBU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :116:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :56:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2195, 2964), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( OpLBU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :116:22) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :56:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2196, 809), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2197, 810), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2192, 386, 2198), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(2906, 4), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLHU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :122:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :57:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2166, 2979), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpLHU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :122:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :57:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2200, 570), // loc(callsite( OpLHU ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :123:20) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :57:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2201, 807), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2202, 808), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2203, 809), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2204, 810), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2199, 389, 2205), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2206, 392, 1232), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2207, 395, 1232), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2208, 398, 1232), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(570, 2013), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :89:23) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(2096, 2697), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :89:64) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2980, 2981), // loc(callsite( builtin Add at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :89:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1760, 50), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :93:18) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2982, 2983), // loc(callsite( builtin Add at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :93:11) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(2984, 377), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(2961, 380), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(744, 383), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(2982, 386), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(2961, 389), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2985, 2986), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2990, 2987), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2991, 2988), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2992, 2989), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1760, 16), // loc(callsite( builtin Mul at callsite( OpLB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :93:36) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :53:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(2994, 377), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(2994, 380), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(745, 383), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2995, 2996), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(2998, 2997), // loc(callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :52:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1, 766), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(766, 3000), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2209, 3001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2898, 767), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3002, 3000), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2210, 3003), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(766, 2898), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2211, 3004), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(766, 767), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2212, 3005), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :71:19) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3000, 2898), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :73:11) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 3000), // loc(callsite( builtin Sub at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:90) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3007, 19), // loc(callsite( builtin Mul at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:102) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(506, 3008), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:85) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3009, 3006), // loc(callsite( builtin Add at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:106) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3010, 768), // loc(callsite( Reg ( :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2213, 3011), // loc(callsite( Reg ( :6:7) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :74:21) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(761, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2214, 3012), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2215, 758), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(757, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2216, 3013), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2217, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(769, 768), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2218, 3014), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(757, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3015, 770), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2219, 1758), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(737, 3016), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2220, 3017), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(762, 2993), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2221, 3018), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(781, 2999), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2222, 3019), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( WriteRd ( zirgen/circuit/rv32im/v2/dsl/inst.zir :75:15) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :62:11) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(764, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2223, 3020), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 800), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 3021), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2224, 3022), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(800, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3023, 798), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(507, 3024), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2225, 3025), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(370, 800), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2226, 2211), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2227, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1139, 804), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3026, 3027), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2228, 3028), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(2089, 437, 2229), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(2909, 2898), // loc(callsite( builtin Add at callsite( Decoder ( zirgen/circuit/rv32im/v2/dsl/decode.zir :67:53) at callsite( DecodeInst ( zirgen/circuit/rv32im/v2/dsl/inst.zir :33:11) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :20:32) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2129, 2121), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :49:36) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(2890, 2894), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :52:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 3030), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :52:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(2912, 576), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2232, 3031), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(629, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2233, 3032), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2234, 2915), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2235, 2916), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2236, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(632, 576), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2237, 3033), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2238, 2918), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2239, 2919), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(570, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2240, 3034), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(572, 2920), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2241, 3035), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2242, 676), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2243, 556), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2244, 573), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(2231, 575, 2245), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(506, 2894), // loc(callsite( builtin Add at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:79) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 3031), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2247, 3032), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2248, 2915), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2249, 2916), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2250, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2251, 3033), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2252, 2918), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2253, 2919), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2254, 3034), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2255, 3035), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :59:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(3036, 577), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2256, 3037), // loc(callsite( Reg ( :6:7) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :37:15) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(676, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2257, 3038), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(556, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2258, 3039), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(563, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2259, 3040), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2260, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(544, 577), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2261, 3041), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(552, 564), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2262, 3042), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(555, 571), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2263, 3043), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(565, 551), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2264, 2938), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(574, 3044), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(2265, 3045), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(2246, 2120, 2266), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(443), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(3046, 575), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3046, 2120), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3047, 3048), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(449), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :53:22) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(3050, 575), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3050, 2120), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3051, 3052), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(497), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(3054, 2120), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3047, 3055), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(503), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadReg ( zirgen/circuit/rv32im/v2/dsl/inst.zir :38:14) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :60:15) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(3057, 2120), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3051, 3058), // loc(callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :50:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3049, 578), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2267, 3060), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :62:17) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3053, 587), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2268, 3061), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :63:17) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3056, 588), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2269, 3062), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :64:17) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3059, 739), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2270, 3063), // loc(callsite( Reg ( :6:7) at callsite( ReadSourceRegs ( zirgen/circuit/rv32im/v2/dsl/inst.zir :65:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :21:33) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(578, 3029), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:35) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(587, 2911), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:36) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:35) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(740, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2271, 3066), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 742), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(742, 3067), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2272, 3068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(742, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3069, 741), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3064, 3070), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2273, 3071), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3065, 742), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2274, 2955), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 745), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(745, 3073), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2275, 3074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(745, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3075, 744), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3072, 3076), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2276, 3077), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :24:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2277, 2075), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :81:31) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 747), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(747, 3078), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2278, 3079), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(747, 7), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3080, 746), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:26) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(501, 744), // loc(callsite( builtin Sub at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:53) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2279, 2080), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(766, 3082), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2280, 3083), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 767), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(767, 3084), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(2281, 3085), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(744, 768), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3086, 3084), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2282, 3087), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(767, 744), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2283, 3088), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(767, 768), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2284, 3089), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2285, 767), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(769, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2286, 3090), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(761, 5), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:4) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3091, 3081), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:12) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3092, 741), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2287, 3093), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(744, 14), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:19) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3094, 761), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:30) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :25:36) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(771, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2288, 3096), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2289, 782), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(781, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2290, 3097), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2291, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(770, 3095), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2292, 3098), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(756, 732), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2293, 3099), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(757, 737), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2294, 3100), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(781, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3101, 772), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2295, 3020), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(798, 3102), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2296, 3103), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemStoreInput ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :26:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :69:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1428, 51), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :129:18) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(747, 737), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :130:24) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3078, 732), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :130:69) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3105, 3106), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :130:42) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 3104), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :96:19) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :129:18) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2298, 2906), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :129:18) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2299, 1138), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :131:27) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2300, 1144), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :131:27) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3107, 2963), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :131:27) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2301, 3108), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :131:27) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2302, 1149), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :132:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2303, 1155), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :132:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1154, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :132:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3109, 1148), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :132:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(588, 3110), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :132:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2304, 3111), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :132:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(2297, 377, 2305), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2298, 2973), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :147:18) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :72:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2307, 746), // loc(callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :148:20) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :72:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2308, 807), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2309, 808), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2310, 809), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2311, 810), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2306, 380, 2312), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2298, 2977), // loc(callsite( VerifyOpcodeF3 ( zirgen/circuit/rv32im/v2/dsl/inst.zir :97:18) at callsite( OpSW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :159:18) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :73:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2314, 746), // loc(callsite( OpSW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :160:20) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :73:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2315, 747), // loc(callsite( OpSW ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :161:20) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :73:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2316, 807), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2317, 808), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2318, 809), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2319, 810), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2313, 383, 2320), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2321, 386, 1232), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2322, 389, 1232), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2323, 392, 1232), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2324, 395, 1232), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2325, 398, 1232), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(746, 2697), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :137:6) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(2074, 2010), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :137:37) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3112, 3113), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :137:22) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(2074, 2013), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :138:20) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(746, 2010), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :138:44) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3115, 3116), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :138:35) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3117, 20), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :138:6) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3114, 3118), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :137:41) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(747, 732), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :141:6) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3078, 3119), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :141:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3120, 3121), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :141:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3122, 377), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(3078, 588), // loc(callsite( builtin Mul at callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :153:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :72:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3120, 3124), // loc(callsite( builtin Add at callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :153:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :72:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3125, 380), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(588, 383), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(3123, 3126), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(3128, 3127), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(3078, 737), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :142:13) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(747, 3119), // loc(callsite( builtin Mul at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :142:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3130, 3131), // loc(callsite( builtin Add at callsite( OpSB ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :142:21) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :71:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3132, 377), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(747, 588), // loc(callsite( builtin Mul at callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :154:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :72:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3130, 3134), // loc(callsite( builtin Add at callsite( OpSH ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :154:21) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :72:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3135, 380), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(739, 383), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(3133, 3136), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(3138, 3137), // loc(callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :70:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(802, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2326, 3140), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(820, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2327, 3141), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(823, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2328, 3142), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2329, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(800, 3095), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2330, 3143), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(823, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3144, 804), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(832, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2331, 3146), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(835, 3145), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2332, 3147), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(826, 3129), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2333, 3148), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(829, 3139), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2334, 3149), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( MemStoreFinalize ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :30:15) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :80:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2335, 2228), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2336, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(844, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3150, 841), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(507, 3151), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2337, 3152), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(370, 844), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2338, 2218), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2339, 855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(853, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3154, 850), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3153, 3155), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2340, 3156), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( Mem1 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :81:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :80:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(2230, 440, 2341), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Sub(371, 1), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :54:13) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(368, 370), // loc(callsite( builtin Add at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:31) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(374, 1), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :94:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(371, 5), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :104:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(371, 4), // loc(callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :137:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(371, 3), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(371, 2), // loc(callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :183:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(1078, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :196:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 3164), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :196:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(1084, 542), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :196:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2343, 3165), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :196:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(1, 362), // loc(callsite( builtin Sub at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:13) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(362, 3166), // loc(callsite( builtin Mul at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(362, 322), // loc(callsite( builtin Mul at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :27:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3166, 54), // loc(callsite( builtin Mul at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :27:47) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3168, 3169), // loc(callsite( builtin Add at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :27:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3170, 1), // loc(callsite( builtin Add at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3170, 7), // loc(callsite( builtin Add at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3170, 6), // loc(callsite( builtin Add at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3170, 5), // loc(callsite( builtin Add at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3170, 4), // loc(callsite( builtin Add at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3170, 3), // loc(callsite( builtin Add at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3170, 2), // loc(callsite( builtin Add at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 3166), // loc(callsite( builtin Sub at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :32:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 371), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :23:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2345, 3167), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :24:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(807, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2346, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1148, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2347, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(810, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2348, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2349, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1137, 3170), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2350, 3182), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1143, 1154), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2351, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(809, 811), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2352, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1160, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2353, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2354, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1385, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2355, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2356, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1372, 3171), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2357, 3187), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1375, 1391), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2358, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1382, 1392), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2359, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1394, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2360, 3190), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1411, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2361, 3191), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1424, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2362, 3192), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2363, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1401, 3172), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2364, 3193), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1404, 1427), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2365, 3194), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1410, 1426), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2366, 3195), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1428, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2367, 3196), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2368, 1854), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1432, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2369, 3197), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2370, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1829, 3173), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2371, 3198), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1429, 1439), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2372, 3199), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1430, 1440), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2373, 3200), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2374, 2790), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2375, 2795), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(601, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2376, 3201), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2377, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(538, 3174), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2378, 3202), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2379, 2794), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(591, 615), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2380, 3203), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(622, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2381, 3204), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2382, 2297), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(652, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2383, 3205), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2384, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(629, 3175), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2385, 3206), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(639, 659), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2386, 3207), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2387, 2918), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(673, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2388, 3208), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2389, 1639), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(556, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2390, 3209), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2391, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(676, 3176), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2392, 3210), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(551, 563), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2393, 3211), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2394, 3042), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(571, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2395, 3212), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2396, 580), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2397, 581), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2398, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(570, 3177), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2399, 3213), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2400, 583), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2401, 584), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :113:10) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :29:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 33), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1154, 3214), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 3215), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 34), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(811, 3216), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2403, 3217), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 35), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1391, 3218), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2404, 3219), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 36), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1392, 3220), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2405, 3221), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 37), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1427, 3222), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2406, 3223), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 38), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1426, 3224), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2407, 3225), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 39), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1439, 3226), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2408, 3227), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 40), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1440, 3228), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2409, 3229), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 41), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(608, 3230), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2410, 3231), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 42), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(615, 3232), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2411, 3233), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 43), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(659, 3234), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2412, 3235), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 44), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(666, 3236), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2413, 3237), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 45), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(563, 3238), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2414, 3239), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 46), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(564, 3240), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2415, 3241), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 47), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(577, 3242), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2416, 3243), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :35:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 48), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :20:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(578, 3244), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2417, 3245), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :36:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(2402, 3166, 2418), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :32:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 54), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1154, 3246), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 3247), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 55), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(811, 3248), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2420, 3249), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 56), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1391, 3250), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2421, 3251), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 57), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1392, 3252), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2422, 3253), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 58), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1427, 3254), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2423, 3255), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 59), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1426, 3256), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2424, 3257), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 60), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1439, 3258), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2425, 3259), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 61), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1440, 3260), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2426, 3261), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 62), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(608, 3262), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2427, 3263), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 63), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(615, 3264), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2428, 3265), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 64), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(659, 3266), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2429, 3267), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 65), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(666, 3268), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2430, 3269), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 66), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(563, 3270), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2431, 3271), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 67), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(564, 3272), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2432, 3273), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 68), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(577, 3274), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2433, 3275), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :44:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 69), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :19:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(578, 3276), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2434, 3277), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :45:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(2419, 3178, 2435), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :32:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2436, 587), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2437, 739), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2438, 741), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2439, 743), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2440, 745), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2441, 747), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2442, 766), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2443, 768), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2444, 761), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2445, 771), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2446, 756), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2447, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2448, 732), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2449, 764), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2450, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2451, 804), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2452, 817), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2453, 823), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2454, 829), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2455, 835), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2456, 841), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2457, 847), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2458, 853), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2459, 859), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2460, 896), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2461, 902), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2462, 908), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2463, 914), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2464, 920), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2465, 926), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2466, 932), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2467, 938), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2468, 975), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2469, 981), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2470, 987), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2471, 993), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2472, 999), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2473, 1005), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2474, 1011), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2475, 1017), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2344, 377, 2476), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(0, 3157), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :54:13) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2478, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(3158, 1057), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3278, 1055), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2479, 3279), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1054, 3158), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2480, 3280), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1054, 1057), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2481, 3281), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :56:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2483, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2484, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2485, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1137, 353), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2486, 3282), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2487, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2488, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1155, 808), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2489, 589), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(588, 3283), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2490, 3284), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2491, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2492, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2493, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2494, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1372, 354), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2495, 3285), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2496, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2497, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1385, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3286, 1373), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2498, 1660), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(740, 3287), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2499, 3288), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :60:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2500, 1394), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2501, 1411), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2502, 1428), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2503, 1431), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2504, 1900), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2505, 594), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2506, 622), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2507, 649), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2508, 673), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2509, 555), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2510, 571), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2511, 575), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2512, 741), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2513, 743), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2514, 745), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2515, 747), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2516, 766), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2517, 768), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(2482, 1054, 2518), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::GetGlobal(0, 0), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::GetGlobal(0, 1), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(810, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2484, 3291), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2520, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1137, 323), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2521, 3292), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2522, 589), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2523, 3284), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1154, 3289), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2524, 3293), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(811, 3290), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2525, 3294), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::GetGlobal(0, 2), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::GetGlobal(0, 3), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2526, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2527, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1385, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2528, 3297), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2529, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1372, 324), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2530, 3298), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2531, 1660), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2532, 3288), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1391, 3295), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2533, 3299), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1392, 3296), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2534, 3300), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::GetGlobal(0, 4), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::GetGlobal(0, 5), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2535, 3190), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2536, 3191), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1424, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2537, 3303), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2538, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1401, 325), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2539, 3304), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1827, 1402), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(741, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2540, 3306), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(742, 3305), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2541, 3307), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1427, 3301), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2542, 3308), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1426, 3302), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2543, 3309), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::GetGlobal(0, 6), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::GetGlobal(0, 7), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2544, 3196), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2545, 1854), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1432, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2546, 3312), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2547, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1829, 326), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2548, 3313), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2785, 1830), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2549, 2955), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(744, 3314), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2550, 3315), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1439, 3310), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2551, 3316), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1440, 3311), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2552, 3317), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::GetGlobal(0, 8), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::GetGlobal(0, 9), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2553, 2790), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2554, 2795), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(601, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2555, 3320), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2556, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(538, 327), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2557, 3321), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2293, 2278), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2558, 754), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(746, 3322), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2559, 3323), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(608, 3318), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2560, 3324), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(615, 3319), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2561, 3325), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::GetGlobal(0, 10), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::GetGlobal(0, 11), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2562, 3204), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2563, 2297), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(652, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2564, 3328), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2565, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(629, 328), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2566, 3329), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2915, 632), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2567, 1745), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(760, 3330), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2568, 3331), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(659, 3326), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2569, 3332), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(666, 3327), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2570, 3333), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::GetGlobal(0, 12), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::GetGlobal(0, 13), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2571, 3208), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2572, 1639), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(556, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2573, 3336), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2574, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(676, 329), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2575, 3337), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3039, 544), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(766, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2576, 3339), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(767, 3338), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2577, 3340), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(563, 3334), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2578, 3341), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(564, 3335), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2579, 3342), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::GetGlobal(0, 14), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::GetGlobal(0, 15), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :63:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2580, 3212), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2581, 580), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(576, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2582, 3345), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2583, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(570, 330), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2584, 3346), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(768, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2585, 3347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(769, 586), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2586, 3348), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(577, 3343), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2587, 3349), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(578, 3344), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2588, 3350), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :65:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(2519, 1055, 2589), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2590, 761), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2591, 771), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2592, 756), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2593, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2594, 732), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2595, 764), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2596, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2597, 804), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2598, 817), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2599, 823), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2600, 829), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2601, 835), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2602, 841), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2603, 847), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2604, 853), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2605, 859), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2606, 896), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2607, 902), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2608, 908), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2609, 914), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2610, 920), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2611, 926), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2612, 932), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2613, 938), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2614, 975), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2615, 981), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2616, 987), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2617, 993), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2618, 999), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2619, 1005), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2620, 1011), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2621, 1017), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2477, 380, 2622), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(374, 1054), // loc(callsite( Reg ( :6:7) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 3351), // loc(callsite( Reg ( :6:7) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :73:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2624, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :81:31) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2625, 1062), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1060, 7), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:19) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3352, 1057), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:26) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1054, 16), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:24) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1055, 15), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:49) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3354, 3355), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:31) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3356, 370), // loc(callsite( builtin Sub at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:53) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2626, 774), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(770, 3357), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2627, 3358), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2628, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(370, 1066), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3359, 1064), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2629, 3360), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1063, 370), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2630, 3361), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1063, 1066), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2631, 3362), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2632, 1063), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:19) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2633, 1751), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(772, 5), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:4) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3363, 3353), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:12) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3364, 368), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2634, 3365), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(503, 772), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:30) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :74:32) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2635, 3353), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :75:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2636, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2637, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2638, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2639, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1137, 3366), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2640, 3367), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2641, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2642, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2643, 589), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2644, 3284), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :76:27) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2645, 811), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :77:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(1154, 45), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :78:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2646, 3368), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :78:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2647, 497), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :79:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2648, 374), // loc(callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :80:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2649, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2650, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2651, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2652, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1372, 331), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2653, 3369), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2654, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2655, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2656, 1660), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2657, 3288), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2658, 3190), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2659, 3191), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2660, 3303), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2661, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1401, 332), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2662, 3370), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2663, 3306), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2664, 3307), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1427, 368), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2665, 3371), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1426, 370), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2666, 3372), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :82:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2667, 1428), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2668, 1431), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2669, 1900), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2670, 594), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2671, 622), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2672, 649), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2673, 673), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2674, 555), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2675, 571), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2676, 575), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2677, 743), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2678, 745), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2679, 747), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2680, 766), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2681, 768), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2682, 756), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2683, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2684, 732), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2685, 764), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2686, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2687, 804), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2688, 817), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2689, 823), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2690, 829), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2691, 835), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2692, 841), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2693, 847), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2694, 853), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2695, 859), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2696, 896), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2697, 902), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2698, 908), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2699, 914), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2700, 920), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2701, 926), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2702, 932), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2703, 938), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2704, 975), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2705, 981), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2706, 987), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2707, 993), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2708, 999), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2709, 1005), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2710, 1011), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2711, 1017), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2623, 383, 2712), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(811, 333), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :91:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2645, 3373), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :91:19) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2714, 3368), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :92:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2715, 497), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :93:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2716, 3159), // loc(callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :94:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2717, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2718, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2719, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2720, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1372, 332), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2721, 3374), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2722, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2723, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2724, 1660), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2725, 3288), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :95:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1391, 5), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2726, 758), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2727, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1069, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3376, 757), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3375, 3377), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2728, 3378), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1392, 1069), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2729, 782), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2730, 1074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1072, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:11) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3380, 781), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3379, 3381), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2731, 3382), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( ControlMRET ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :96:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :201:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2732, 1394), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2733, 1411), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2734, 1428), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2735, 1431), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2736, 1900), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2737, 594), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2738, 622), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2739, 649), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2740, 673), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2741, 555), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2742, 571), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2743, 575), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2744, 741), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2745, 743), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2746, 745), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2747, 747), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2748, 766), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2749, 768), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2750, 732), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2751, 764), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2752, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2753, 804), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2754, 817), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2755, 823), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2756, 829), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2757, 835), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2758, 841), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2759, 847), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2760, 853), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2761, 859), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2762, 896), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2763, 902), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2764, 908), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2765, 914), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2766, 920), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2767, 926), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2768, 932), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2769, 938), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2770, 975), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2771, 981), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2772, 987), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2773, 993), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2774, 999), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2775, 1005), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2776, 1011), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2777, 1017), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2713, 386, 2778), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(0, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :102:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(3158, 1060), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :102:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3383, 1058), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :102:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2780, 3384), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :102:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2781, 3278), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :102:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1057, 1060), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :102:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2782, 3385), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :102:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 3160), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :104:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2784, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2785, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2786, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2787, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1137, 334), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2788, 3386), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2789, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2790, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2791, 589), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2792, 3284), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2793, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2794, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2795, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2796, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1372, 335), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2797, 3387), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2798, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2799, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2800, 1660), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2801, 3288), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2802, 3190), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2803, 3191), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2804, 3192), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2805, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1401, 336), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2806, 3388), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2807, 3194), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2808, 3195), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2809, 3306), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2810, 3307), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2811, 3196), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2812, 1854), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2813, 3197), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2814, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1829, 337), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2815, 3389), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2816, 3199), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2817, 3200), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2818, 2955), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2819, 3315), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2820, 2790), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2821, 2795), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2822, 3201), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2823, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(538, 338), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2824, 3390), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2825, 2794), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2826, 3203), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2827, 754), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2828, 3323), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2829, 3204), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2830, 2297), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2831, 3205), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2832, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(629, 339), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2833, 3391), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2834, 3207), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2835, 2918), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2836, 1745), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2837, 3331), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2838, 3208), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2839, 1639), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2840, 3209), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2841, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(676, 340), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2842, 3392), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2843, 3211), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2844, 3042), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2845, 3339), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2846, 3340), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2847, 3212), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2848, 580), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2849, 581), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2850, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(570, 341), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2851, 3393), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2852, 583), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2853, 584), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2854, 3347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2855, 3348), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :109:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::GetGlobal(0, 17), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1154, 3394), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2856, 3395), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 18), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(811, 3396), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2857, 3397), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 19), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1391, 3398), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2858, 3399), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 20), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1392, 3400), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2859, 3401), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 21), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1427, 3402), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2860, 3403), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 22), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1426, 3404), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2861, 3405), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 23), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1439, 3406), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2862, 3407), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 24), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1440, 3408), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2863, 3409), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 25), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(608, 3410), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2864, 3411), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 26), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(615, 3412), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2865, 3413), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 27), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(659, 3414), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2866, 3415), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 28), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(666, 3416), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2867, 3417), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 29), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(563, 3418), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2868, 3419), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 30), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(564, 3420), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2869, 3421), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 31), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(577, 3422), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2870, 3423), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 32), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(578, 3424), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2871, 3425), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :108:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 16), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :106:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 3426), // loc(callsite( builtin Sub at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :111:10) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::GetGlobal(0, 87), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :112:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(0, 3428), // loc(callsite( Reg ( :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :112:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 3429), // loc(callsite( Reg ( :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :112:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::GetGlobal(0, 86), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :113:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(0, 3430), // loc(callsite( Reg ( :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :113:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2873, 3431), // loc(callsite( Reg ( :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :113:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::GetGlobal(0, 89), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :114:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(0, 3432), // loc(callsite( Reg ( :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :114:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2874, 3433), // loc(callsite( Reg ( :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :114:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::GetGlobal(0, 88), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(0, 3434), // loc(callsite( Reg ( :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2875, 3435), // loc(callsite( Reg ( :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :115:26) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(2872, 3427, 2876), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :111:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(2783, 1057, 2877), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(371, 1054), // loc(callsite( Reg ( :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :123:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 3436), // loc(callsite( Reg ( :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :123:18) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1054, 13), // loc(callsite( builtin Sub at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :124:7) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1054, 5), // loc(callsite( builtin Sub at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :124:33) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3437, 3438), // loc(callsite( builtin Mul at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :124:28) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2879, 3439), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :124:57) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(3437, 355), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :127:54) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3440, 3426), // loc(callsite( Reg ( :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :127:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2880, 3441), // loc(callsite( Reg ( :6:7) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :127:25) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2881, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2882, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2883, 3291), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2884, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2885, 3282), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2886, 589), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2887, 3284), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1154, 368), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2888, 3442), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(811, 370), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2889, 3443), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :129:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2890, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2891, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2892, 3297), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2893, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2894, 3285), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2895, 1660), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2896, 3288), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1391, 374), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2897, 3444), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2898, 1392), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :130:17) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(2899, 1394), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2900, 1411), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2901, 1428), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2902, 1431), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2903, 1900), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2904, 594), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2905, 622), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2906, 649), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2907, 673), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2908, 555), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2909, 571), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2910, 575), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2911, 741), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2912, 743), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2913, 745), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2914, 747), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2915, 766), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2916, 768), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(2878, 1058, 2917), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2918, 761), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2919, 771), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2920, 756), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2921, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2922, 732), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2923, 764), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2924, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2925, 804), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2926, 817), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2927, 823), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2928, 829), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2929, 835), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2930, 841), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2931, 847), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2932, 853), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2933, 859), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2934, 896), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2935, 902), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2936, 908), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2937, 914), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2938, 920), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2939, 926), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2940, 932), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2941, 938), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2942, 975), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2943, 981), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2944, 987), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2945, 993), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2946, 999), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2947, 1005), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2948, 1011), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(2949, 1017), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2779, 389, 2950), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(0, 3161), // loc(callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :137:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(2952, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2953, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2954, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2955, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1137, 322), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2956, 3445), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2957, 589), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2958, 3284), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2959, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2960, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2961, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2962, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1372, 342), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2963, 3446), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2964, 1660), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2965, 3288), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2966, 3190), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2967, 3191), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2968, 3192), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2969, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1401, 343), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2970, 3447), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2971, 3306), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2972, 3307), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2973, 3196), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2974, 1854), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2975, 3197), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2976, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1829, 344), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2977, 3448), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2978, 2955), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2979, 3315), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2980, 2790), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2981, 2795), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2982, 3201), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2983, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(538, 345), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2984, 3449), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2985, 754), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2986, 3323), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2987, 3204), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2988, 2297), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2989, 3205), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2990, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(629, 346), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2991, 3450), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2992, 1745), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2993, 3331), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(2994, 3208), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2995, 1639), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2996, 3209), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2997, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(676, 347), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2998, 3451), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2999, 3339), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3000, 3340), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3001, 3212), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3002, 580), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3003, 581), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3004, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(570, 348), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3005, 3452), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3006, 3347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3007, 3348), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :140:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::GetGlobal(0, 70), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1143, 3453), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3008, 3454), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 71), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(809, 3455), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3009, 3456), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 72), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1375, 3457), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3010, 3458), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 73), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1382, 3459), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3011, 3460), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 74), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1404, 3461), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3012, 3462), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 75), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1410, 3463), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3013, 3464), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 76), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1429, 3465), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3014, 3466), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 77), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1430, 3467), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3015, 3468), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 78), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(539, 3469), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3016, 3470), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 79), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(591, 3471), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3017, 3472), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 80), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(639, 3473), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3018, 3474), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 81), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(646, 3475), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3019, 3476), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 82), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(551, 3477), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3020, 3478), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 83), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(552, 3479), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3021, 3480), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 84), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(573, 3481), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3022, 3482), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :8:23) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 85), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(574, 3483), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3023, 3484), // loc(callsite( Reg ( :6:7) at callsite( DigestReg ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :9:24) at callsite( ControlStoreRoot ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :138:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :203:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3024, 761), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3025, 771), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3026, 756), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3027, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3028, 732), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3029, 764), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3030, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3031, 804), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3032, 817), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3033, 823), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3034, 829), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3035, 835), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3036, 841), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3037, 847), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3038, 853), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3039, 859), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3040, 896), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3041, 902), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3042, 908), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3043, 914), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3044, 920), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3045, 926), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3046, 932), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3047, 938), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3048, 975), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3049, 981), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3050, 987), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3051, 993), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3052, 999), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3053, 1005), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3054, 1011), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3055, 1017), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2951, 392, 3056), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(0, 3162), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :147:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(368, 1060), // loc(callsite( Reg ( :6:7) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :148:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3058, 3485), // loc(callsite( Reg ( :6:7) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :148:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(374, 1063), // loc(callsite( Reg ( :6:7) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :149:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3059, 3486), // loc(callsite( Reg ( :6:7) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :149:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1060, 1), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1060, 7), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1060, 6), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1060, 5), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1060, 4), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1060, 3), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1060, 2), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1060, 12), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1060, 11), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1060, 10), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1060, 9), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1060, 8), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1060, 34), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1060, 35), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1060, 36), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :154:15) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1060, 23), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :158:14) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3502, 33), // loc(callsite( builtin Sub at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :159:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(770, 1060), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 3504), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(772, 3487), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3061, 3505), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(757, 3488), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3062, 3506), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(781, 3489), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3063, 3507), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(737, 3490), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3064, 3508), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(798, 3491), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3065, 3509), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(802, 3492), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3066, 3510), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(814, 3493), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3067, 3511), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(820, 3494), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3068, 3512), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(826, 3495), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3069, 3513), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(832, 3496), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3070, 3514), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(838, 3497), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3071, 3515), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(844, 3498), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3072, 3516), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(850, 3499), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3073, 3517), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(856, 3500), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3074, 3518), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(893, 3501), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3075, 3519), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :156:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3076, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :159:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(3503, 1057), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :159:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3520, 1055), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :159:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3077, 3521), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :159:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1054, 3503), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :159:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3078, 3522), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :159:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3079, 3281), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :159:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3080, 896), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3081, 902), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3082, 908), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3083, 914), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3084, 920), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3085, 926), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3086, 932), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3087, 938), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3088, 975), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3089, 981), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3090, 987), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3091, 993), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3092, 999), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3093, 1005), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3094, 1011), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3095, 1017), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(3060, 1063, 3096), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(3502, 20), // loc(callsite( builtin Sub at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:21) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(899, 1060), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 3524), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(905, 3487), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3098, 3525), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(911, 3488), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3099, 3526), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(917, 3489), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3100, 3527), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(923, 3490), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3101, 3528), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(929, 3491), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3102, 3529), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(935, 3492), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3103, 3530), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(972, 3493), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3104, 3531), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(978, 3494), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3105, 3532), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(984, 3495), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3106, 3533), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(990, 3496), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3107, 3534), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(996, 3497), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3108, 3535), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(1002, 3498), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3109, 3536), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(1008, 3499), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3110, 3537), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(1014, 3500), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3111, 3538), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(1051, 3501), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3112, 3539), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :170:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3113, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(3523, 1057), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3540, 1055), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3114, 3541), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1054, 3523), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3115, 3542), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3116, 3281), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :173:20) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3117, 761), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3118, 771), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3119, 756), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3120, 762), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3121, 732), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3122, 764), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3123, 800), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3124, 804), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3125, 817), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3126, 823), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3127, 829), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3128, 835), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3129, 841), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3130, 847), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3131, 853), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3132, 859), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(3097, 1064, 3133), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3134, 807), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3135, 1148), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3136, 1160), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3137, 1383), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3138, 1394), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3139, 1411), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3140, 1428), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3141, 1431), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3142, 1900), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3143, 594), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3144, 622), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3145, 649), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3146, 673), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3147, 555), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3148, 571), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3149, 575), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3150, 587), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3151, 739), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3152, 741), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3153, 743), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3154, 745), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3155, 747), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3156, 766), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3157, 768), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(3057, 395, 3158), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(0, 3163), // loc(callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :183:16) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(499, 3427), // loc(callsite( builtin Mul at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :186:23) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 3543), // loc(callsite( builtin Sub at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :186:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::GetGlobal(0, 53), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :185:24) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(362, 3545), // loc(callsite( builtin Sub at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :188:14) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 589), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :188:13) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(588, 3546), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :188:13) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3161, 3547), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :188:13) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(3160, 3543, 3162), // loc(callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :186:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 587), // loc(callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :186:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(3163, 3544, 3164), // loc(callsite( ControlDone ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :186:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :205:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3165, 807), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3166, 1148), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3167, 1160), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3168, 1383), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3169, 1394), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3170, 1411), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3171, 1428), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3172, 1431), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3173, 1900), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3174, 594), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3175, 622), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3176, 649), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3177, 673), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3178, 555), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3179, 571), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3180, 575), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3181, 739), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3182, 741), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3183, 743), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3184, 745), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3185, 747), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3186, 766), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3187, 768), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3188, 761), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3189, 771), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3190, 756), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3191, 762), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3192, 732), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3193, 764), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3194, 800), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3195, 804), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3196, 817), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3197, 823), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3198, 829), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3199, 835), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3200, 841), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3201, 847), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3202, 853), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3203, 859), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3204, 896), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3205, 902), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3206, 908), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3207, 914), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3208, 920), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3209, 926), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3210, 932), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3211, 938), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3212, 975), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3213, 981), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3214, 987), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3215, 993), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3216, 999), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3217, 1005), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3218, 1011), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3219, 1017), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(3159, 398, 3220), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(2342, 443, 3221), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Sub(371, 11), // loc(callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :46:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(371, 10), // loc(callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :70:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(371, 9), // loc(callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :103:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(371, 8), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :121:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(371, 34), // loc(callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :171:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(380, 5), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(386, 13), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(570, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :201:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 3555), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :201:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(573, 542), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :201:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3223, 3556), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :201:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3224, 2115), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :81:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3225, 2121), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(575, 7), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3557, 574), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :83:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3226, 585), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(577, 502), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3227, 3559), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3228, 2135), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(370, 587), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3560, 2134), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3229, 3561), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(578, 370), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3230, 3562), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(578, 587), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3231, 3563), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3232, 578), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(588, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3233, 3564), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(739, 5), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3565, 3558), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:12) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3566, 368), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3234, 3567), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(503, 739), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :202:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3235, 3558), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :203:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1137, 3568), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(2486, 3569), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3237, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3238, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3239, 1901), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(538, 3283), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3240, 3570), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :26:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3241, 497), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :27:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3242, 811), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :28:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3243, 3368), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :29:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3244, 3159), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :30:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3245, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3246, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3247, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3248, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1372, 52), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3249, 3571), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3250, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3251, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3252, 2279), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(539, 3287), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3253, 3572), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :31:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3254, 1392), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :32:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3255, 2151), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3256, 2157), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3257, 3068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3258, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 744), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(744, 3573), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3259, 3574), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3260, 3074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(740, 741), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3575, 742), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3576, 743), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3577, 744), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3578, 745), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3579, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3261, 3580), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(742, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(743, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(744, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(745, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(741, 3581), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3585, 3582), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3586, 3583), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3587, 3584), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3588, 1391), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3262, 3589), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3263, 1394), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3264, 1411), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3265, 1428), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3266, 1431), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3267, 591), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3268, 601), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3269, 615), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3270, 629), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3271, 639), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3272, 649), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3273, 659), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3274, 673), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3275, 544), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3276, 552), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(3236, 377, 3277), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(0, 3548), // loc(callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :46:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3279, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3280, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3281, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3282, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1137, 62), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3283, 3590), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3284, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3285, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3286, 1901), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3287, 3570), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :47:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3288, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3289, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3290, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3291, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1372, 64), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3292, 3591), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3293, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3294, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3295, 2279), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3296, 3572), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :48:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1154, 3428), // loc(callsite( Reg ( :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :49:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3297, 3592), // loc(callsite( Reg ( :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :49:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(811, 3430), // loc(callsite( Reg ( :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :50:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3298, 3593), // loc(callsite( Reg ( :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :50:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1391, 3432), // loc(callsite( Reg ( :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :51:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3299, 3594), // loc(callsite( Reg ( :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :51:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1392, 3434), // loc(callsite( Reg ( :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :52:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3300, 3595), // loc(callsite( Reg ( :6:7) at callsite( ECallTerminate ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :52:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :206:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3301, 1394), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3302, 1411), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3303, 1428), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3304, 1431), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3305, 591), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3306, 601), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3307, 615), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3308, 629), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3309, 639), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3310, 649), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3311, 659), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3312, 673), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3313, 544), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3314, 552), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(3278, 380, 3315), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(0, 3549), // loc(callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :70:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3317, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3318, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3319, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3320, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3321, 3590), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3322, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3323, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3324, 1901), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3325, 3570), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :72:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3326, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3327, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3328, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3329, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3330, 3591), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3331, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3332, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3333, 2279), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3334, 3572), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3335, 3190), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3336, 3191), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3337, 3192), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3338, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1401, 65), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3339, 3596), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3340, 3194), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3341, 3195), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3342, 2280), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(594, 3305), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3343, 3597), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :74:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3344, 1426), // loc(callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :76:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3345, 2294), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :78:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1427, 622), // loc(callsite( builtin Sub at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :80:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3346, 2295), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :80:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(632, 3598), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :80:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3347, 3599), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :80:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3348, 3196), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3349, 1854), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3350, 3312), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3351, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1829, 62), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3352, 3600), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3353, 2293), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(608, 3314), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3354, 3601), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1439, 622), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3355, 3602), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3356, 1440), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :82:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3357, 2296), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1697, 740), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:12) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1391, 3603), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3358, 3604), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3359, 2157), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3360, 3068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3361, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3362, 3574), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(741, 742), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(3605, 743), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(3606, 744), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3607, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3363, 3608), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(743, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(744, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(742, 3609), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(3611, 3610), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3612, 740), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3364, 3613), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3365, 3074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(646, 746), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3614, 3073), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3366, 3615), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(745, 646), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3367, 3616), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(745, 746), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3368, 3617), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(745, 741), // loc(callsite( builtin Mul at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3618, 747), // loc(callsite( Reg ( :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3369, 3619), // loc(callsite( Reg ( :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(742, 743), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :66:35) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3620, 744), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :66:48) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3370, 2297), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(652, 5), // loc(callsite( builtin Mul at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:10) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3622, 760), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:12) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(622, 3623), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3371, 3624), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3372, 3001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3373, 3085), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 768), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(768, 3625), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(3374, 3626), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 769), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(769, 3627), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(3375, 3628), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(766, 767), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(3629, 768), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(3630, 769), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3631, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3376, 3632), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(768, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(769, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(767, 3633), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(3635, 3634), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3636, 760), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3377, 3637), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 761), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(761, 3638), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3378, 3639), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(652, 770), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3640, 3638), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3379, 3641), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(761, 652), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3380, 3642), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(761, 770), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3381, 3643), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(761, 766), // loc(callsite( builtin Mul at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:25) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3644, 771), // loc(callsite( Reg ( :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3382, 3645), // loc(callsite( Reg ( :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(767, 768), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :66:35) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3646, 769), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :66:48) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :86:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(761, 3647), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :88:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3648, 772), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :88:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3383, 3649), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :88:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(772, 3621), // loc(callsite( builtin Add at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :90:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(772, 3621), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :90:51) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3650, 3651), // loc(callsite( builtin Sub at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :90:37) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3652, 756), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :90:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3384, 3653), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :90:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3385, 659), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3386, 673), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3387, 544), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3388, 552), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(3316, 383, 3389), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(0, 3550), // loc(callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :103:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3391, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3392, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3393, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3394, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3395, 3590), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3396, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3397, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3398, 1901), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3399, 3570), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :105:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3400, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3401, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3402, 3186), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3403, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3404, 3591), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3405, 3188), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3406, 3189), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3407, 2279), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3408, 3572), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :106:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3409, 3190), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3410, 3191), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3411, 3192), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3412, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3413, 3596), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3414, 3194), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3415, 3195), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3416, 2280), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3417, 3597), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :107:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3418, 811), // loc(callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :108:12) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3419, 1426), // loc(callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :109:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3420, 2294), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :111:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3421, 2295), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :113:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3422, 3599), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :113:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3423, 3196), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3424, 1854), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3425, 3312), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3426, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3427, 3600), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3428, 2293), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3429, 3601), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3430, 3602), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3431, 1440), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ECallHostWrite ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :115:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :208:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3432, 639), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3433, 649), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3434, 659), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3435, 673), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3436, 544), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3437, 552), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(3390, 386, 3438), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(486), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(492), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:52) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(498), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:58) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 3551), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :121:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(3656, 1), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3440, 2294), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(622, 5), // loc(callsite( builtin Mul at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:10) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3658, 740), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:12) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3657, 3659), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3441, 3660), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3442, 2157), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3443, 3068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3444, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3445, 3574), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3446, 3608), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3447, 3613), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3448, 3074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(622, 746), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3661, 3073), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3449, 3662), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(745, 622), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3450, 3663), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3451, 3617), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3452, 3619), // loc(callsite( Reg ( :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :123:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(745, 3621), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :125:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3664, 760), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :125:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3453, 3665), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :125:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3655, 6), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3454, 3001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(3666, 767), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3667, 3000), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3455, 3668), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(766, 3666), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3456, 3669), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3457, 3005), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :127:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(760, 3000), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(760, 3000), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:43) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3670, 3671), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3672, 768), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3458, 3673), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3459, 3628), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(3657, 761), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3674, 3627), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3460, 3675), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(769, 3657), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3461, 3676), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(769, 761), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3462, 3677), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 770), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :136:24) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(770, 3678), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :136:24) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3463, 3679), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :136:24) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3655, 770), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3680, 37), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 771), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(771, 3682), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3464, 3683), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3681, 771), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3465, 3684), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :137:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3466, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3467, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3468, 3181), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3469, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1137, 3654), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3470, 3685), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3471, 3183), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3472, 3184), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3473, 1901), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3474, 3570), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :139:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3475, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3476, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3477, 3297), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3478, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1372, 3654), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3479, 3686), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3480, 2279), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3481, 3572), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :141:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1154, 1391), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :144:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 3687), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :144:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(3482, 771, 3483), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :143:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(811, 1392), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :146:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 3688), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :146:20) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(3484, 3682, 3485), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :143:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(771, 811), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :149:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3682, 1154), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :149:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3689, 3690), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :149:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(771, 1392), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :150:15) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3682, 1391), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :150:52) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3692, 3693), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :150:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3486, 2320), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :152:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3487, 2346), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :152:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1708, 666), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :152:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3691, 3695), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :152:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3488, 3696), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :152:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3489, 2368), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3490, 2925), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(555, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3697, 551), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3694, 3698), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3491, 3699), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :153:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(666, 551), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :156:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 3700), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :156:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(3492, 770, 3493), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :155:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(676, 555), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :158:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 3701), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :158:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(3494, 3678, 3495), // loc(callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :155:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3496, 1394), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3497, 1411), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3498, 1428), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3499, 1431), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3500, 591), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3501, 601), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3502, 629), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3503, 639), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3504, 649), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(3439, 389, 3505), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(0, 3552), // loc(callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :171:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3507, 2294), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3656, 3659), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3508, 3702), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3509, 2157), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3510, 3068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3511, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3512, 3574), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3513, 3608), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3514, 3613), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3515, 3074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3516, 3662), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3517, 3663), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3518, 3617), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3519, 3619), // loc(callsite( Reg ( :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :172:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3520, 2295), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(690, 760), // loc(callsite( builtin Add at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:12) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(622, 3703), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3521, 3704), // loc(callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :61:8) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3522, 3001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3523, 3085), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3524, 3626), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3525, 3628), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3526, 3632), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3527, 3637), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3528, 3639), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(632, 770), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3705, 3638), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3529, 3706), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(761, 632), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3530, 3707), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3531, 3643), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3532, 3645), // loc(callsite( Reg ( :6:7) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :64:24) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3648, 3638), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:96) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(768, 769), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3709, 761), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:54) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3710, 3638), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:69) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3677, 3638), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :177:45) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3708, 3711), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3713, 3712), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3714, 3638), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3708, 3654), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 3708), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3717, 349), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:60) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3716, 3718), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:42) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3719, 772), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3533, 3720), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3534, 3179), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3535, 3180), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3536, 3291), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3537, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1137, 772), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3538, 3721), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3539, 1901), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3540, 3570), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(3654, 1), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3711, 3722), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 3711), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3724, 350), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:60) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3723, 3725), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:42) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3726, 756), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3541, 3727), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3542, 3185), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3543, 1811), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3544, 3297), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3545, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1372, 756), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3546, 3728), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3547, 2279), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3548, 3572), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(3654, 7), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3712, 3729), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 3712), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3731, 351), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:60) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3730, 3732), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:42) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3733, 757), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3549, 3734), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3550, 3190), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3551, 3191), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3552, 3303), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3553, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1401, 757), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3554, 3735), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3555, 2280), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3556, 3597), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(3654, 6), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3638, 3736), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 3638), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3738, 352), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:60) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3737, 3739), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:42) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3740, 762), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3557, 3741), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :182:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3558, 3196), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3559, 1854), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3560, 3312), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3561, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1829, 762), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3562, 3742), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :105:25) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3563, 2293), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3564, 3601), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWriteUnconstrained ( zirgen/circuit/rv32im/v2/dsl/mem.zir :106:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :183:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(622, 3715), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:39) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 781), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(781, 3744), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3565, 3745), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(3743, 732), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3746, 3744), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3566, 3747), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(781, 3743), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3567, 3748), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(781, 732), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3568, 3749), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 3621), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :186:37) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(781, 3750), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :186:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3751, 737), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :186:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3569, 3752), // loc(callsite( Reg ( :6:7) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :186:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3570, 639), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3571, 649), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3572, 659), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3573, 673), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3574, 544), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3575, 552), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(3506, 392, 3576), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1229, 1148), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3578, 1160), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3579, 1383), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3580, 1394), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3581, 1411), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3582, 1428), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3583, 1431), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3584, 1900), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3585, 2278), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3586, 591), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3587, 601), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3588, 615), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3589, 629), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3590, 639), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3591, 649), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3592, 659), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3593, 673), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3594, 544), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3595, 552), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(3577, 395, 3596), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(3597, 398, 3596), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(571), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Get(576), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Get(581), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Get(586), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Get(591), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Get(596), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :33:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(3753, 11), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(3754, 10), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(3755, 9), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(3756, 23), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(3757, 24), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(3758, 53), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(3759, 3760), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(3765, 3761), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(3766, 3762), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(3767, 3763), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(3768, 3764), // loc(callsite( MachineECall ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :34:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :205:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(3769, 377), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(792, 13), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :94:16) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 792), // loc(callsite( builtin Sub at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :96:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3772, 1768), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :96:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3773, 8), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :96:31) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3771, 3774), // loc(callsite( builtin Add at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :94:37) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 1768), // loc(callsite( builtin Sub at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :98:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3772, 3776), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :98:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3777, 34), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :98:42) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3775, 3778), // loc(callsite( builtin Add at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :96:59) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3779, 383), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(626), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :132:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(631), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :134:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(3782, 13), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :162:6) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 3782), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :164:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3784, 3781), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :164:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3785, 8), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :164:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3783, 3786), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :162:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 3781), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :166:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3784, 3788), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :166:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3789, 34), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :166:33) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3787, 3790), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :164:50) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3791, 389), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(671), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :185:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(681), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :186:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(3794, 13), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :189:6) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 3794), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :191:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3796, 3793), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :191:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3797, 8), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :191:22) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3795, 3798), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :189:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 3793), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :193:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3796, 3800), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :193:18) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3801, 34), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :193:41) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3799, 3802), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :191:58) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3803, 392), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(3770, 3553), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(3805, 3780), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(3806, 3554), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(3807, 3792), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(3808, 3804), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(227), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :73:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(419), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :59:31) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :84:30) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(3810, 14), // loc(callsite( builtin Mul at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :85:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3812, 3811), // loc(callsite( builtin Add at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :85:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3813, 383), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(486), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:46) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 1764), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :128:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3815, 1), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :129:34) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1764, 3817), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :129:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3816, 3815), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :129:49) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3818, 3819), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :129:45) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3820, 389), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(621), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :62:31) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(636), // loc(callsite( builtin NondetReg at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :8:23) at callsite( DecomposeLow2 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :63:29) at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :173:32) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(3822, 3781), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3824, 3782), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:53) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3825, 3823), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:79) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 3823), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:108) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3826, 3827), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :175:96) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3781, 3782), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3829, 3823), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:54) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3830, 3827), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :176:69) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3782, 3823), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :177:29) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3832, 3827), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :177:45) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3828, 3831), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3834, 3833), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3835, 3827), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :180:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3815, 3836), // loc(callsite( builtin Add at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :194:27) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3837, 392), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(3814, 3821), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(3839, 3838), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(3753, 383), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(492), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:52) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3842, 1), // loc(callsite( builtin Add at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :130:36) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3816, 3843), // loc(callsite( builtin Mul at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :130:19) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3844, 389), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(3841, 3845), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(395), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( ECallHostReadSetup ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :78:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :207:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(3847, 383), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(498), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:58) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3849, 1), // loc(callsite( builtin Sub at callsite( ECallHostReadBytes ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :167:53) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :209:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3850, 389), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(3836, 5), // loc(callsite( builtin Mul at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :194:53) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3849, 3852), // loc(callsite( builtin Sub at callsite( ECallHostReadWords ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :194:47) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :210:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3853, 392), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(3848, 3851), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(3855, 3854), // loc(callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :204:38) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(3840, 556), // loc(callsite( Reg ( :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :214:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3598, 3857), // loc(callsite( Reg ( :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :214:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(3846, 563), // loc(callsite( Reg ( :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :215:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3599, 3858), // loc(callsite( Reg ( :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :215:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(3856, 564), // loc(callsite( Reg ( :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :216:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3600, 3859), // loc(callsite( Reg ( :6:7) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :216:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(3809, 5), // loc(callsite( builtin Sub at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:31) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3601, 1735), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3860, 798), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3861, 1734), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3602, 3862), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(764, 3860), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3603, 3863), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(764, 798), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3604, 3864), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :217:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(3809, 13), // loc(callsite( builtin Sub at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3605, 3022), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3865, 802), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3866, 3021), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3606, 3867), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(800, 3865), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3607, 3868), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(800, 802), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3608, 3869), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :218:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(3809, 23), // loc(callsite( builtin Sub at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:31) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(1, 804), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(804, 3871), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3609, 3872), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3870, 814), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3873, 3871), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3610, 3874), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(804, 3870), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3611, 3875), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(804, 814), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3612, 3876), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :219:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(3809, 24), // loc(callsite( builtin Sub at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3613, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3877, 820), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3878, 818), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3614, 3879), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(817, 3877), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3615, 3880), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(817, 820), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3616, 3881), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :220:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(3809, 53), // loc(callsite( builtin Sub at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3617, 825), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(3882, 826), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3883, 824), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3618, 3884), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(823, 3882), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3619, 3885), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(823, 826), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3620, 3886), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :221:27) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(764, 800), // loc(callsite( builtin Add at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:60) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(3887, 804), // loc(callsite( builtin Add at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:72) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(3888, 817), // loc(callsite( builtin Add at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:83) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(3889, 823), // loc(callsite( builtin Add at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:95) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(3890, 5), // loc(callsite( builtin Mul at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:121) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(368, 3891), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(829, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3621, 3893), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3622, 837), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(835, 33), // loc(callsite( builtin Mul at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:12) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(3894, 832), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(3892, 3895), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3623, 3896), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(370, 835), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3624, 2228), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3625, 846), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3897, 3151), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3626, 3898), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( ECall0 ( zirgen/circuit/rv32im/v2/dsl/inst_ecall.zir :222:25) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :82:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(3222, 446, 3627), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(376, 23), // loc(callsite( builtin Add at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:42) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(371, 3899), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(374, 56), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :110:15) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(3901, 55), // loc(callsite( builtin Mul at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :114:22) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 3901), // loc(callsite( builtin Sub at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :114:46) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(3903, 54), // loc(callsite( builtin Mul at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :114:57) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(3902, 3904), // loc(callsite( builtin Add at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :114:32) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1090, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :469:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 3906), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :469:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3629, 2740), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :469:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3630, 3900), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :470:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(0, 2755), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(3158, 2760), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3907, 2754), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3632, 3908), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(2753, 3158), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3633, 3909), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(2753, 2760), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3634, 3910), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :131:20) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(0, 807), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 3911), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1137), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3636, 3912), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3905, 808), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3637, 3913), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1143), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3638, 3914), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 809), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3639, 3915), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1148), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3640, 3916), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(57, 810), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3641, 3917), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1154), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3642, 3918), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 811), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3643, 3919), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1160), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3644, 3920), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(374, 1372), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3645, 3921), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1373), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3646, 3922), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1375), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3647, 3923), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1382), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3648, 3924), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1383), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3649, 3925), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1385), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3650, 3926), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1391), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3651, 3927), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1392), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3652, 3928), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1394), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3653, 3929), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1401), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3654, 3930), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1402), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3655, 3931), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1404), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3656, 3932), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1410), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3657, 3933), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1411), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3658, 3934), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1424), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3659, 3935), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1427), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3660, 3936), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1426), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3661, 3937), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1428), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3662, 3938), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1829), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3663, 3939), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1830), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3664, 3940), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1429), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3665, 3941), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1430), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3666, 3942), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1431), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3667, 3943), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1432), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3668, 3944), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1439), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3669, 3945), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2278, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(538, 3946), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(3947, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1900, 3948), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(3949, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(1440, 3950), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(3951, 58), // loc(callsite( builtin ExtSub at callsite( ExtReg ( :13:18) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3670, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :119:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :133:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3671, 539), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3672, 615), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3673, 639), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3674, 666), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3675, 551), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3676, 564), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3677, 573), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3678, 578), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3679, 838), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3680, 844), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3681, 850), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3682, 856), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(3635, 2753, 3683), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(539, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(0, 3953), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3685, 2294), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(622, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3686, 3954), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3687, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(591, 62), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3688, 3955), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(601, 629), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3689, 3956), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(608, 632), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3690, 3957), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(622, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(3958, 594), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(3691, 2228), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(841, 3959), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(3692, 3960), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(632, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(629, 63), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(3961, 3962), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :84:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(639, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3693, 3964), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(666, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3694, 3965), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(673, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3695, 3966), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3696, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(646, 64), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3697, 3967), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(652, 676), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3698, 3968), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(659, 544), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3699, 3969), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(2346, 649), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(844, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(3700, 3971), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(847, 3970), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(3701, 3972), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(544, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(676, 63), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(3973, 3974), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :85:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(551, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3702, 3976), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(564, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3703, 3977), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(571, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3704, 3978), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3705, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(552, 65), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3706, 3979), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(556, 570), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3707, 3980), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(563, 572), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3708, 3981), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1647, 555), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(850, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(3709, 3983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(853, 3982), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(3710, 3984), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(572, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(570, 63), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(3985, 3986), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :86:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3711, 1652), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3712, 1658), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(587, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3713, 3988), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3714, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(574, 66), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3715, 3989), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3716, 1657), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(577, 739), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3717, 3990), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(589, 575), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(856, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3718, 3992), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(859, 3991), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3719, 3993), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :87:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 2736), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(2736, 3994), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3720, 3995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(3963, 2737), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3996, 3994), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3721, 3997), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2736, 3963), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3722, 3998), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2736, 2737), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3723, 3999), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :90:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 2744), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :94:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(2744, 4000), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :94:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3724, 4001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :94:26) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 2745), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :95:28) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(2745, 4002), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :95:28) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3725, 4003), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :95:28) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2744, 29), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :96:24) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2745, 14), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :96:42) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4004, 4005), // loc(callsite( builtin Add at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :96:33) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(739, 4006), // loc(callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :96:22) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3726, 4007), // loc(callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :96:22) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 2750), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(2750, 4008), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3727, 4009), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(588, 2751), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4010, 4008), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3728, 4011), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2750, 588), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3729, 4012), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2750, 2751), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3730, 4013), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :99:23) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2750, 13), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :101:6) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4008, 3994), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :102:20) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4015, 59), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :102:24) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4014, 4016), // loc(callsite( builtin Add at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :101:30) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 3994), // loc(callsite( builtin Sub at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :103:25) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4008, 4018), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :103:20) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4019, 60), // loc(callsite( builtin Mul at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :103:37) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4017, 4020), // loc(callsite( builtin Add at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :102:58) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3994, 807), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3731, 4022), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3963, 1137), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3732, 4023), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3987, 808), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3733, 4024), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2744, 1143), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3734, 4025), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2745, 809), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3735, 4026), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(0, 1148), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3736, 4027), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4021, 810), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3737, 4028), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3738, 3918), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3975, 811), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3739, 4029), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(588, 1160), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3740, 4030), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3741, 3921), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3742, 3922), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3743, 3923), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3744, 3924), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3745, 3925), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3746, 3926), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3747, 3927), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3748, 3928), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3749, 3929), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3750, 3930), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3751, 3931), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3752, 3932), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3753, 3933), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3754, 3934), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3755, 3935), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3756, 3936), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3757, 3937), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3758, 3938), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3759, 3939), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3760, 3940), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3761, 3941), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3762, 3942), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3763, 3943), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3764, 3944), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3765, 3945), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3766, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonEcall ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :105:17) at callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :135:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndCond(3684, 2754, 3767), // loc(callsite( PoseidonEntry ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :132:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :473:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(3768, 740), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3769, 745), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3770, 766), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3771, 770), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3772, 757), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3773, 764), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3774, 804), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3775, 826), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3776, 893), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3777, 899), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3778, 905), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3779, 911), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3780, 917), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3781, 920), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3782, 923), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3783, 929), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3784, 932), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3785, 935), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3786, 972), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3787, 975), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3788, 978), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3789, 984), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3790, 987), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3791, 990), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3792, 996), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3793, 999), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3794, 1002), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3795, 1008), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3796, 1011), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3797, 1014), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3798, 1051), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3799, 1054), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3800, 1057), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3801, 1063), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3802, 1066), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3803, 1069), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3804, 1075), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3805, 1081), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(3631, 377, 3806), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(155), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(157), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(159), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(161), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(163), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(165), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(174), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(180), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(186), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:36) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(591, 4032), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3688, 4040), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3808, 3956), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3809, 3957), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3810, 2228), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3811, 3960), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(632, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4041, 629), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4032, 1), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3812, 3964), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3813, 3965), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3814, 3966), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3815, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(646, 4043), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3816, 4044), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3817, 3968), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3818, 3969), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3819, 3971), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3820, 3972), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(544, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4045, 676), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4032, 7), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3821, 3976), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3822, 3977), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3823, 3978), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3824, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(552, 4047), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3825, 4048), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3826, 3980), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3827, 3981), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3828, 3983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3829, 3984), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(572, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4049, 570), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4032, 6), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3830, 1652), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3831, 1658), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3832, 3988), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3833, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(574, 4051), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3834, 4052), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3835, 1657), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3836, 3990), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3837, 3992), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3838, 3993), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(739, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4053, 588), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4032, 5), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(740, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3839, 4056), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3840, 754), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(746, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3841, 4057), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3842, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(741, 4055), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3843, 4058), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3844, 753), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3845, 1743), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1740, 742), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(893, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3846, 4060), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(896, 4059), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3847, 4061), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(760, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4062, 747), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4032, 4), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(766, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3848, 4065), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3849, 779), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(771, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3850, 4066), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3851, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(767, 4064), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3852, 4067), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3853, 778), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3854, 1754), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1751, 768), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(899, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3855, 4069), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(902, 4068), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3856, 4070), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(756, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4071, 772), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4032, 3), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(757, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3857, 4074), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3858, 3020), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(798, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3859, 4075), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3860, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(762, 4073), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3861, 4076), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(732, 800), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3862, 4077), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(737, 802), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3863, 4078), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(798, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(4079, 781), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(905, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3864, 4081), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(908, 4080), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3865, 4082), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(802, 33), // loc(callsite( builtin Mul at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:11) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4083, 800), // loc(callsite( builtin Add at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :141:18) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4032, 2), // loc(callsite( builtin Add at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(804, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3866, 4086), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(826, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3867, 4087), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(829, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3868, 4088), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3869, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(814, 4085), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3870, 4089), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(820, 832), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3871, 4090), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(823, 835), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3872, 4091), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3893, 817), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(911, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3873, 4093), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(914, 4092), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3874, 4094), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :147:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(4031, 807), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3875, 4095), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4032, 1137), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3876, 4096), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4033, 808), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3877, 4097), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4034, 1143), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3878, 4098), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4035, 809), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3879, 4099), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4036, 1148), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3880, 4100), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(60, 810), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3881, 4101), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3882, 3918), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4037, 811), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3883, 4102), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4038, 1160), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3884, 4103), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4039, 1372), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3885, 4104), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3886, 3922), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3887, 3923), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3888, 3924), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3889, 3925), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3890, 3926), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3891, 3927), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3892, 3928), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3893, 3929), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3894, 3930), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3895, 3931), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3896, 3932), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3897, 3933), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3898, 3934), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3899, 3935), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3900, 3936), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3901, 3937), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4042, 1428), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3902, 4105), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4046, 1829), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3903, 4106), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4050, 1830), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3904, 4107), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4054, 1429), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3905, 4108), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4063, 1430), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3906, 4109), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4072, 1431), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3907, 4110), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4084, 1432), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3908, 4111), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3895, 1439), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3909, 4112), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3910, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :156:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :474:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3911, 917), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3912, 920), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3913, 923), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3914, 929), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3915, 932), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3916, 935), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3917, 972), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3918, 975), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3919, 978), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3920, 984), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3921, 987), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3922, 990), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3923, 996), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3924, 999), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3925, 1002), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3926, 1008), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3927, 1011), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3928, 1014), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3929, 1051), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3930, 1054), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3931, 1057), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3932, 1063), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3933, 1066), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3934, 1069), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3935, 1075), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(3936, 1081), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(3807, 380, 3937), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(168), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(192), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(198), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(204), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(210), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(216), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(222), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(228), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(234), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(240), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(246), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(252), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(258), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(264), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(270), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(276), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(282), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(288), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(294), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(300), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(306), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(312), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(318), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(324), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(330), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(354), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(348), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4138, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4139, 4140), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(342), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4141, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4142, 4143), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(336), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4144, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4145, 4146), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:33) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4034, 4113), // loc(callsite( builtin Add at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :232:19) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 4003), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3939, 4009), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 2751), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(2751, 4149), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3940, 4150), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2745, 2750), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4151, 2751), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4152, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3941, 4153), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(2751, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2750, 4154), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4155, 4148), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(3942, 4156), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:13) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(4037, 1), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4037, 7), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4037, 6), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4037, 5), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4037, 4), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4037, 3), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4037, 2), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:28) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4037, 12), // loc(callsite( builtin Add at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:65) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4130, 4131), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4132, 4133), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4131, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4167, 4166), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4133, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4169, 4165), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4166, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4171, 4170), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4165, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4173, 4168), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4170, 4174), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4168, 4172), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4134, 4135), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4136, 4137), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4135, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4179, 4178), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4137, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4181, 4177), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4178, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4183, 4182), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4177, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4185, 4180), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4182, 4186), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4180, 4184), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(0, 3995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 2737), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2737, 4189), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(3944, 4190), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3945, 4001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(2736, 2737), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4191, 2744), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4192, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3946, 4193), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2744, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2737, 4194), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4195, 4036), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3947, 4196), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :176:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(591, 4037), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3688, 4197), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3949, 3956), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3950, 3957), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3951, 2228), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(3952, 3960), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(3948, 2736, 3953), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3951, 838), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(3954, 2737, 3955), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3949, 2228), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(3957, 3960), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(3956, 2744, 3958), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(401), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4198, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4198, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(377), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4201, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4199, 4200), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4203, 4202), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(407), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4205, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4205, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(383), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4208, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4206, 4207), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4210, 4209), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4198, 4201), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4212, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(371), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(3847, 4214), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4215, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4205, 4208), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4217, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2736, 4216), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4219, 4218), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(0, 3964), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3960, 3965), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3961, 3966), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3962, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(646, 4157), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3963, 4221), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3964, 3968), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3965, 3969), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3966, 3971), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(3967, 3972), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(3959, 2736, 3968), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3966, 844), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(3969, 2737, 3970), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3964, 3971), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(3972, 3972), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(3971, 2744, 3973), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(455), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4222, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4222, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(431), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4225, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4223, 4224), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4227, 4226), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(461), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4229, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4229, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(437), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4232, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4230, 4231), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4234, 4233), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4222, 4225), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4236, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(425), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(3050, 4238), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4239, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4229, 4232), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4241, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2736, 4240), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4243, 4242), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(0, 3976), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3975, 3977), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3976, 3978), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3977, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(552, 4158), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3978, 4245), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3979, 3980), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3980, 3981), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3981, 3983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(3982, 3984), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(3974, 2736, 3983), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3981, 850), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(3984, 2737, 3985), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3979, 3983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(3987, 3984), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(3986, 2744, 3988), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(509), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4246, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4246, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(485), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4249, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4247, 4248), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4251, 4250), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(515), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4253, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4253, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(491), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4256, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4254, 4255), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4258, 4257), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4246, 4249), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4260, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(479), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(3057, 4262), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4263, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4253, 4256), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4265, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2736, 4264), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4267, 4266), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(0, 1652), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3990, 1658), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3991, 3988), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3992, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(574, 4159), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3993, 4269), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3994, 1657), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3995, 3990), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3996, 3992), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(3997, 3993), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(3989, 2736, 3998), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3996, 856), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(3999, 2737, 4000), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(3994, 3992), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4002, 3993), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(4001, 2744, 4003), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(561), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4270, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4270, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(539), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4273, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4271, 4272), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4275, 4274), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(566), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4277, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4277, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(545), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4280, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4278, 4279), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4282, 4281), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4270, 4273), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4284, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(533), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Get(556), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(4287, 4286), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4288, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4277, 4280), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4290, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2736, 4289), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4292, 4291), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(0, 4056), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4005, 754), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4006, 4057), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4007, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(741, 4160), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4008, 4294), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4009, 753), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4010, 1743), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4011, 4060), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4012, 4061), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(4004, 2736, 4013), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4011, 893), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(4014, 2737, 4015), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4009, 4060), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4017, 4061), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(4016, 2744, 4018), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(788, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(788, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(3756, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4295, 4296), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4298, 4297), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1760, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1760, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(3757, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4300, 4301), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4303, 4302), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(788, 3756), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4305, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(784, 3755), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4307, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1760, 3757), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4309, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2736, 4308), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4311, 4310), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(0, 4065), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4020, 779), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4021, 4066), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4022, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(767, 4161), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4023, 4313), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4024, 778), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4025, 1754), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4026, 4069), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4027, 4070), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(4019, 2736, 4028), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4026, 899), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(4029, 2737, 4030), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4024, 4069), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4032, 4070), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(4031, 2744, 4033), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(795, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(795, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(3782, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4314, 4315), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4317, 4316), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1768, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1768, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(3823, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4319, 4320), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4322, 4321), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(795, 3782), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4324, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(792, 3781), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4326, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1768, 3823), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4328, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2736, 4327), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4330, 4329), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(0, 4074), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4035, 3020), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4036, 4075), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4037, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(762, 4162), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4038, 4332), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4039, 4077), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4040, 4078), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4041, 4081), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4042, 4082), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(4034, 2736, 4043), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4041, 905), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(4044, 2737, 4045), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4039, 4081), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4047, 4082), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(4046, 2744, 4048), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(696), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4333, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4333, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(676), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :67:30) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :120:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4336, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4334, 4335), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4338, 4337), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(701), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Mul(4340, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4340, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(3794, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4341, 4342), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4344, 4343), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4333, 4336), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4346, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(691), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :27:29) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :112:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))))) +PolyExtStep::Sub(4348, 3793), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4349, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4340, 3794), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4351, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2736, 4350), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4353, 4352), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(0, 4086), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4050, 4087), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4051, 4088), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4052, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(814, 4163), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4053, 4355), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4054, 4090), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4055, 4091), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4056, 4093), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4057, 4094), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :129:16) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(4049, 2736, 4058), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4056, 911), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(4059, 2737, 4060), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4054, 4093), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4062, 4094), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :121:13) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndCond(4061, 2744, 4063), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1188, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1188, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1184, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4356, 4357), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4359, 4358), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1189, 2736), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1189, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1185, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4361, 4362), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4364, 4363), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1188, 1184), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :122:33) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4366, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1187, 1183), // loc(callsite( builtin Sub at callsite( MemoryPageIn ( zirgen/circuit/rv32im/v2/dsl/mem.zir :114:36) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :130:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4368, 2737), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1189, 1185), // loc(callsite( builtin Sub at callsite( MemoryPageOut ( zirgen/circuit/rv32im/v2/dsl/mem.zir :123:16) at callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :131:19) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4370, 2744), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2736, 4369), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4372, 4371), // loc(callsite( MemoryGet ( zirgen/circuit/rv32im/v2/dsl/mem.zir :128:12) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :178:15) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::GetGlobal(0, 52), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::GetGlobal(0, 51), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4374, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4375, 4376), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::GetGlobal(0, 50), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4377, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4378, 4379), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::GetGlobal(0, 49), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4380, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4381, 4382), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :160:14) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4383, 67), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4213, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4385, 67), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4386, 58), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4384, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4220, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4389, 4384), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4387, 4390), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4388, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4237, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4393, 4388), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4391, 4394), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4392, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4244, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4397, 4392), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4395, 4398), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4396, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4261, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4401, 4396), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4399, 4402), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4400, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4268, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4405, 4400), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4403, 4406), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4404, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4285, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4409, 4404), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4407, 4410), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4408, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4293, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4413, 4408), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4411, 4414), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4412, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4306, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4417, 4412), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4415, 4418), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4416, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4312, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4421, 4416), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4419, 4422), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4420, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4325, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4425, 4420), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4423, 4426), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4424, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4331, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4429, 4424), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4427, 4430), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4428, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4347, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4433, 4428), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4431, 4434), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4432, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4354, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4437, 4432), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4435, 4438), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4436, 4383), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:30) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4367, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4441, 4436), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4439, 4442), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4373, 58), // loc(callsite( builtin MakeExt at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:81) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4444, 4440), // loc(callsite( builtin ExtMul at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:73) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(4443, 4445), // loc(callsite( builtin ExtAdd at callsite( PolyEvalStateReduce ( zirgen/circuit/rv32im/v2/dsl/poly.zir :14:55) at callsite( PolyEval ( zirgen/circuit/rv32im/v2/dsl/poly.zir :18:11) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :170:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(4440, 4383), // loc(callsite( builtin ExtMul at callsite( Pow ( zirgen/circuit/rv32im/v2/dsl/poly.zir :10:4) at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :171:29) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4147, 4447), // loc(callsite( builtin ExtMul at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :171:17) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4448, 4446), // loc(callsite( builtin ExtAdd at callsite( ShiftPoly ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :171:10) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :180:23) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4204, 4211), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4228, 4235), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4211, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4452, 4451), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4235, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4454, 4450), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4451, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4456, 4455), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4450, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4458, 4453), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4455, 4459), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4453, 4457), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4252, 4259), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4276, 4283), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4259, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4464, 4463), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4283, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4466, 4462), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4463, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4468, 4467), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4462, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4470, 4465), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4467, 4471), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4465, 4469), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4299, 4304), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4318, 4323), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4304, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4476, 4475), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4323, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4478, 4474), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4475, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4480, 4479), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4474, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4482, 4477), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4479, 4483), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4477, 4481), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4339, 4345), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4360, 4365), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4345, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4488, 4487), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4365, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4490, 4486), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4487, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4492, 4491), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4486, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4494, 4489), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4491, 4495), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4489, 4493), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4460, 4472), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4459, 4471), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4461, 4473), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4457, 4469), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4498, 4484), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4499, 4483), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4500, 4485), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4501, 4481), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4502, 4496), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4503, 4495), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4504, 4497), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4505, 4493), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4506, 4175), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4507, 4174), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4508, 4176), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4509, 4172), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4510, 4187), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4511, 4186), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4512, 4188), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4513, 4184), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4460, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4459, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4461, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4457, 4517), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4472, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4471, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4473, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4469, 4517), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4484, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4483, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4485, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4481, 4517), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4496, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4495, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4497, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4493, 4517), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4175, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4174, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4176, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4172, 4517), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4187, 4514), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4186, 4515), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4188, 4516), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4184, 4517), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4064, 4095), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4065, 4096), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4066, 4097), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4067, 4098), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4068, 4099), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4069, 4100), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(68, 810), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4070, 4542), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4071, 3918), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4164, 811), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4072, 4543), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4073, 4103), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4074, 4104), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4518, 1373), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4075, 4544), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4519, 1375), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4076, 4545), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4520, 1382), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4077, 4546), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4521, 1383), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4078, 4547), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4522, 1385), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4079, 4548), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4523, 1391), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4080, 4549), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4524, 1392), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4081, 4550), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4525, 1394), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4082, 4551), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4526, 1401), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4083, 4552), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4527, 1402), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4084, 4553), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4528, 1404), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4085, 4554), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4529, 1410), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4086, 4555), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4530, 1411), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4087, 4556), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4531, 1424), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4088, 4557), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4532, 1427), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4089, 4558), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4533, 1426), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4090, 4559), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4534, 1428), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4091, 4560), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4535, 1829), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4092, 4561), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4536, 1830), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4093, 4562), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4537, 1429), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4094, 4563), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4538, 1430), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4095, 4564), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4539, 1431), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4096, 4565), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4540, 1432), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4097, 4566), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4541, 1439), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4098, 4567), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3951, 4449), // loc(callsite( builtin ExtSub at callsite( ExtReg ( :13:18) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4099, 4568), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonLoadInShort ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :194:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :234:25) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndCond(3943, 2745, 4100), // loc(callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(4211, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4569, 4204), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4235, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4571, 4228), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4259, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4573, 4252), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4283, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4575, 4276), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4304, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4577, 4299), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4323, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4579, 4318), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4345, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4581, 4339), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4365, 33), // loc(callsite( builtin Mul at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:8) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4583, 4360), // loc(callsite( builtin Add at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :206:30) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4070, 4101), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1154), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4102, 4585), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4103, 4543), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4104, 4103), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4105, 4104), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4570, 1373), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4106, 4586), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4572, 1375), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4107, 4587), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4574, 1382), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4108, 4588), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4576, 1383), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4109, 4589), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4578, 1385), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4110, 4590), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4580, 1391), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4111, 4591), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4582, 1392), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4112, 4592), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4584, 1394), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4113, 4593), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4122, 1401), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4114, 4594), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4123, 1402), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4115, 4595), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4124, 1404), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4116, 4596), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4125, 1410), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4117, 4597), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4126, 1411), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4118, 4598), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4127, 1424), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4119, 4599), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4128, 1427), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4120, 4600), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4129, 1426), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4121, 4601), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4130, 1428), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4122, 4602), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4131, 1829), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4123, 4603), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4132, 1830), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4124, 4604), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4133, 1429), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4125, 4605), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4134, 1430), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4126, 4606), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4135, 1431), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4127, 4607), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4136, 1432), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4128, 4608), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4137, 1439), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4129, 4609), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4130, 4568), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonLoadInLow ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :211:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :235:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndCond(4101, 2750, 4131), // loc(callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(4114, 4115), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4116, 4117), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4115, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4612, 4611), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4117, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4614, 4610), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4611, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4616, 4615), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4610, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4618, 4613), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4615, 4619), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4613, 4617), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4118, 4119), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4120, 4121), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4119, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4624, 4623), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4121, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4626, 4622), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4623, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4628, 4627), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4622, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4630, 4625), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4627, 4631), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4625, 4629), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4620, 4632), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4619, 4631), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4621, 4633), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4617, 4629), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4570, 4572), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4574, 4576), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4572, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4640, 4639), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4576, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4642, 4638), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4639, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4644, 4643), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4638, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4646, 4641), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4643, 4647), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4641, 4645), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4578, 4580), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4582, 4584), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4580, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4652, 4651), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4584, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4654, 4650), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4651, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4656, 4655), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4650, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4658, 4653), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4655, 4659), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4653, 4657), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4634, 4648), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4635, 4647), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4636, 4649), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4637, 4645), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4662, 4660), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4663, 4659), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4664, 4661), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4665, 4657), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4666, 4175), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4667, 4174), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4668, 4176), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4669, 4172), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4670, 4187), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4671, 4186), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4672, 4188), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4673, 4184), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4620, 4674), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4619, 4675), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4621, 4676), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4617, 4677), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4632, 4674), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4631, 4675), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4633, 4676), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4629, 4677), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4648, 4674), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4647, 4675), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4649, 4676), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4645, 4677), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4660, 4674), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4659, 4675), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4661, 4676), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4657, 4677), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4175, 4674), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4174, 4675), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4176, 4676), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4172, 4677), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4187, 4674), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4186, 4675), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4188, 4676), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4184, 4677), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:117) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4678, 1373), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4075, 4702), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4679, 1375), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4133, 4703), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4680, 1382), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4134, 4704), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4681, 1383), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4135, 4705), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4682, 1385), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4136, 4706), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4683, 1391), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4137, 4707), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4684, 1392), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4138, 4708), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4685, 1394), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4139, 4709), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4686, 1401), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4140, 4710), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4687, 1402), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4141, 4711), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4688, 1404), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4142, 4712), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4689, 1410), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4143, 4713), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4690, 1411), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4144, 4714), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4691, 1424), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4145, 4715), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4692, 1427), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4146, 4716), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4693, 1426), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4147, 4717), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4694, 1428), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4148, 4718), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4695, 1829), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4149, 4719), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4696, 1830), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4150, 4720), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4697, 1429), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4151, 4721), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4698, 1430), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4152, 4722), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4699, 1431), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4153, 4723), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4700, 1432), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4154, 4724), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4701, 1439), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4155, 4725), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4156, 4568), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonLoadInHigh ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :228:17) at callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :236:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndCond(4132, 2751, 4157), // loc(callsite( PoseidonLoadIn ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :233:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :475:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4158, 917), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4159, 920), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4160, 923), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4161, 929), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4162, 932), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4163, 935), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4164, 972), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4165, 975), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4166, 978), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4167, 984), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4168, 987), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4169, 990), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4170, 996), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4171, 999), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4172, 1002), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4173, 1008), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4174, 1011), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4175, 1014), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4176, 1051), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4177, 1054), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4178, 1057), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4179, 1063), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4180, 1066), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4181, 1069), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4182, 1075), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4183, 1081), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(3938, 383, 4184), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1228, 3911), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4186, 3912), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(0, 808), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4187, 4726), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(0, 1143), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4188, 4727), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(0, 809), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4189, 4728), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4190, 4027), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(0, 810), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4191, 4729), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4192, 3918), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4193, 3919), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4194, 3920), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(0, 1372), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4195, 4730), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4196, 3922), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4197, 3923), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4198, 3924), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4199, 3925), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4200, 3926), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4201, 3927), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4202, 3928), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4203, 3929), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4204, 3930), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4205, 3931), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4206, 3932), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4207, 3933), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4208, 3934), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4209, 3935), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4210, 3936), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4211, 3937), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4212, 3938), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4213, 3939), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4214, 3940), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4215, 3941), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4216, 3942), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4217, 3943), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4218, 3944), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4219, 3945), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4220, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :61:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :476:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4221, 539), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4222, 615), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4223, 639), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4224, 666), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4225, 551), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4226, 564), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4227, 573), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4228, 578), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4229, 740), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4230, 745), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4231, 766), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4232, 770), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4233, 757), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4234, 764), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4235, 804), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4236, 826), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4237, 838), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4238, 844), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4239, 850), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4240, 856), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4241, 893), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4242, 899), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4243, 905), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4244, 911), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4245, 917), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4246, 920), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4247, 923), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4248, 929), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4249, 932), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4250, 935), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4251, 972), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4252, 975), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4253, 978), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4254, 984), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4255, 987), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4256, 990), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4257, 996), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4258, 999), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4259, 1002), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4260, 1008), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4261, 1011), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4262, 1014), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4263, 1051), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4264, 1054), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4265, 1057), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4266, 1063), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4267, 1066), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4268, 1069), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4269, 1075), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4270, 1081), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(4185, 386, 4271), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(4272, 389, 4271), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1, 4035), // loc(callsite( builtin Sub at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(4033, 1), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4033, 7), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4033, 6), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4033, 5), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4033, 4), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4033, 3), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4033, 2), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:35) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4031, 44), // loc(callsite( builtin Mul at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :269:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 4031), // loc(callsite( builtin Sub at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :269:62) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(591, 4033), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(3688, 4741), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4274, 3956), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4275, 3957), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4276, 2228), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4277, 3960), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(4042, 4114), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4278, 4742), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4279, 3964), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4280, 3965), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4281, 3966), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4282, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(646, 4732), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4283, 4743), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4284, 3968), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4285, 3969), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4286, 3971), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4287, 3972), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(4046, 4115), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4288, 4744), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4289, 3976), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4290, 3977), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4291, 3978), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4292, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(552, 4733), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4293, 4745), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4294, 3980), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4295, 3981), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4296, 3983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4297, 3984), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(4050, 4116), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4298, 4746), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4299, 1652), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4300, 1658), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4301, 3988), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4302, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(574, 4734), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4303, 4747), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4304, 1657), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4305, 3990), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4306, 3992), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4307, 3993), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(4054, 4117), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4308, 4748), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4309, 4056), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4310, 754), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4311, 4057), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4312, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(741, 4735), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4313, 4749), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4314, 753), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4315, 1743), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4316, 4060), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4317, 4061), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(4063, 4118), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4318, 4750), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4319, 4065), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4320, 779), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4321, 4066), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4322, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(767, 4736), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4323, 4751), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4324, 778), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4325, 1754), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4326, 4069), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4327, 4070), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(4072, 4119), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4328, 4752), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4329, 4074), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4330, 3020), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4331, 4075), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4332, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(762, 4737), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4333, 4753), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4334, 4077), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4335, 4078), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4336, 4081), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4337, 4082), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(4084, 4120), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4338, 4754), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4339, 4086), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4340, 4087), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4341, 4088), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4342, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(814, 4738), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4343, 4755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4344, 4090), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4345, 4091), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4346, 4093), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4347, 4094), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadElem ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :140:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :264:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(3895, 4121), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4348, 4756), // loc(callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :265:11) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4349, 3995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4036, 2737), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4757, 3994), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4350, 4758), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2736, 4036), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4351, 4759), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4352, 3999), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :267:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2736, 13), // loc(callsite( builtin Mul at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :268:16) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(3994, 57), // loc(callsite( builtin Mul at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :268:56) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4760, 4761), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :268:39) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4740, 4762), // loc(callsite( builtin Mul at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :269:80) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4739, 4763), // loc(callsite( builtin Add at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :269:57) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4353, 4095), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4354, 4096), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4355, 4097), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4356, 4098), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4357, 4099), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4358, 4100), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4764, 810), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4359, 4765), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4360, 3918), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4361, 3919), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4362, 3920), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4363, 4104), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4114, 1373), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4364, 4766), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4115, 1375), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4365, 4767), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4116, 1382), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4366, 4768), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4117, 1383), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4367, 4769), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4118, 1385), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4368, 4770), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4119, 1391), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4369, 4771), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4120, 1392), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4370, 4772), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4121, 1394), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4371, 4773), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4372, 4594), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4373, 4595), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4374, 4596), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4375, 4597), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4376, 4598), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4377, 4599), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4378, 4600), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4379, 4601), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4380, 4602), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4381, 4603), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4382, 4604), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4383, 4605), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4384, 4606), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4385, 4607), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4386, 4608), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4387, 4609), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4388, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonCheckOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :277:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:41) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4389, 917), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4390, 920), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4391, 923), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4392, 929), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4393, 932), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4394, 935), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4395, 972), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4396, 975), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4397, 978), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4398, 984), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4399, 987), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4400, 990), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4401, 996), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4402, 999), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4403, 1002), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4404, 1008), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4405, 1011), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4406, 1014), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4407, 1051), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4408, 1054), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4409, 1057), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4410, 1063), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4411, 1066), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4412, 1069), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(0, 4035, 4413), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(917, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 4774), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4114, 629), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4775, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(920, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4415, 4777), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(632, 4776), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4416, 4778), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4417, 3995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(70, 632), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 629), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(923, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4419, 4780), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(926, 4779), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4420, 4781), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4418, 2736, 4421), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(69, 632), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 4780), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(926, 4782), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4423, 4783), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4422, 3994, 4424), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4425, 3953), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4426, 2294), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(622, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4427, 4784), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4428, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4429, 4741), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4430, 2228), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4431, 3960), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4432, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4433, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(929, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4434, 4785), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4115, 676), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4786, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4435, 2047), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(544, 4787), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4436, 4788), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4437, 4190), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(70, 544), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 676), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4439, 2050), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(938, 4789), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4440, 4790), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4438, 2737, 4441), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(69, 544), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 2050), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(938, 4791), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4443, 4792), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4442, 4189, 4444), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4445, 3964), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4446, 3965), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(673, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4447, 4793), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4448, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4449, 4743), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4450, 3971), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4451, 3972), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4452, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4453, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(972, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4454, 4794), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4116, 570), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4795, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4455, 2052), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(572, 4796), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4456, 4797), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4457, 4001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(70, 572), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 570), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(978, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4459, 4799), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(981, 4798), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4460, 4800), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4458, 2744, 4461), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(69, 572), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 4799), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(981, 4801), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4463, 4802), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4462, 4000, 4464), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4465, 3976), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4466, 3977), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(571, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4467, 4803), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4468, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4469, 4745), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4470, 3983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4471, 3984), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4472, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4473, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(984, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4474, 4804), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4117, 588), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4805, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(987, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4475, 4807), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(739, 4806), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4476, 4808), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4477, 4003), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(70, 739), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 588), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4479, 2061), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(993, 4809), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4480, 4810), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4478, 2745, 4481), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(69, 739), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 2061), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(993, 4811), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4483, 4812), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4482, 4002, 4484), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4485, 1652), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4486, 1658), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(587, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4487, 4813), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4488, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4489, 4747), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4490, 3992), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4491, 3993), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4492, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4493, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(996, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4494, 4814), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4118, 747), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4815, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(999, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4495, 4817), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(760, 4816), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4496, 4818), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4497, 4009), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(70, 760), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 747), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1002, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4499, 4820), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1005, 4819), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4500, 4821), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4498, 2750, 4501), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(69, 760), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 4820), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1005, 4822), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4503, 4823), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4502, 4008, 4504), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4505, 4056), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4506, 754), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(746, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4507, 4824), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4508, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4509, 4749), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4510, 4060), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4511, 4061), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4512, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4513, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1008, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4514, 4825), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4119, 772), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4826, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1011, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4515, 4828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(756, 4827), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4516, 4829), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4517, 4150), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(70, 756), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 772), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1014, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4519, 4831), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1017, 4830), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4520, 4832), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4518, 2751, 4521), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(69, 756), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 4831), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1017, 4833), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4523, 4834), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4522, 4149, 4524), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4525, 4065), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4526, 779), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(771, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4527, 4835), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4528, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4529, 4751), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4530, 4069), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4531, 4070), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4532, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4533, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1051, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4534, 4836), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4120, 800), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4837, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1054, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4535, 4839), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(802, 4838), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4536, 4840), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4537, 2755), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(70, 802), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 800), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1057, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4539, 4842), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1060, 4841), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4540, 4843), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4538, 2753, 4541), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(69, 802), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 4842), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1060, 4844), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4543, 4845), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4542, 2754, 4544), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4545, 4074), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4546, 3020), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(798, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4547, 4846), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4548, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4549, 4753), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4550, 4081), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4551, 4082), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4552, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4553, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1063, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4554, 4847), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4121, 832), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4848, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1066, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4555, 4850), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(835, 4849), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4556, 4851), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 2760), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(2760, 4852), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(4557, 4853), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(70, 835), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 832), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :291:10) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1069, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4559, 4855), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1072, 4854), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4560, 4856), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :292:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4558, 2760, 4561), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(69, 835), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 4855), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1072, 4857), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4563, 4858), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :294:12) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4562, 4852, 4564), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :302:24) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4565, 4086), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4566, 4087), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(829, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4567, 4859), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4568, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4569, 4755), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4570, 4093), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4571, 4094), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4572, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4573, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :303:23) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 2761), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(2761, 4860), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(4574, 4861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4036, 2763), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4862, 4860), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4575, 4863), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2761, 4036), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4576, 4864), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2761, 2763), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4577, 4865), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :307:22) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2761, 13), // loc(callsite( builtin Mul at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :308:16) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4860, 57), // loc(callsite( builtin Mul at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :308:56) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4866, 4867), // loc(callsite( builtin Add at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :308:39) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4740, 4868), // loc(callsite( builtin Mul at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :311:25) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4739, 4869), // loc(callsite( builtin Add at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :310:46) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4578, 4095), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4579, 4096), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4580, 4097), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4581, 4098), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4582, 4099), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4583, 4100), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4870, 810), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4584, 4871), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4585, 3918), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4586, 3919), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4587, 3920), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4588, 4104), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4589, 4766), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4590, 4767), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4591, 4768), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4592, 4769), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4593, 4770), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4594, 4771), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4595, 4772), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4596, 4773), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4597, 4594), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4598, 4595), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4599, 4596), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4600, 4597), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4601, 4598), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4602, 4599), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4603, 4600), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4604, 4601), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4605, 4602), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4606, 4603), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4607, 4604), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4608, 4605), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4609, 4606), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4610, 4607), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4611, 4608), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4612, 4609), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4613, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonStoreOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :313:17) at callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:80) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndCond(4414, 4731, 4614), // loc(callsite( PoseidonDoOut ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :317:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :478:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4615, 1075), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4616, 1081), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(4273, 392, 4617), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(54, 4033), // loc(callsite( builtin Sub at callsite( NodeAddrToIdx ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :337:40) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :442:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4872, 71), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( NodeAddrToIdx ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :337:57) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :442:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 4001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4619, 4003), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4620, 4009), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4621, 4150), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4622, 2755), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4623, 4853), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2744, 2745), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4874, 2750), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4875, 2751), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4876, 2753), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4877, 2760), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4878, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4624, 4879), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(2750, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2751, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2753, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2760, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(2745, 4880), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4884, 4881), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4885, 4882), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4886, 4883), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4887, 2737), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4625, 4888), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :446:26) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4626, 4774), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :341:25) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2736, 629), // loc(callsite( builtin Sub at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:11) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4889, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:20) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1075, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :26:22) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4627, 4891), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :26:22) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1078, 4890), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4628, 4892), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :448:9) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 4875), // loc(callsite( builtin Sub at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :449:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(4873, 1), // loc(callsite( builtin Add at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(2736, 4894), // loc(callsite( builtin Sub at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:12) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 4777), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :341:25) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4895, 632), // loc(callsite( builtin Sub at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:11) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4896, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:20) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1081, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :26:22) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4630, 4898), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :26:22) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1084, 4897), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4631, 4899), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :451:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(4629, 4875, 4632), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :449:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(4873, 1), // loc(callsite( builtin Sub at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :454:12) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(4900, 2736), // loc(callsite( builtin Sub at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :454:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(4901, 632), // loc(callsite( builtin Sub at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:11) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :454:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4902, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:20) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :454:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1084, 4903), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :454:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4631, 4904), // loc(callsite( U8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :27:8) at callsite( IsU24 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :342:9) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :454:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(4633, 4893, 4634), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :449:4) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(2737, 374), // loc(callsite( builtin Sub at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:11) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4635, 4861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:10) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4905, 2761), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:10) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4636, 4906), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :457:10) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(2736, 12), // loc(callsite( builtin Mul at callsite( NodeIdxToAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :338:51) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :349:34) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(54, 4907), // loc(callsite( builtin Sub at callsite( NodeIdxToAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :338:38) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :349:34) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2736, 7), // loc(callsite( builtin Mul at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :358:34) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(4909, 1), // loc(callsite( builtin Add at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :358:38) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4910, 12), // loc(callsite( builtin Mul at callsite( NodeIdxToAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :338:51) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :358:33) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(54, 4911), // loc(callsite( builtin Sub at callsite( NodeIdxToAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :338:38) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :358:33) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4908, 808), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3637, 4913), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4638, 3914), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4639, 3915), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4640, 3916), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4641, 4101), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4642, 3918), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4912, 811), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4643, 4914), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1160), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4644, 4915), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4645, 4730), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4646, 3922), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4647, 3923), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4648, 3924), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4649, 3925), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4650, 3926), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4651, 3927), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4652, 3928), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4653, 3929), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4654, 3930), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4655, 3931), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4656, 3932), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4657, 3933), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4658, 3934), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4659, 3935), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4660, 3936), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4661, 3937), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4662, 3938), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4663, 3939), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4664, 3940), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4665, 3941), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4666, 3942), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4667, 3943), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4668, 3944), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4669, 3945), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4670, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingLoadNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :354:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :459:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndCond(4637, 2744, 4671), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(2736, 72), // loc(callsite( builtin Sub at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :367:13) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4916, 20), // loc(callsite( builtin Mul at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :380:20) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4638, 4727), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4673, 3915), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4674, 3916), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4675, 4101), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4676, 3918), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4917, 811), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4677, 4918), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(24, 1160), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4678, 4919), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 1372), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4679, 4920), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4680, 3922), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4681, 3923), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4682, 3924), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4683, 3925), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4684, 3926), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4685, 3927), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4686, 3928), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4687, 3929), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4688, 3930), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4689, 3931), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4690, 3932), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4691, 3933), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4692, 3934), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4693, 3935), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4694, 3936), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4695, 3937), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4696, 3938), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4697, 3939), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4698, 3940), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4699, 3941), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4700, 3942), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4701, 3943), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4702, 3944), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4703, 3945), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4704, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingLoadPage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :376:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :460:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndCond(4672, 2745, 4705), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(55, 808), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3637, 4921), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4707, 4727), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4708, 4728), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4709, 4027), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 810), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4710, 4922), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4711, 3918), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4712, 3919), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4713, 3920), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(7, 1372), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4714, 4923), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4715, 3922), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4716, 3923), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4717, 3924), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4718, 3925), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4719, 3926), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4720, 3927), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4721, 3928), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4722, 3929), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4723, 3930), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4724, 3931), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4725, 3932), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4726, 3933), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4727, 3934), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4728, 3935), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4729, 3936), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4730, 3937), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4731, 3938), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4732, 3939), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4733, 3940), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4734, 3941), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4735, 3942), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4736, 3943), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4737, 3944), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4738, 3945), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4739, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingLoadDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :390:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :461:28) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndCond(4706, 2750, 4740), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4673, 4728), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(7, 1148), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4742, 4924), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4743, 4101), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4744, 3918), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4745, 4918), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4746, 4919), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(6, 1372), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4747, 4925), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4748, 3922), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4749, 3923), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4750, 3924), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4751, 3925), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4752, 3926), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4753, 3927), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4754, 3928), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4755, 3929), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4756, 3930), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4757, 3931), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4758, 3932), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4759, 3933), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4760, 3934), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4761, 3935), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4762, 3936), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4763, 3937), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4764, 3938), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4765, 3939), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4766, 3940), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4767, 3941), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4768, 3942), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4769, 3943), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4770, 3944), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4771, 3945), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4772, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingStorePage ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :424:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :462:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndCond(4741, 2751, 4773), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4639, 4728), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4775, 4924), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4776, 4101), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4777, 3918), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4778, 4914), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4779, 4915), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(5, 1372), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4780, 4926), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4781, 3922), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4782, 3923), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4783, 3924), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4784, 3925), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4785, 3926), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4786, 3927), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4787, 3928), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4788, 3929), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4789, 3930), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4790, 3931), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4791, 3932), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4792, 3933), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4793, 3934), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4794, 3935), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4795, 3936), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4796, 3937), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4797, 3938), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4798, 3939), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4799, 3940), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4800, 3941), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4801, 3942), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4802, 3943), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4803, 3944), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4804, 3945), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4805, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingStoreNode ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :402:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :463:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndCond(4774, 2753, 4806), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(54, 808), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(3637, 4927), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4808, 4727), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4809, 4728), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4810, 4027), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4, 810), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4811, 4928), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4812, 3918), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4813, 3919), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4814, 3920), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4, 1372), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4815, 4929), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4816, 3922), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4817, 3923), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4818, 3924), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4819, 3925), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4820, 3926), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4821, 3927), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4822, 3928), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4823, 3929), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4824, 3930), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4825, 3931), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4826, 3932), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4827, 3933), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4828, 3934), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4829, 3935), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4830, 3936), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4831, 3937), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4832, 3938), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4833, 3939), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4834, 3940), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4835, 3941), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4836, 3942), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4837, 3943), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4838, 3944), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4839, 3945), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4840, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonPagingStoreDone ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :438:17) at callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :464:29) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndCond(4807, 2760, 4841), // loc(callsite( PoseidonPaging ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :458:14) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :479:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(4842, 539), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4843, 615), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4844, 639), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4845, 666), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4846, 551), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4847, 564), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4848, 573), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4849, 578), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4850, 740), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4851, 745), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4852, 766), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4853, 770), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4854, 757), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4855, 764), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4856, 804), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4857, 826), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4858, 838), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4859, 844), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4860, 850), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4861, 856), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4862, 893), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4863, 899), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4864, 905), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4865, 911), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4866, 923), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4867, 929), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4868, 932), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4869, 935), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4870, 972), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4871, 975), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4872, 978), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4873, 984), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4874, 987), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4875, 990), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4876, 996), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4877, 999), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4878, 1002), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4879, 1008), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4880, 1011), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4881, 1014), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4882, 1051), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4883, 1054), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4884, 1057), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4885, 1063), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4886, 1066), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4887, 1069), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(4618, 395, 4888), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(4130, 629), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4930, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(632, 4931), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4416, 4932), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4890, 3995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4891, 2736, 4421), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(4892, 3994, 4424), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4893, 3953), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4894, 2294), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4895, 4784), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4896, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4897, 4040), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4898, 2228), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4899, 3960), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4900, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4901, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4902, 4785), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4131, 676), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4933, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4903, 2047), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(544, 4934), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4904, 4935), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4905, 4190), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4906, 2737, 4441), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(4907, 4189, 4444), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4908, 3964), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4909, 3965), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4910, 4793), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4911, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4912, 4044), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4913, 3971), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4914, 3972), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4915, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4916, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4917, 4794), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4132, 570), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4936, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4918, 2052), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(572, 4937), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4919, 4938), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4920, 4001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4921, 2744, 4461), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(4922, 4000, 4464), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4923, 3976), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4924, 3977), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4925, 4803), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4926, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4927, 4048), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4928, 3983), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4929, 3984), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4930, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4931, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4932, 4804), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4133, 588), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4939, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4933, 4807), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(739, 4940), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4934, 4941), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4935, 4003), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4936, 2745, 4481), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(4937, 4002, 4484), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4938, 1652), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4939, 1658), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4940, 4813), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4941, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4942, 4052), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4943, 3992), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4944, 3993), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4945, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4946, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4947, 4814), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4134, 747), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4942, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4948, 4817), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(760, 4943), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4949, 4944), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4950, 4009), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4951, 2750, 4501), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(4952, 4008, 4504), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4953, 4056), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4954, 754), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4955, 4824), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4956, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4957, 4058), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4958, 4060), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4959, 4061), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4960, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4961, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4962, 4825), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4135, 772), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4945, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4963, 4828), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(756, 4946), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4964, 4947), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4965, 4150), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4966, 2751, 4521), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(4967, 4149, 4524), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4968, 4065), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4969, 779), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4970, 4835), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4971, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4972, 4067), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4973, 4069), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4974, 4070), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4975, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4976, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4977, 4836), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4136, 800), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4948, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4978, 4839), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(802, 4949), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4979, 4950), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4980, 2755), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4981, 2753, 4541), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(4982, 2754, 4544), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4983, 4074), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4984, 3020), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4985, 4846), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4986, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4987, 4076), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4988, 4081), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4989, 4082), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4990, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4991, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4992, 4847), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :282:30) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4137, 832), // loc(callsite( builtin Sub at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4951, 49), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:36) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(4993, 4850), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(835, 4952), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4994, 4953), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :283:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4995, 4853), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :287:29) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(4996, 2760, 4561), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndCond(4997, 4852, 4564), // loc(callsite( FieldToWord ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :290:4) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :322:24) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(4998, 4086), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(4999, 4087), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5000, 4859), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5001, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5002, 4089), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5003, 4093), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5004, 4094), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5005, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5006, 0), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :323:23) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5007, 4095), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5008, 4096), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5009, 4097), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5010, 4098), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5011, 4099), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5012, 4100), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(13, 810), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5013, 4954), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5014, 3918), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5015, 3919), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5016, 3920), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5017, 4104), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5018, 4766), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5019, 4767), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5020, 4768), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5021, 4769), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5022, 4770), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5023, 4771), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5024, 4772), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5025, 4773), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5026, 4594), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5027, 4595), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5028, 4596), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5029, 4597), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5030, 4598), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5031, 4599), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5032, 4600), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5033, 4601), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5034, 4602), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5035, 4603), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5036, 4604), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5037, 4605), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5038, 4606), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5039, 4607), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5040, 4608), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5041, 4609), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5042, 3952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :327:17) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :480:24) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5043, 1075), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5044, 1081), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(4889, 398, 5045), // loc(callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(3628, 449, 5046), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(376, 68), // loc(callsite( builtin Add at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :487:45) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(371, 4955), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :487:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(591, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :486:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 4957), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :486:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5048, 3320), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :486:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5049, 4956), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :487:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(4113, 6), // loc(callsite( builtin Sub at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 610), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4958, 615), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4959, 609), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5051, 4960), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(608, 4958), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5052, 4961), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(608, 615), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5053, 4962), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :241:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(4113, 2), // loc(callsite( builtin Sub at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5054, 624), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4963, 629), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4964, 623), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5055, 4965), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(622, 4963), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5056, 4966), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(622, 629), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5057, 4967), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :242:22) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(4038, 1), // loc(callsite( builtin Sub at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :243:21) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5058, 634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4968, 639), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4969, 633), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5059, 4970), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(632, 4968), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5060, 4971), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(632, 639), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5061, 4972), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :244:23) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(4038, 622), // loc(callsite( builtin Sub at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :245:21) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(608, 73), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :247:6) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(609, 622), // loc(callsite( builtin Sub at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :248:11) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(4975, 68), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :248:30) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(4974, 4976), // loc(callsite( builtin Add at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :247:40) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(622, 633), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :249:6) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(4978, 60), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :249:31) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(4977, 4979), // loc(callsite( builtin Add at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :248:56) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(622, 632), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :250:6) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(4981, 61), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :250:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(4980, 4982), // loc(callsite( builtin Add at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :249:55) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(4113, 1), // loc(callsite( builtin Add at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :251:54) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(4975, 4984), // loc(callsite( builtin Mul at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :251:44) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 737), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(737, 4986), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(5062, 4987), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5063, 1735), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 798), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(798, 4988), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(5064, 4989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5065, 3022), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 802), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(802, 4990), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(5066, 4991), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5067, 3872), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5068, 816), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5069, 819), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(737, 764), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4992, 798), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4993, 800), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4994, 802), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4995, 804), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4996, 814), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4997, 817), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4998, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5070, 4999), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(798, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 3), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 2), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(764, 5000), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5006, 5001), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5007, 5002), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5008, 5003), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5009, 5004), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5010, 5005), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(5011, 4113), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5071, 5012), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :115:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(737, 74), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 75), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 76), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 77), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 78), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 79), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 80), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 81), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 82), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 83), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 84), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 85), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 86), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 87), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 88), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 89), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 90), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 91), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 92), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 93), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 94), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 95), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 96), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 97), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 121), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 120), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 119), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 118), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 117), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 116), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 115), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 114), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 113), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 112), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 111), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 110), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 109), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 108), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 107), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 106), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 105), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 104), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 103), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 102), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 101), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 100), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 99), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 98), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 145), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 144), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 143), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 142), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 141), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 140), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 139), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 138), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 137), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 136), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 135), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 134), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 133), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 132), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 131), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 130), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 129), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 128), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 127), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 126), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 125), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 124), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 123), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 122), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 169), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 168), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 167), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 166), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 165), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 164), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 163), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 162), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 161), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 160), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 159), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 158), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 157), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 156), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 155), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 154), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 153), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 152), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 151), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 150), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 149), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 148), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 147), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 146), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 193), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 192), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 191), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 190), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 189), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 188), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 187), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 186), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 185), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 184), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 183), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 182), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 181), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 180), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 179), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 178), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 177), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 176), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 175), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 174), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 173), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 172), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 171), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 170), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 217), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 216), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 215), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 214), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 213), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 212), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 211), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 210), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 209), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 208), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 207), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 206), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 205), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 204), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 203), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 202), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 201), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 200), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 199), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 198), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 197), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 196), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 195), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 194), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 241), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 240), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 239), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 238), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 237), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 236), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 235), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 234), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 233), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 232), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 231), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 230), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 229), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 228), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 227), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 226), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 225), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 224), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 223), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 222), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 221), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 220), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 219), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(814, 218), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 265), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 264), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 263), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 262), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 261), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 260), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 259), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 258), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 257), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 256), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 255), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 254), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 253), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 252), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 251), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 250), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 249), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 248), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 247), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 246), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 245), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 244), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 243), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(817, 242), // loc(callsite( builtin Mul at callsite( MultBy ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :111:16) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :119:12) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5013, 5037), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5014, 5038), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5015, 5039), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5016, 5040), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5017, 5041), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5018, 5042), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5019, 5043), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5020, 5044), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5021, 5045), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5022, 5046), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5023, 5047), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5024, 5048), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5025, 5049), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5026, 5050), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5027, 5051), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5028, 5052), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5029, 5053), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5030, 5054), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5031, 5055), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5032, 5056), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5033, 5057), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5034, 5058), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5035, 5059), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5036, 5060), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5205, 5061), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5206, 5062), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5207, 5063), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5208, 5064), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5209, 5065), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5210, 5066), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5211, 5067), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5212, 5068), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5213, 5069), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5214, 5070), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5215, 5071), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5216, 5072), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5217, 5073), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5218, 5074), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5219, 5075), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5220, 5076), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5221, 5077), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5222, 5078), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5223, 5079), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5224, 5080), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5225, 5081), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5226, 5082), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5227, 5083), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5228, 5084), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5229, 5085), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5230, 5086), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5231, 5087), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5232, 5088), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5233, 5089), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5234, 5090), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5235, 5091), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5236, 5092), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5237, 5093), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5238, 5094), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5239, 5095), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5240, 5096), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5241, 5097), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5242, 5098), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5243, 5099), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5244, 5100), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5245, 5101), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5246, 5102), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5247, 5103), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5248, 5104), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5249, 5105), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5250, 5106), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5251, 5107), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5252, 5108), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5253, 5109), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5254, 5110), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5255, 5111), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5256, 5112), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5257, 5113), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5258, 5114), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5259, 5115), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5260, 5116), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5261, 5117), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5262, 5118), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5263, 5119), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5264, 5120), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5265, 5121), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5266, 5122), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5267, 5123), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5268, 5124), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5269, 5125), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5270, 5126), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5271, 5127), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5272, 5128), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5273, 5129), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5274, 5130), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5275, 5131), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5276, 5132), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5277, 5133), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5278, 5134), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5279, 5135), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5280, 5136), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5281, 5137), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5282, 5138), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5283, 5139), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5284, 5140), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5285, 5141), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5286, 5142), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5287, 5143), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5288, 5144), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5289, 5145), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5290, 5146), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5291, 5147), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5292, 5148), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5293, 5149), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5294, 5150), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5295, 5151), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5296, 5152), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5297, 5153), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5298, 5154), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5299, 5155), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5300, 5156), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5301, 5157), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5302, 5158), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5303, 5159), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5304, 5160), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5305, 5161), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5306, 5162), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5307, 5163), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5308, 5164), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5309, 5165), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5310, 5166), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5311, 5167), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5312, 5168), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5313, 5169), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5314, 5170), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5315, 5171), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5316, 5172), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5317, 5173), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5318, 5174), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5319, 5175), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5320, 5176), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5321, 5177), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5322, 5178), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5323, 5179), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5324, 5180), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5325, 5181), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5326, 5182), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5327, 5183), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5328, 5184), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5329, 5185), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5330, 5186), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5331, 5187), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5332, 5188), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5333, 5189), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5334, 5190), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5335, 5191), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5336, 5192), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5337, 5193), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5338, 5194), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5339, 5195), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5340, 5196), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5341, 5197), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5342, 5198), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5343, 5199), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5344, 5200), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5345, 5201), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5346, 5202), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5347, 5203), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(5348, 5204), // loc(callsite( builtin Add at callsite( AddConsts ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :107:23) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :118:19) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4114, 5349), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5373, 5373), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5374, 5373), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5375, 649), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5072, 5376), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(649, 649), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5377, 5373), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5378, 646), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5073, 5379), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4115, 5350), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5380, 5380), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5381, 5380), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5382, 659), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5074, 5383), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(659, 659), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5384, 5380), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5385, 652), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5075, 5386), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4116, 5351), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5387, 5387), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5388, 5387), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5389, 673), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5076, 5390), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(673, 673), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5391, 5387), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5392, 666), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5077, 5393), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4117, 5352), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5394, 5394), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5395, 5394), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5396, 544), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5078, 5397), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(544, 544), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5398, 5394), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5399, 676), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5079, 5400), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4118, 5353), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5401, 5401), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5402, 5401), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5403, 552), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5080, 5404), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(552, 552), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5405, 5401), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5406, 551), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5081, 5407), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4119, 5354), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5408, 5408), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5409, 5408), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5410, 556), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5082, 5411), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(556, 556), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5412, 5408), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5413, 555), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5083, 5414), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4120, 5355), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5415, 5415), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5416, 5415), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5417, 564), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5084, 5418), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(564, 564), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5419, 5415), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5420, 563), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5085, 5421), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4121, 5356), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5422, 5422), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5423, 5422), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5424, 570), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5086, 5425), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(570, 570), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5426, 5422), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5427, 571), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5087, 5428), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4122, 5357), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5429, 5429), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5430, 5429), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5431, 573), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5088, 5432), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(573, 573), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5433, 5429), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5434, 572), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5089, 5435), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4123, 5358), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5436, 5436), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5437, 5436), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5438, 575), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5090, 5439), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(575, 575), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5440, 5436), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5441, 574), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5091, 5442), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4124, 5359), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5443, 5443), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5444, 5443), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5445, 577), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5092, 5446), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(577, 577), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5447, 5443), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5448, 576), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5093, 5449), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4125, 5360), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5450, 5450), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5451, 5450), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5452, 587), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5094, 5453), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(587, 587), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5454, 5450), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5455, 578), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5095, 5456), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4126, 5361), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5457, 5457), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5458, 5457), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5459, 739), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5096, 5460), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(739, 739), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5461, 5457), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5462, 588), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5097, 5463), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4127, 5362), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5464, 5464), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5465, 5464), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5466, 741), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5098, 5467), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(741, 741), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5468, 5464), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5469, 740), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5099, 5470), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4128, 5363), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5471, 5471), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5472, 5471), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5473, 743), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5100, 5474), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(743, 743), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5475, 5471), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5476, 742), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5101, 5477), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4129, 5364), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5478, 5478), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5479, 5478), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5480, 745), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5102, 5481), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(745, 745), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5482, 5478), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5483, 744), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5103, 5484), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4130, 5365), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5485, 5485), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5486, 5485), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5487, 747), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5104, 5488), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(747, 747), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5489, 5485), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5490, 746), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5105, 5491), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4131, 5366), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5492, 5492), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5493, 5492), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5494, 766), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5106, 5495), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(766, 766), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5496, 5492), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5497, 760), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5107, 5498), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4132, 5367), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5499, 5499), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5500, 5499), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5501, 768), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5108, 5502), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(768, 768), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5503, 5499), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5504, 767), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5109, 5505), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4133, 5368), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5506, 5506), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5507, 5506), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5508, 761), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5110, 5509), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(761, 761), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5510, 5506), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5511, 769), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5111, 5512), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4134, 5369), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5513, 5513), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5514, 5513), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5515, 771), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5112, 5516), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(771, 771), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5517, 5513), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5518, 770), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5113, 5519), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4135, 5370), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5520, 5520), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5521, 5520), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5522, 756), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5114, 5523), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(756, 756), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5524, 5520), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5525, 772), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5115, 5526), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4136, 5371), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5527, 5527), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5528, 5527), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5529, 762), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5116, 5530), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(762, 762), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5531, 5527), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5532, 757), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5117, 5533), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4137, 5372), // loc(callsite( builtin Add at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:44) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5534, 5534), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5535, 5534), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5536, 732), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5118, 5537), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(732, 732), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5538, 5534), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5539, 781), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5119, 5540), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:39) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(646, 652), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(666, 676), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(652, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5543, 5542), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(1723, 5541), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(5542, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5546, 5545), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(5541, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5548, 5544), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5545, 5549), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5544, 5547), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(551, 555), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(563, 571), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(555, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5554, 5553), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(571, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5556, 5552), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(5553, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5558, 5557), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(5552, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5560, 5555), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5557, 5561), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5555, 5559), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(572, 574), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(576, 578), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(2193, 5565), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(578, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5567, 5564), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(5565, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5569, 5568), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(5564, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5571, 5566), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5568, 5572), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5566, 5570), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(588, 740), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(742, 744), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(2197, 5576), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(744, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5578, 5575), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(5576, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5580, 5579), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(5575, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5582, 5577), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5579, 5583), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5577, 5581), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(746, 760), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(767, 769), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(760, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5588, 5587), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(769, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5590, 5586), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(5587, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5592, 5591), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(5586, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5594, 5589), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5591, 5595), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5589, 5593), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(770, 772), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :42:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(757, 781), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :43:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(772, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5600, 5599), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :44:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(781, 7), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5602, 5598), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :45:19) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(5599, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5604, 5603), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :46:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(5598, 5), // loc(callsite( builtin Mul at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5606, 5601), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :47:15) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5603, 5607), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :48:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5601, 5605), // loc(callsite( builtin Add at callsite( MultiplyByCirculant ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :49:11) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :61:25) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5550, 5562), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5549, 5561), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5551, 5563), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5547, 5559), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5610, 5573), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5611, 5572), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5612, 5574), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5613, 5570), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5614, 5584), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5615, 5583), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5616, 5585), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5617, 5581), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5618, 5596), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5619, 5595), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5620, 5597), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5621, 5593), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5622, 5608), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5623, 5607), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5624, 5609), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5625, 5605), // loc(callsite( builtin Add at callsite( ReduceVec4 ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :54:22) at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :64:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Add(5550, 5626), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5549, 5627), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5551, 5628), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5547, 5629), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5562, 5626), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5561, 5627), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5563, 5628), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5559, 5629), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5573, 5626), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5572, 5627), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5574, 5628), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5570, 5629), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5584, 5626), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5583, 5627), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5585, 5628), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5581, 5629), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5596, 5626), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5595, 5627), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5597, 5628), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5593, 5629), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5608, 5626), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5607, 5627), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5609, 5628), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5605, 5629), // loc(callsite( builtin Add at callsite( MultiplyByMExt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :69:18) at callsite( DoExtRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :103:18) at callsite( DoExtRoundByIdx ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :122:14) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :252:32) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5120, 4095), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5121, 4096), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5122, 4097), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5123, 4098), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5124, 4099), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5125, 4100), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4983, 810), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5126, 5654), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4985, 1154), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5127, 5655), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5128, 4102), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4973, 1160), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5129, 5656), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5130, 4104), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5630, 1373), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5131, 5657), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5631, 1375), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5132, 5658), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5632, 1382), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5133, 5659), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5633, 1383), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5134, 5660), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5634, 1385), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5135, 5661), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5635, 1391), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5136, 5662), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5636, 1392), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5137, 5663), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5637, 1394), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5138, 5664), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5638, 1401), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5139, 5665), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5639, 1402), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5140, 5666), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5640, 1404), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5141, 5667), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5641, 1410), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5142, 5668), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5642, 1411), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5143, 5669), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5643, 1424), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5144, 5670), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5644, 1427), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5145, 5671), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5645, 1426), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5146, 5672), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5646, 1428), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5147, 5673), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5647, 1829), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5148, 5674), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5648, 1830), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5149, 5675), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5649, 1429), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5150, 5676), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5650, 1430), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5151, 5677), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5651, 1431), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5152, 5678), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5652, 1432), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5153, 5679), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5653, 1439), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5154, 5680), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(3951, 4147), // loc(callsite( builtin ExtSub at callsite( ExtReg ( :13:18) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5155, 5681), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonExtRound ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :253:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :490:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(5050, 377, 5156), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(4114, 266), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5682, 5682), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5683, 5682), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5684, 615), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(0, 5685), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(615, 615), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5686, 5682), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5687, 608), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5158, 5688), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(608, 4115), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5689, 4116), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5690, 4117), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5691, 4118), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5692, 4119), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5693, 4120), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5694, 4121), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5695, 4122), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5696, 4123), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5697, 4124), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5698, 4125), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5699, 4126), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5700, 4127), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5701, 4128), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5702, 4129), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5703, 4130), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5704, 4131), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5705, 4132), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5706, 4133), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5707, 4134), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5708, 4135), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5709, 4136), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5710, 4137), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(608, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5712), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4115, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5714), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4116, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5716), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4117, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5718), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4118, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5720), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4119, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5722), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4120, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5724), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4121, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5726), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4122, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5728), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4123, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5730), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4124, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5732), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4125, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5734), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4126, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5736), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4127, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5738), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4128, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5740), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4129, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5742), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4130, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5744), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4131, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5746), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4132, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5748), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4133, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5750), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4134, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5752), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4135, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5754), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4136, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5756), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4137, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5711, 5758), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5713, 267), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5760, 5760), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5761, 5760), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5762, 629), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5159, 5763), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(629, 629), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5764, 5760), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5765, 622), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5160, 5766), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(622, 5715), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5767, 5717), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5768, 5719), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5769, 5721), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5770, 5723), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5771, 5725), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5772, 5727), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5773, 5729), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5774, 5731), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5775, 5733), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5776, 5735), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5777, 5737), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5778, 5739), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5779, 5741), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5780, 5743), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5781, 5745), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5782, 5747), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5783, 5749), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5784, 5751), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5785, 5753), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5786, 5755), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5787, 5757), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5788, 5759), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(622, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5790), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5715, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5792), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5717, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5794), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5719, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5796), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5721, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5798), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5723, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5800), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5725, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5802), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5727, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5804), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5729, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5806), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5731, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5808), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5733, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5810), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5735, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5812), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5737, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5814), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5739, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5816), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5741, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5818), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5743, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5820), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5745, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5822), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5747, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5824), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5749, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5826), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5751, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5828), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5753, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5830), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5755, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5832), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5757, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5834), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5759, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5789, 5836), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5791, 268), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5838, 5838), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5839, 5838), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5840, 639), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5161, 5841), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(639, 639), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:15) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5842, 5838), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5843, 632), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5162, 5844), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(632, 5793), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5845, 5795), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5846, 5797), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5847, 5799), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5848, 5801), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5849, 5803), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5850, 5805), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5851, 5807), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5852, 5809), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5853, 5811), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5854, 5813), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5855, 5815), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5856, 5817), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5857, 5819), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5858, 5821), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5859, 5823), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5860, 5825), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5861, 5827), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5862, 5829), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5863, 5831), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5864, 5833), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5865, 5835), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5866, 5837), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(632, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5868), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5793, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5870), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5795, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5872), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5797, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5874), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5799, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5876), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5801, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5878), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5803, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5880), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5805, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5882), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5807, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5884), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5809, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5886), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5811, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5888), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5813, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5890), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5815, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5892), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5817, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5894), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5819, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5896), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5821, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5898), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5823, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5900), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5825, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5902), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5827, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5904), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5829, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5906), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5831, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5908), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5833, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5910), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5835, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5912), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5837, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5867, 5914), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5869, 269), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5916, 5916), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5917, 5916), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5918, 649), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5163, 5919), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5377, 5916), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5920, 646), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5164, 5921), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(646, 5871), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5922, 5873), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5923, 5875), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5924, 5877), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5925, 5879), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5926, 5881), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5927, 5883), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5928, 5885), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5929, 5887), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5930, 5889), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5931, 5891), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5932, 5893), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5933, 5895), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5934, 5897), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5935, 5899), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5936, 5901), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5937, 5903), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5938, 5905), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5939, 5907), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5940, 5909), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5941, 5911), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5942, 5913), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5943, 5915), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(646, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5945), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5871, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5947), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5873, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5949), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5875, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5951), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5877, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5953), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5879, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5955), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5881, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5957), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5883, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5959), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5885, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5961), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5887, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5963), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5889, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5965), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5891, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5967), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5893, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5969), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5895, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5971), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5897, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5973), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5899, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5975), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5901, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5977), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5903, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5979), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5905, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5981), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5907, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5983), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5909, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5985), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5911, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5987), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5913, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5989), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5915, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5944, 5991), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5946, 270), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(5993, 5993), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5994, 5993), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5995, 659), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5165, 5996), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5384, 5993), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(5997, 652), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5166, 5998), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(652, 5948), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(5999, 5950), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6000, 5952), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6001, 5954), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6002, 5956), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6003, 5958), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6004, 5960), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6005, 5962), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6006, 5964), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6007, 5966), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6008, 5968), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6009, 5970), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6010, 5972), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6011, 5974), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6012, 5976), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6013, 5978), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6014, 5980), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6015, 5982), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6016, 5984), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6017, 5986), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6018, 5988), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6019, 5990), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6020, 5992), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(652, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6022), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5948, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6024), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5950, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6026), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5952, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6028), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5954, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6030), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5956, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6032), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5958, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6034), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5960, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6036), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5962, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6038), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5964, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6040), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5966, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6042), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5968, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6044), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5970, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6046), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5972, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6048), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5974, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6050), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5976, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6052), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5978, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6054), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5980, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6056), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5982, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6058), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5984, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6060), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5986, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6062), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5988, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6064), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5990, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6066), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5992, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6021, 6068), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6023, 271), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(6070, 6070), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6071, 6070), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6072, 673), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5167, 6073), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5391, 6070), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6074, 666), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5168, 6075), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(666, 6025), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6076, 6027), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6077, 6029), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6078, 6031), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6079, 6033), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6080, 6035), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6081, 6037), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6082, 6039), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6083, 6041), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6084, 6043), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6085, 6045), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6086, 6047), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6087, 6049), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6088, 6051), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6089, 6053), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6090, 6055), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6091, 6057), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6092, 6059), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6093, 6061), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6094, 6063), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6095, 6065), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6096, 6067), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6097, 6069), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(666, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6099), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6025, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6101), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6027, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6103), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6029, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6105), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6031, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6107), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6033, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6109), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6035, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6111), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6037, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6113), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6039, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6115), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6041, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6117), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6043, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6119), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6045, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6121), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6047, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6123), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6049, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6125), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6051, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6127), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6053, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6129), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6055, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6131), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6057, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6133), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6059, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6135), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6061, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6137), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6063, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6139), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6065, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6141), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6067, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6143), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6069, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6098, 6145), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6100, 272), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(6147, 6147), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6148, 6147), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6149, 544), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5169, 6150), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5398, 6147), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6151, 676), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5170, 6152), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(676, 6102), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6153, 6104), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6154, 6106), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6155, 6108), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6156, 6110), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6157, 6112), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6158, 6114), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6159, 6116), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6160, 6118), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6161, 6120), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6162, 6122), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6163, 6124), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6164, 6126), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6165, 6128), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6166, 6130), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6167, 6132), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6168, 6134), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6169, 6136), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6170, 6138), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6171, 6140), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6172, 6142), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6173, 6144), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6174, 6146), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(676, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6176), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6102, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6178), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6104, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6180), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6106, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6182), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6108, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6184), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6110, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6186), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6112, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6188), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6114, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6190), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6116, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6192), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6118, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6194), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6120, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6196), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6122, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6198), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6124, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6200), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6126, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6202), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6128, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6204), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6130, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6206), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6132, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6208), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6134, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6210), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6136, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6212), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6138, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6214), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6140, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6216), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6142, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6218), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6144, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6220), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6146, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6175, 6222), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6177, 273), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(6224, 6224), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6225, 6224), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6226, 552), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5171, 6227), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5405, 6224), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6228, 551), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5172, 6229), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(551, 6179), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6230, 6181), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6231, 6183), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6232, 6185), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6233, 6187), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6234, 6189), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6235, 6191), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6236, 6193), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6237, 6195), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6238, 6197), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6239, 6199), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6240, 6201), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6241, 6203), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6242, 6205), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6243, 6207), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6244, 6209), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6245, 6211), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6246, 6213), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6247, 6215), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6248, 6217), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6249, 6219), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6250, 6221), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6251, 6223), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(551, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6253), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6179, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6255), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6181, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6257), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6183, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6259), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6185, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6261), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6187, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6263), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6189, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6265), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6191, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6267), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6193, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6269), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6195, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6271), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6197, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6273), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6199, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6275), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6201, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6277), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6203, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6279), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6205, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6281), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6207, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6283), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6209, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6285), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6211, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6287), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6213, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6289), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6215, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6291), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6217, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6293), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6219, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6295), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6221, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6297), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6223, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6252, 6299), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6254, 274), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(6301, 6301), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6302, 6301), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6303, 556), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5173, 6304), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5412, 6301), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6305, 555), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5174, 6306), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(555, 6256), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6307, 6258), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6308, 6260), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6309, 6262), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6310, 6264), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6311, 6266), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6312, 6268), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6313, 6270), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6314, 6272), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6315, 6274), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6316, 6276), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6317, 6278), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6318, 6280), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6319, 6282), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6320, 6284), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6321, 6286), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6322, 6288), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6323, 6290), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6324, 6292), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6325, 6294), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6326, 6296), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6327, 6298), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6328, 6300), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(555, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6330), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6256, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6332), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6258, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6334), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6260, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6336), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6262, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6338), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6264, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6340), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6266, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6342), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6268, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6344), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6270, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6346), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6272, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6348), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6274, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6350), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6276, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6352), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6278, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6354), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6280, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6356), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6282, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6358), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6284, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6360), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6286, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6362), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6288, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6364), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6290, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6366), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6292, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6368), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6294, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6370), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6296, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6372), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6298, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6374), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6300, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6329, 6376), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6331, 275), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(6378, 6378), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6379, 6378), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6380, 564), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5175, 6381), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5419, 6378), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6382, 563), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5176, 6383), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(563, 6333), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6384, 6335), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6385, 6337), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6386, 6339), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6387, 6341), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6388, 6343), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6389, 6345), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6390, 6347), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6391, 6349), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6392, 6351), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6393, 6353), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6394, 6355), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6395, 6357), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6396, 6359), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6397, 6361), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6398, 6363), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6399, 6365), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6400, 6367), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6401, 6369), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6402, 6371), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6403, 6373), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6404, 6375), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6405, 6377), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(563, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6407), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6333, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6409), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6335, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6411), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6337, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6413), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6339, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6415), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6341, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6417), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6343, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6419), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6345, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6421), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6347, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6423), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6349, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6425), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6351, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6427), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6353, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6429), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6355, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6431), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6357, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6433), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6359, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6435), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6361, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6437), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6363, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6439), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6365, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6441), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6367, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6443), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6369, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6445), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6371, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6447), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6373, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6449), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6375, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6451), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6377, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6406, 6453), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6408, 276), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(6455, 6455), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6456, 6455), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6457, 570), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5177, 6458), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5426, 6455), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6459, 571), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5178, 6460), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(571, 6410), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6461, 6412), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6462, 6414), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6463, 6416), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6464, 6418), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6465, 6420), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6466, 6422), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6467, 6424), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6468, 6426), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6469, 6428), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6470, 6430), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6471, 6432), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6472, 6434), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6473, 6436), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6474, 6438), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6475, 6440), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6476, 6442), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6477, 6444), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6478, 6446), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6479, 6448), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6480, 6450), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6481, 6452), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6482, 6454), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(571, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6484), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6410, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6486), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6412, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6488), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6414, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6490), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6416, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6492), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6418, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6494), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6420, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6496), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6422, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6498), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6424, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6500), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6426, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6502), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6428, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6504), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6430, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6506), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6432, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6508), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6434, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6510), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6436, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6512), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6438, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6514), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6440, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6516), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6442, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6518), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6444, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6520), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6446, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6522), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6448, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6524), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6450, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6526), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6452, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6528), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6454, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6483, 6530), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6485, 277), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(6532, 6532), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6533, 6532), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6534, 573), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5179, 6535), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5433, 6532), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6536, 572), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5180, 6537), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(572, 6487), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6538, 6489), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6539, 6491), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6540, 6493), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6541, 6495), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6542, 6497), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6543, 6499), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6544, 6501), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6545, 6503), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6546, 6505), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6547, 6507), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6548, 6509), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6549, 6511), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6550, 6513), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6551, 6515), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6552, 6517), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6553, 6519), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6554, 6521), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6555, 6523), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6556, 6525), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6557, 6527), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6558, 6529), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6559, 6531), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(572, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6561), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6487, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6563), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6489, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6565), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6491, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6567), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6493, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6569), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6495, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6571), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6497, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6573), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6499, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6575), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6501, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6577), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6503, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6579), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6505, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6581), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6507, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6583), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6509, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6585), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6511, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6587), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6513, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6589), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6515, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6591), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6517, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6593), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6519, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6595), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6521, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6597), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6523, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6599), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6525, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6601), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6527, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6603), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6529, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6605), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6531, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6560, 6607), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6562, 278), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(6609, 6609), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6610, 6609), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6611, 575), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5181, 6612), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5440, 6609), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6613, 574), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5182, 6614), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(574, 6564), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6615, 6566), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6616, 6568), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6617, 6570), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6618, 6572), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6619, 6574), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6620, 6576), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6621, 6578), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6622, 6580), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6623, 6582), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6624, 6584), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6625, 6586), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6626, 6588), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6627, 6590), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6628, 6592), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6629, 6594), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6630, 6596), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6631, 6598), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6632, 6600), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6633, 6602), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6634, 6604), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6635, 6606), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6636, 6608), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(574, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6638), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6564, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6640), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6566, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6642), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6568, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6644), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6570, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6646), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6572, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6648), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6574, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6650), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6576, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6652), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6578, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6654), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6580, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6656), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6582, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6658), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6584, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6660), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6586, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6662), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6588, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6664), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6590, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6666), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6592, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6668), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6594, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6670), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6596, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6672), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6598, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6674), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6600, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6676), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6602, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6678), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6604, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6680), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6606, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6682), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6608, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6637, 6684), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6639, 279), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(6686, 6686), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6687, 6686), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6688, 577), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5183, 6689), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5447, 6686), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6690, 576), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5184, 6691), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(576, 6641), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6692, 6643), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6693, 6645), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6694, 6647), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6695, 6649), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6696, 6651), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6697, 6653), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6698, 6655), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6699, 6657), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6700, 6659), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6701, 6661), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6702, 6663), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6703, 6665), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6704, 6667), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6705, 6669), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6706, 6671), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6707, 6673), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6708, 6675), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6709, 6677), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6710, 6679), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6711, 6681), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6712, 6683), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6713, 6685), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(576, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6715), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6641, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6717), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6643, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6719), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6645, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6721), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6647, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6723), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6649, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6725), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6651, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6727), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6653, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6729), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6655, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6731), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6657, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6733), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6659, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6735), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6661, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6737), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6663, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6739), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6665, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6741), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6667, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6743), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6669, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6745), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6671, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6747), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6673, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6749), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6675, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6751), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6677, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6753), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6679, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6755), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6681, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6757), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6683, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6759), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6685, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6714, 6761), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6716, 280), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(6763, 6763), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6764, 6763), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6765, 587), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5185, 6766), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5454, 6763), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6767, 578), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5186, 6768), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(578, 6718), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6769, 6720), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6770, 6722), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6771, 6724), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6772, 6726), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6773, 6728), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6774, 6730), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6775, 6732), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6776, 6734), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6777, 6736), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6778, 6738), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6779, 6740), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6780, 6742), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6781, 6744), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6782, 6746), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6783, 6748), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6784, 6750), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6785, 6752), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6786, 6754), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6787, 6756), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6788, 6758), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6789, 6760), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6790, 6762), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(578, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6792), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6718, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6794), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6720, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6796), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6722, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6798), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6724, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6800), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6726, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6802), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6728, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6804), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6730, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6806), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6732, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6808), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6734, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6810), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6736, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6812), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6738, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6814), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6740, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6816), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6742, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6818), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6744, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6820), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6746, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6822), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6748, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6824), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6750, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6826), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6752, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6828), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6754, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6830), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6756, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6832), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6758, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6834), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6760, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6836), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6762, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6791, 6838), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6793, 281), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(6840, 6840), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6841, 6840), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6842, 739), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5187, 6843), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5461, 6840), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6844, 588), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5188, 6845), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(588, 6795), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6846, 6797), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6847, 6799), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6848, 6801), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6849, 6803), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6850, 6805), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6851, 6807), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6852, 6809), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6853, 6811), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6854, 6813), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6855, 6815), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6856, 6817), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6857, 6819), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6858, 6821), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6859, 6823), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6860, 6825), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6861, 6827), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6862, 6829), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6863, 6831), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6864, 6833), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6865, 6835), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6866, 6837), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6867, 6839), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(588, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6869), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6795, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6871), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6797, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6873), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6799, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6875), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6801, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6877), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6803, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6879), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6805, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6881), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6807, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6883), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6809, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6885), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6811, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6887), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6813, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6889), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6815, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6891), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6817, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6893), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6819, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6895), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6821, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6897), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6823, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6899), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6825, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6901), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6827, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6903), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6829, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6905), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6831, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6907), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6833, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6909), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6835, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6911), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6837, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6913), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6839, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6868, 6915), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6870, 282), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(6917, 6917), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6918, 6917), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6919, 741), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5189, 6920), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5468, 6917), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6921, 740), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5190, 6922), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(740, 6872), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6923, 6874), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6924, 6876), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6925, 6878), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6926, 6880), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6927, 6882), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6928, 6884), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6929, 6886), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6930, 6888), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6931, 6890), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6932, 6892), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6933, 6894), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6934, 6896), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6935, 6898), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6936, 6900), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6937, 6902), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6938, 6904), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6939, 6906), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6940, 6908), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6941, 6910), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6942, 6912), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6943, 6914), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6944, 6916), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(740, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6946), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6872, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6948), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6874, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6950), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6876, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6952), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6878, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6954), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6880, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6956), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6882, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6958), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6884, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6960), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6886, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6962), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6888, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6964), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6890, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6966), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6892, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6968), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6894, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6970), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6896, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6972), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6898, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6974), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6900, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6976), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6902, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6978), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6904, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6980), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6906, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6982), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6908, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6984), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6910, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6986), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6912, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6988), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6914, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6990), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6916, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6945, 6992), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(6947, 283), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(6994, 6994), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6995, 6994), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6996, 743), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5191, 6997), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5475, 6994), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(6998, 742), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5192, 6999), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(742, 6949), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7000, 6951), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7001, 6953), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7002, 6955), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7003, 6957), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7004, 6959), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7005, 6961), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7006, 6963), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7007, 6965), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7008, 6967), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7009, 6969), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7010, 6971), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7011, 6973), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7012, 6975), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7013, 6977), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7014, 6979), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7015, 6981), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7016, 6983), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7017, 6985), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7018, 6987), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7019, 6989), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7020, 6991), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7021, 6993), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(742, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7023), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6949, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7025), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6951, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7027), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6953, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7029), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6955, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7031), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6957, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7033), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6959, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7035), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6961, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7037), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6963, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7039), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6965, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7041), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6967, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7043), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6969, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7045), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6971, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7047), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6973, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7049), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6975, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7051), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6977, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7053), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6979, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7055), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6981, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7057), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6983, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7059), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6985, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7061), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6987, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7063), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6989, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7065), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6991, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7067), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(6993, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7022, 7069), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7024, 284), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7071, 7071), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7072, 7071), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7073, 745), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5193, 7074), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5482, 7071), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7075, 744), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5194, 7076), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(744, 7026), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7077, 7028), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7078, 7030), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7079, 7032), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7080, 7034), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7081, 7036), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7082, 7038), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7083, 7040), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7084, 7042), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7085, 7044), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7086, 7046), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7087, 7048), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7088, 7050), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7089, 7052), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7090, 7054), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7091, 7056), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7092, 7058), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7093, 7060), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7094, 7062), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7095, 7064), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7096, 7066), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7097, 7068), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7098, 7070), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(744, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7100), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7026, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7102), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7028, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7104), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7030, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7106), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7032, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7108), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7034, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7110), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7036, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7112), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7038, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7114), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7040, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7116), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7042, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7118), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7044, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7120), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7046, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7122), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7048, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7124), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7050, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7126), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7052, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7128), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7054, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7130), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7056, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7132), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7058, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7134), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7060, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7136), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7062, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7138), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7064, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7140), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7066, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7142), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7068, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7144), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7070, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7099, 7146), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7101, 285), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7148, 7148), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7149, 7148), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7150, 747), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5195, 7151), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5489, 7148), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7152, 746), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5196, 7153), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(746, 7103), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7154, 7105), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7155, 7107), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7156, 7109), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7157, 7111), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7158, 7113), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7159, 7115), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7160, 7117), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7161, 7119), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7162, 7121), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7163, 7123), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7164, 7125), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7165, 7127), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7166, 7129), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7167, 7131), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7168, 7133), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7169, 7135), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7170, 7137), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7171, 7139), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7172, 7141), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7173, 7143), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7174, 7145), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7175, 7147), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(746, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7177), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7103, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7179), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7105, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7181), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7107, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7183), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7109, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7185), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7111, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7187), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7113, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7189), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7115, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7191), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7117, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7193), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7119, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7195), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7121, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7197), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7123, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7199), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7125, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7201), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7127, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7203), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7129, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7205), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7131, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7207), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7133, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7209), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7135, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7211), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7137, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7213), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7139, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7215), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7141, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7217), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7143, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7219), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7145, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7221), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7147, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7176, 7223), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7178, 286), // loc(callsite( builtin Add at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :31:13) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7225, 7225), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:17) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7226, 7225), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:22) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7227, 766), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5197, 7228), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :25:16) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(5496, 7225), // loc(callsite( builtin Mul at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:23) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7229, 760), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5198, 7230), // loc(callsite( Reg ( :6:7) at callsite( SBox ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :26:14) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :32:16) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(760, 7180), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7231, 7182), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7232, 7184), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7233, 7186), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7234, 7188), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7235, 7190), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7236, 7192), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7237, 7194), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7238, 7196), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7239, 7198), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7240, 7200), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7241, 7202), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7242, 7204), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7243, 7206), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7244, 7208), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7245, 7210), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7246, 7212), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7247, 7214), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7248, 7216), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7249, 7218), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7250, 7220), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7251, 7222), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7252, 7224), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :13:11) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(760, 287), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7254), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7180, 288), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7256), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7182, 289), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7258), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7184, 290), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7260), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7186, 291), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7262), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7188, 292), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7264), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7190, 293), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7266), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7192, 294), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7268), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7194, 295), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7270), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7196, 296), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7272), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7198, 297), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7274), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7200, 298), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7276), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7202, 299), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7278), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7204, 300), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7280), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7206, 301), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7282), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7208, 302), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7284), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7210, 303), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7286), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7212, 304), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7288), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7214, 305), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7290), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7216, 306), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7292), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7218, 307), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7294), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7220, 308), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7296), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7222, 309), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7298), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7224, 310), // loc(callsite( builtin Mul at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:44) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7253, 7300), // loc(callsite( builtin Add at callsite( MultiplyByMInt ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :14:20) at callsite( DoIntRound ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :34:18) at callsite( DoIntRounds ( zirgen/circuit/rv32im/v2/dsl/poseidon2.zir :38:4) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :257:28) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5199, 4095), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :34:26) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5200, 4096), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :35:27) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5201, 4097), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :36:28) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5202, 4098), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :37:24) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5203, 4099), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :38:26) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5204, 4100), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :39:28) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5205, 4542), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(5, 1154), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5206, 7302), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :42:26) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5207, 4102), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :43:27) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5208, 4103), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :44:23) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5209, 4104), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7255, 1373), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5210, 7303), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7257, 1375), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5211, 7304), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7259, 1382), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5212, 7305), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7261, 1383), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5213, 7306), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7263, 1385), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5214, 7307), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7265, 1391), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5215, 7308), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7267, 1392), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5216, 7309), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7269, 1394), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5217, 7310), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7271, 1401), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5218, 7311), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7273, 1402), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5219, 7312), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7275, 1404), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5220, 7313), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7277, 1410), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5221, 7314), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7279, 1411), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5222, 7315), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7281, 1424), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5223, 7316), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7283, 1427), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5224, 7317), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7285, 1426), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5225, 7318), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7287, 1428), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5226, 7319), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7289, 1829), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5227, 7320), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7291, 1830), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5228, 7321), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7293, 1429), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5229, 7322), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7295, 1430), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5230, 7323), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7297, 1431), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5231, 7324), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7299, 1432), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5232, 7325), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7301, 1439), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5233, 7326), // loc(callsite( Reg ( :6:7) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :47:39) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5234, 5681), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :48:27) at callsite( PoseidonIntRounds ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :258:17) at callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :491:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(5157, 380, 5235), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(5236, 383, 4221), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(5237, 386, 4221), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(5238, 389, 4221), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(5239, 392, 4221), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(5240, 395, 4221), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(5241, 398, 4221), // loc(callsite( Poseidon1 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :489:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :84:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(5047, 452, 5242), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(376, 24), // loc(callsite( builtin Add at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :226:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(371, 7327), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :226:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1075, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :225:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 7329), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :225:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(1081, 542), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :225:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5244, 7330), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :225:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5245, 7328), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :226:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(814, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(0, 7331), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5247, 3893), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(832, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5248, 7332), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5249, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(817, 62), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5250, 7333), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5251, 4091), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(826, 838), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5252, 7334), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3146, 820), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5253, 4828), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1014, 7335), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5254, 7336), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(838, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(835, 63), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7337, 7338), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :46:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(841, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5255, 7340), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5256, 3992), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(859, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5257, 7341), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5258, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(844, 64), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5259, 7342), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(850, 893), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5260, 7343), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(853, 896), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5261, 7344), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(859, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7345, 847), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1017, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5262, 7347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1051, 7346), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5263, 7348), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(896, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(893, 63), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7349, 7350), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :47:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(899, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5264, 7352), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(914, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5265, 7353), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(917, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5266, 7354), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5267, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(902, 65), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5268, 7355), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(908, 920), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5269, 7356), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(911, 923), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5270, 7357), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4774, 905), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5271, 4839), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1057, 7358), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5272, 7359), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(923, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(920, 63), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7360, 7361), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :48:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(926, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5273, 7363), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5274, 4794), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(975, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5275, 7364), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5276, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(929, 66), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5277, 7365), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(935, 978), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5278, 7366), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(938, 981), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5279, 7367), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(2052, 932), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1060, 1), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5280, 7369), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1063, 7368), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5281, 7370), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :50:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(984, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5282, 7371), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5283, 4817), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1002, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5284, 7372), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5285, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(987, 311), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5286, 7373), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(993, 1005), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5287, 7374), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(996, 1008), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5288, 7375), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4820, 990), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5289, 4850), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1069, 7376), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5290, 7377), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1008, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1005, 63), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7378, 7379), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :51:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7339, 807), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5291, 7381), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7351, 1137), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5292, 7382), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7362, 808), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5293, 7383), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(978, 1143), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5294, 7384), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7380, 809), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5295, 7385), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5296, 4027), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(312, 810), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5297, 7386), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaEcall ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :52:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :229:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(5246, 377, 5298), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(6, 4036), // loc(callsite( builtin Sub at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(0, 1086), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(7387, 1087), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7388, 1085), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5300, 7389), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1084, 7387), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5301, 7390), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1084, 1087), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5302, 7391), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :99:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5303, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(4034, 1093), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7392, 1091), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5304, 7393), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1090, 4034), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5305, 7394), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1090, 1093), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:4) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5306, 7395), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :100:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1090, 13), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :102:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1091, 313), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :102:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(7396, 7397), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :102:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(7398, 1084), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :101:17) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1085, 312), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :101:17) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(7399, 7400), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :101:17) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(4031, 6), // loc(callsite( builtin Add at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:34) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(7402, 4036), // loc(callsite( builtin Sub at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:48) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5307, 7331), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5308, 3893), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5309, 7332), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5310, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(817, 7403), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5311, 7404), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5312, 4091), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5313, 7334), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5314, 4828), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5315, 7336), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :110:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(4031, 2), // loc(callsite( builtin Add at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:34) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(7405, 4036), // loc(callsite( builtin Sub at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:48) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5316, 7340), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5317, 3992), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5318, 7341), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5319, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(844, 7406), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5320, 7407), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5321, 7343), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5322, 7344), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5323, 7347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5324, 7348), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :111:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(4051, 4036), // loc(callsite( builtin Sub at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:43) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5325, 7352), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5326, 7353), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(917, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5327, 7409), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5328, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(902, 7408), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5329, 7410), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5330, 4839), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5331, 7359), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(920, 835), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5332, 7411), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(923, 838), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5333, 7412), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :112:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(4085, 4036), // loc(callsite( builtin Sub at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:43) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5334, 7363), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5335, 4794), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(975, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5336, 7414), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5337, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(929, 7413), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5338, 7415), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5339, 7369), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5340, 7370), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(978, 893), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5341, 7416), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(981, 896), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5342, 7417), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :113:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(4036, 1), // loc(callsite( builtin Add at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :123:30) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1085, 7418), // loc(callsite( builtin Mul at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :123:20) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5343, 4095), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5344, 4096), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5345, 4097), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5346, 4098), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5347, 4099), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7419, 1148), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5348, 7420), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7401, 810), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5349, 7421), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :114:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(811, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1160, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1372, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1373, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1375, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1382, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1383, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1154, 7422), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7429, 7423), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7430, 7424), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7431, 7425), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7432, 7426), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7433, 7427), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7434, 7428), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1391, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1392, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1394, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1401, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1402, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1404, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1410, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1385, 7436), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7443, 7437), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7444, 7438), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7445, 7439), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7446, 7440), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7447, 7441), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7448, 7442), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1424, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1427, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1426, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1428, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1829, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1830, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1429, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1411, 7450), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7457, 7451), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7458, 7452), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7459, 7453), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7460, 7454), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7461, 7455), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7462, 7456), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1431, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1432, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1439, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1440, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1900, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(538, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2278, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1430, 7464), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7471, 7465), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7472, 7466), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7473, 7467), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7474, 7468), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7475, 7469), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7476, 7470), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1154, 4585), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5350, 7478), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 811), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(811, 7479), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5351, 7480), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1160, 4915), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5352, 7481), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1372, 4920), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5353, 7482), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 1373), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1373, 7483), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5354, 7484), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5355, 1377), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5356, 2799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5357, 2805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5358, 1387), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5359, 2815), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5360, 2821), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5361, 1396), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5362, 2827), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5363, 2833), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5364, 1406), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5365, 1413), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5366, 2839), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5367, 2845), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5368, 2851), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5369, 2857), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 1428), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1428, 7485), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5370, 7486), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5371, 2772), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 1830), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1830, 7487), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5372, 7488), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 1429), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1429, 7489), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5373, 7490), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5374, 2780), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 1431), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1431, 7491), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5375, 7492), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 1432), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1432, 7493), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5376, 7494), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 1439), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1439, 7495), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5377, 7496), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 1440), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1440, 7497), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5378, 7498), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 1900), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1900, 7499), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5379, 7500), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 538), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(538, 7501), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5380, 7502), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 2278), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2278, 7503), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5381, 7504), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(7463, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(7505, 7477), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:27) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(835, 7506), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5382, 7507), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(7435, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:24) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(7508, 7449), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:28) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(838, 7509), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5383, 7510), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :126:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(591, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(594, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(601, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(615, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(622, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(539, 7511), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7516, 7512), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7517, 7513), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7518, 1726), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7519, 7514), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7520, 7515), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7521, 1691), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(649, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(652, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(659, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(666, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(632, 708), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7527, 1697), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7528, 7523), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7529, 7524), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7530, 7525), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7531, 7526), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7532, 703), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(544, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(551, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(552, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(555, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(556, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(563, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(564, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(676, 7534), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7541, 7535), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7542, 7536), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7543, 7537), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7544, 7538), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7545, 7539), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7546, 7540), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(570, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(572, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(574, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(575, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(576, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(577, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(571, 7548), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7554, 7549), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7555, 2192), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7556, 7550), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7557, 7551), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7558, 7552), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7559, 7553), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 539), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(539, 7561), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5384, 7562), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5385, 593), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5386, 596), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5387, 603), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5388, 610), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5389, 617), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5390, 624), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5391, 631), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5392, 634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5393, 641), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5394, 648), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5395, 651), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5396, 654), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5397, 661), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5398, 668), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5399, 675), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5400, 1679), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5401, 546), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 551), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(551, 7563), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5402, 7564), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5403, 1634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5404, 558), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5405, 2927), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5406, 1642), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5407, 2089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5408, 2091), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5409, 2097), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5410, 2103), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5411, 2109), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5412, 2115), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5413, 2121), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5414, 2123), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5415, 2129), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(7547, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:23) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(7565, 7560), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:27) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(893, 7566), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5416, 7567), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(7522, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:24) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(7568, 7533), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:28) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(896, 7569), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5417, 7570), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :127:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5418, 578), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5419, 587), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5420, 588), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5421, 739), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5422, 740), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5423, 741), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5424, 742), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5425, 743), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5426, 744), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5427, 745), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5428, 746), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5429, 747), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5430, 760), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5431, 766), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5432, 767), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5433, 768), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5434, 769), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5435, 761), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5436, 770), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5437, 771), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5438, 772), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5439, 756), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5440, 757), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5441, 762), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5442, 781), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5443, 732), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5444, 737), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5445, 764), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5446, 798), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5447, 800), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5448, 802), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5449, 804), // loc(callsite( ShaLoadState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :128:29) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :230:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5450, 984), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5451, 999), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5452, 1066), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(5299, 380, 5453), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(360), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(366), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(372), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(378), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(384), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(390), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(396), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(402), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(408), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(414), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(420), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(426), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(432), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(438), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(444), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(450), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(456), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(462), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(468), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(474), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(480), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(504), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(510), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(516), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(522), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(528), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(534), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(540), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(546), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:30) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(169), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(175), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(181), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(187), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(193), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(199), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(205), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(211), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(217), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(223), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(229), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(235), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(241), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(247), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(253), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(259), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(265), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(271), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(277), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(283), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(289), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(295), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(301), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(307), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(313), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(319), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(325), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(331), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(337), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(343), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(349), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(355), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(361), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(367), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(373), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(379), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(385), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(391), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(397), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(403), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(409), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(415), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(421), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(427), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(433), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(439), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(445), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(451), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(457), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(463), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(469), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(475), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(481), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(487), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(493), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(499), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(505), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(511), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(517), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(523), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(529), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(535), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(541), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(547), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:39) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(170), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(176), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(182), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(188), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(194), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(200), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(206), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(212), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(218), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(224), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(230), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(236), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(242), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(248), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(254), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(260), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(266), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(272), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(278), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(284), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(290), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(296), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(302), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(308), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(314), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(320), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(326), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(332), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(338), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(344), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(350), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(356), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(362), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(368), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(374), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(380), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(386), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(392), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(398), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(404), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(410), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(416), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(422), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(428), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(434), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(440), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(446), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(452), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(458), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(464), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(470), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(476), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(482), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(488), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(494), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(500), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(506), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(512), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(518), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(524), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(530), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(536), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(542), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(548), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:48) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(171), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(177), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(183), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(189), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(195), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(201), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(207), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(213), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(219), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(225), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(231), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(237), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(243), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(249), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(255), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(261), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(267), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(273), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(279), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(285), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(291), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(297), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(303), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(309), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(315), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(321), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(327), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(333), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(339), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(345), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(351), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(357), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(363), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(369), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(375), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(381), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(387), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(393), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(399), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(405), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(411), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(417), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(423), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(429), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(435), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(441), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(447), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(453), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(459), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(465), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(471), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(477), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(483), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(489), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(495), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(501), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(507), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(513), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(519), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(525), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(531), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(537), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(543), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(549), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:57) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(36, 4036), // loc(callsite( builtin Sub at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(7792, 1087), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(7793, 1085), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5300, 7794), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1084, 7792), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5455, 7795), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5456, 7391), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :133:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(4035, 4036), // loc(callsite( builtin Add at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:32) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5457, 7331), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5458, 3893), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5459, 7332), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5460, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(817, 7796), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5461, 7797), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5462, 4091), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5463, 7334), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5464, 4828), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5465, 7336), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :134:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5466, 7340), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5467, 3992), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5468, 7341), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5469, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(844, 4033), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5470, 7798), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5471, 7343), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5472, 7344), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5473, 7347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5474, 7348), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :135:22) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(587, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(588, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(740, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(741, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(742, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(743, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(578, 7799), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7805, 7800), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7806, 2196), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7807, 7801), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7808, 7802), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7809, 7803), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7810, 7804), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(745, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(746, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(747, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(760, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(766, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(767, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(768, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(744, 7812), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7819, 7813), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7820, 7814), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7821, 7815), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7822, 7816), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7823, 7817), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7824, 7818), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(761, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(770, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(771, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(772, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(756, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(757, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(762, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(769, 7826), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7833, 7827), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7834, 7828), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7835, 7829), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7836, 7830), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7837, 7831), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7838, 7832), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(732, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(737, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(764, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(798, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(800, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(802, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(804, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(781, 7840), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7847, 7841), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7848, 7842), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7849, 7843), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7850, 7844), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7851, 7845), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(7852, 7846), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :87:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5475, 2135), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5476, 2137), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5477, 2139), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5478, 2145), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5479, 2151), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5480, 2157), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5481, 3068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5482, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5483, 3574), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5484, 3074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5485, 2075), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5486, 3079), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5487, 2969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5488, 3001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5489, 3085), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5490, 3626), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5491, 3628), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5492, 3639), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5493, 3679), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5494, 3683), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 772), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(772, 7854), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5495, 7855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 756), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(756, 7856), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5496, 7857), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 757), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(757, 7858), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5497, 7859), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 762), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(762, 7860), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5498, 7861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5499, 3745), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5500, 734), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5501, 4987), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5502, 1735), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5503, 4989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5504, 3022), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5505, 4991), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5506, 3872), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :88:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(7839, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(7862, 7853), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:27) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(893, 7863), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5507, 7864), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :89:13) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(7811, 20), // loc(callsite( builtin Mul at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:24) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(7865, 7825), // loc(callsite( builtin Add at callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(896, 7866), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5508, 7867), // loc(callsite( VerifyUnpackU32BE ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :90:14) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :138:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(4123, 4132), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4123, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7869, 4132), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7868, 7870), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4124, 4133), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4124, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7873, 4133), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7872, 7874), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4125, 4134), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4125, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7877, 4134), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7876, 7878), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4126, 4135), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4126, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7881, 4135), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7880, 7882), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4127, 4136), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4127, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7885, 4136), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7884, 7886), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4128, 4137), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4128, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7889, 4137), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7888, 7890), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4129, 4145), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4129, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7893, 4145), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7892, 7894), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4130, 4142), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4130, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7897, 4142), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7896, 7898), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4131, 4139), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4167, 4139), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7900, 7901), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4132, 4138), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4132, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7904, 4138), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7903, 7905), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4133, 4113), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4169, 4113), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7907, 7908), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4134, 4037), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4134, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7911, 4037), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7910, 7912), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4135, 4038), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4179, 4038), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7914, 7915), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4136, 4039), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4136, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7918, 4039), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7917, 7919), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4137, 4114), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4181, 4114), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7921, 7922), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4145, 4115), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4145, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7925, 4115), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7924, 7926), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4142, 4116), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4142, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7929, 4116), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7928, 7930), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4139, 4117), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4139, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7933, 4117), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7932, 7934), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4138, 4118), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4138, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7937, 4118), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7936, 7938), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4113, 4119), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4113, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7941, 4119), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7940, 7942), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4037, 4120), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4037, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7945, 4120), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7944, 7946), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4038, 4121), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4038, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7949, 4121), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7948, 7950), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4039, 4122), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4039, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7953, 4122), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7952, 7954), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4114, 4123), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4114, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7957, 4123), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7956, 7958), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4115, 4124), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4612, 4124), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7960, 7961), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4116, 4125), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4116, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7964, 4125), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7963, 7965), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4117, 4126), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4614, 4126), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7967, 7968), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4118, 4127), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4118, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7971, 4127), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7970, 7972), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4119, 4128), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4624, 4128), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7974, 7975), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4120, 4129), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4120, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7978, 4129), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7977, 7979), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4121, 4130), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4626, 4130), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7981, 7982), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4122, 4131), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4122, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7985, 4131), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7984, 7986), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4038, 7871), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7949, 7871), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7988, 7989), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4039, 7875), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7953, 7875), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7991, 7992), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4114, 7879), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7957, 7879), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7994, 7995), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4115, 7883), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4612, 7883), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(7997, 7998), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4116, 7887), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7964, 7887), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8000, 8001), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4117, 7891), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4614, 7891), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8003, 8004), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4118, 7895), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7971, 7895), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8006, 8007), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4119, 7899), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4624, 7899), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8009, 8010), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4120, 7902), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7978, 7902), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8012, 8013), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4121, 7906), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4626, 7906), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8015, 8016), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4122, 7909), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7985, 7909), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8018, 8019), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4123, 7913), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7869, 7913), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8021, 8022), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4124, 7916), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7873, 7916), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8024, 8025), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4125, 7920), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7877, 7920), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8027, 8028), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4126, 7923), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7881, 7923), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8030, 8031), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4127, 7927), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7885, 7927), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8033, 8034), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4128, 7931), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7889, 7931), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8036, 8037), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4129, 7935), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7893, 7935), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8039, 8040), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4130, 7939), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7897, 7939), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8042, 8043), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4131, 7943), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4167, 7943), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8045, 8046), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4132, 7947), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7904, 7947), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8048, 8049), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4133, 7951), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4169, 7951), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8051, 8052), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4134, 7955), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7911, 7955), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8054, 8055), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4135, 7959), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4179, 7959), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8057, 8058), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4136, 7962), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7918, 7962), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8060, 8061), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4137, 7966), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(4181, 7966), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8063, 8064), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4145, 7969), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7925, 7969), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8066, 8067), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4142, 7973), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7929, 7973), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8069, 8070), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4139, 7976), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7933, 7976), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8072, 8073), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4138, 7980), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7937, 7980), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8075, 8076), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4113, 7983), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7941, 7983), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8078, 8079), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(4037, 7987), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7945, 7987), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8081, 8082), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :96:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7582, 7593), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7582, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8085, 7593), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8084, 8086), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7583, 7594), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7583, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8089, 7594), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8088, 8090), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7584, 7595), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7584, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8093, 7595), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8092, 8094), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7585, 7596), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7585, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8097, 7596), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8096, 8098), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7586, 7597), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7586, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8101, 7597), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8100, 8102), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7587, 7598), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7587, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8105, 7598), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8104, 8106), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7588, 7599), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7588, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8109, 7599), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8108, 8110), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7589, 7571), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7589, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8113, 7571), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8112, 8114), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7590, 7572), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7590, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8117, 7572), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8116, 8118), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7591, 7573), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7591, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8121, 7573), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8120, 8122), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(3654, 7574), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(3654, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8125, 7574), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8124, 8126), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(3655, 7575), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(3655, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8129, 7575), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8128, 8130), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(3656, 7576), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(3656, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8133, 7576), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8132, 8134), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7592, 7577), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7592, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8137, 7577), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8136, 8138), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7593, 7578), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7593, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8141, 7578), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8140, 8142), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7594, 7579), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7594, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8145, 7579), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8144, 8146), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7595, 7580), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7595, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8149, 7580), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8148, 8150), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7596, 7581), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7596, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8153, 7581), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8152, 8154), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7597, 7582), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7597, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8157, 7582), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8156, 8158), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7598, 7583), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7598, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8161, 7583), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8160, 8162), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7599, 7584), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7599, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8165, 7584), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8164, 8166), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7571, 7585), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7571, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8169, 7585), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8168, 8170), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7572, 7586), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7572, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8173, 7586), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8172, 8174), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7573, 7587), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7573, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8177, 7587), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8176, 8178), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7574, 7588), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7574, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8181, 7588), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8180, 8182), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7575, 7589), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7575, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8185, 7589), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8184, 8186), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7576, 7590), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7576, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8189, 7590), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8188, 8190), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7577, 7591), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7577, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8193, 7591), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8192, 8194), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7578, 3654), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7578, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8197, 3654), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8196, 8198), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7579, 3655), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7579, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8201, 3655), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8200, 8202), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7580, 3656), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7580, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8205, 3656), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8204, 8206), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7581, 7592), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7581, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8209, 7592), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8208, 8210), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:46) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7577, 8087), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8193, 8087), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8212, 8213), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7578, 8091), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8197, 8091), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8215, 8216), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7579, 8095), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8201, 8095), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8218, 8219), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7580, 8099), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8205, 8099), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8221, 8222), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7581, 8103), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8209, 8103), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8224, 8225), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7582, 8107), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8085, 8107), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8227, 8228), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7583, 8111), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8089, 8111), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8230, 8231), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7584, 8115), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8093, 8115), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8233, 8234), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7585, 8119), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8097, 8119), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8236, 8237), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7586, 8123), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8101, 8123), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8239, 8240), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7587, 8127), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8105, 8127), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8242, 8243), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7588, 8131), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8109, 8131), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8245, 8246), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7589, 8135), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8113, 8135), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8248, 8249), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7590, 8139), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8117, 8139), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8251, 8252), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7591, 8143), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8121, 8143), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8254, 8255), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(3654, 8147), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8125, 8147), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8257, 8258), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(3655, 8151), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8129, 8151), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8260, 8261), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(3656, 8155), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8133, 8155), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8263, 8264), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7592, 8159), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8137, 8159), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8266, 8267), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7593, 8163), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8141, 8163), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8269, 8270), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7594, 8167), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8145, 8167), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8272, 8273), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7595, 8171), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8149, 8171), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8275, 8276), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7596, 8175), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8153, 8175), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8278, 8279), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7597, 8179), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8157, 8179), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8281, 8282), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7598, 8183), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8161, 8183), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8284, 8285), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7599, 8187), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8165, 8187), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8287, 8288), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7571, 8191), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8169, 8191), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8290, 8291), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7572, 8195), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8173, 8195), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8293, 8294), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7573, 8199), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8177, 8199), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8296, 8297), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7574, 8203), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8181, 8203), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8299, 8300), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7575, 8207), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8185, 8207), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8302, 8303), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7576, 8211), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8189, 8211), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8305, 8306), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :97:16) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(744, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(745, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(746, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(747, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(760, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(766, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(767, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(768, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7811, 8308), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8316, 8309), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8317, 8310), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8318, 8311), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8319, 8312), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8320, 8313), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8321, 8314), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8322, 8315), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(781, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(732, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(737, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(764, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(798, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(800, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(802, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(804, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7839, 8324), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8332, 8325), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8333, 8326), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8334, 8327), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8335, 8328), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8336, 8329), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8337, 8330), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8338, 8331), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:25) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7761, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7762, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7763, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7764, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7765, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7766, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7767, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7768, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7769, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7770, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7771, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7772, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7773, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7774, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7775, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7760, 8340), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8355, 8341), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8356, 8342), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8357, 8343), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8358, 8344), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8359, 8345), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8360, 8346), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8361, 8347), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8362, 8348), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8363, 8349), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8364, 8350), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8365, 8351), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8366, 8352), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8367, 8353), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8368, 8354), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7777, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7778, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7779, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7780, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7781, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7782, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7783, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7784, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7785, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7786, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7787, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7788, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7789, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7790, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7791, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7776, 8370), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8385, 8371), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8386, 8372), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8387, 8373), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8388, 8374), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8389, 8375), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8390, 8376), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8391, 8377), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8392, 8378), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8393, 8379), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8394, 8380), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8395, 8381), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8396, 8382), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8397, 8383), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8398, 8384), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:49) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7571, 7632), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7571), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8401, 7696), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8400, 8402), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7572, 7633), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7572), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8405, 7697), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8404, 8406), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7573, 7634), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7573), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8409, 7698), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8408, 8410), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7574, 7635), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7574), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8413, 7699), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8412, 8414), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7575, 7636), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7575), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8417, 7700), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8416, 8418), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7576, 7637), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7576), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8421, 7701), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8420, 8422), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7577, 7638), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7577), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8425, 7702), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8424, 8426), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7578, 7639), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7578), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8429, 7703), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8428, 8430), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7579, 7640), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7579), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8433, 7704), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8432, 8434), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7580, 7641), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7580), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8437, 7705), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8436, 8438), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7581, 7642), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7581), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8441, 7706), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8440, 8442), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7582, 7643), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7582), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8445, 7707), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8444, 8446), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7583, 7644), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7583), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8449, 7708), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8448, 8450), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7584, 7645), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7584), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8453, 7709), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8452, 8454), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7585, 7646), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7585), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8457, 7710), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8456, 8458), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7586, 7647), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7586), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8461, 7711), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8460, 8462), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7587, 7648), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7587), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8465, 7712), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8464, 8466), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7588, 7649), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7588), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8469, 7713), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8468, 8470), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7589, 7650), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7589), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8473, 7714), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8472, 8474), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7590, 7651), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7590), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8477, 7715), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8476, 8478), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7591, 7652), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7591), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8481, 7716), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8480, 8482), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(3654, 7653), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 3654), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8485, 7717), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8484, 8486), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(3655, 7654), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 3655), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8489, 7718), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8488, 8490), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(3656, 7655), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 3656), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8493, 7719), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8492, 8494), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7592, 7656), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7592), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8497, 7720), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8496, 8498), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7593, 7657), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7593), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8501, 7721), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8500, 8502), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7594, 7658), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7594), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8505, 7722), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8504, 8506), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7595, 7659), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7595), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8509, 7723), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8508, 8510), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7596, 7660), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7596), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8513, 7724), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8512, 8514), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7597, 7661), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7597), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8517, 7725), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8516, 8518), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7598, 7662), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7598), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8521, 7726), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8520, 8522), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7599, 7663), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7599), // loc(callsite( builtin Sub at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8525, 7727), // loc(callsite( builtin Mul at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8524, 8526), // loc(callsite( builtin Add at callsite( ChU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :25:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:71) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8407, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8411, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8415, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8419, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8423, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8427, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8431, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8435, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8439, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8443, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8447, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8451, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8455, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8459, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8463, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8403, 8528), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8543, 8529), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8544, 8530), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8545, 8531), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8546, 8532), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8547, 8533), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8548, 8534), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8549, 8535), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8550, 8536), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8551, 8537), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8552, 8538), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8553, 8539), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8554, 8540), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8555, 8541), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8556, 8542), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8471, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8475, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8479, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8483, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8487, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8491, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8495, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8499, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8503, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8507, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8511, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8515, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8519, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8523, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8527, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8467, 8558), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8573, 8559), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8574, 8560), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8575, 8561), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8576, 8562), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8577, 8563), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8578, 8564), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8579, 8565), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8580, 8566), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8581, 8567), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8582, 8568), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8583, 8569), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8584, 8570), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8585, 8571), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8586, 8572), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:65) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8217, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8220, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8223, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8226, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8229, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8232, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8235, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8238, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8241, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8244, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8247, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8250, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8253, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8256, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8259, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8214, 8588), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8603, 8589), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8604, 8590), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8605, 8591), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8606, 8592), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8607, 8593), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8608, 8594), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8609, 8595), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8610, 8596), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8611, 8597), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8612, 8598), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8613, 8599), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8614, 8600), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8615, 8601), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8616, 8602), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8265, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8268, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8271, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8274, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8277, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8280, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8283, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8286, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8289, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8292, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8295, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8298, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8301, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8304, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8307, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8262, 8618), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8633, 8619), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8634, 8620), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8635, 8621), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8636, 8622), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8637, 8623), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8638, 8624), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8639, 8625), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8640, 8626), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8641, 8627), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8642, 8628), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8643, 8629), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8644, 8630), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8645, 8631), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8646, 8632), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:89) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8557, 8617), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:58) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8587, 8647), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:58) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8369, 8648), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:42) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8399, 8649), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:42) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(835, 8650), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:34) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(838, 8651), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:34) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8323, 8652), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8339, 8653), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :98:18) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4113, 7600), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7664), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8656, 8657), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7600), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4113, 8659), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8660, 7664), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8658, 8661), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4113), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8663, 7600), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8664, 7664), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8662, 8665), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8656, 7664), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8666, 8667), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4037, 7601), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7665), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8669, 8670), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7601), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4037, 8672), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8673, 7665), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8671, 8674), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4037), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8676, 7601), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8677, 7665), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8675, 8678), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8669, 7665), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8679, 8680), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4038, 7602), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7666), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8682, 8683), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7602), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4038, 8685), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8686, 7666), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8684, 8687), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4038), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8689, 7602), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8690, 7666), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8688, 8691), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8682, 7666), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8692, 8693), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4039, 7603), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7667), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8695, 8696), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7603), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4039, 8698), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8699, 7667), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8697, 8700), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4039), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8702, 7603), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8703, 7667), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8701, 8704), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8695, 7667), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8705, 8706), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4114, 7604), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7668), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8708, 8709), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7604), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4114, 8711), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8712, 7668), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8710, 8713), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4114), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8715, 7604), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8716, 7668), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8714, 8717), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8708, 7668), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8718, 8719), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4115, 7605), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7669), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8721, 8722), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7605), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4115, 8724), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8725, 7669), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8723, 8726), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4115), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8728, 7605), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8729, 7669), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8727, 8730), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8721, 7669), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8731, 8732), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4116, 7606), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7670), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8734, 8735), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7606), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4116, 8737), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8738, 7670), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8736, 8739), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4116), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8741, 7606), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8742, 7670), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8740, 8743), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8734, 7670), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8744, 8745), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4117, 7607), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7671), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8747, 8748), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7607), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4117, 8750), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8751, 7671), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8749, 8752), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4117), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8754, 7607), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8755, 7671), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8753, 8756), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8747, 7671), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8757, 8758), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4118, 7608), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7672), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8760, 8761), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7608), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4118, 8763), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8764, 7672), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8762, 8765), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4118), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8767, 7608), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8768, 7672), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8766, 8769), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8760, 7672), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8770, 8771), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4119, 7609), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7673), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8773, 8774), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7609), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4119, 8776), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8777, 7673), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8775, 8778), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4119), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8780, 7609), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8781, 7673), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8779, 8782), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8773, 7673), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8783, 8784), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4120, 7610), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7674), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8786, 8787), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7610), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4120, 8789), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8790, 7674), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8788, 8791), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4120), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8793, 7610), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8794, 7674), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8792, 8795), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8786, 7674), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8796, 8797), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4121, 7611), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7675), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8799, 8800), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7611), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4121, 8802), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8803, 7675), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8801, 8804), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4121), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8806, 7611), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8807, 7675), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8805, 8808), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8799, 7675), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8809, 8810), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4122, 7612), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7676), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8812, 8813), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7612), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4122, 8815), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8816, 7676), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8814, 8817), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4122), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8819, 7612), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8820, 7676), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8818, 8821), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8812, 7676), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8822, 8823), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4123, 7613), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7677), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8825, 8826), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7613), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4123, 8828), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8829, 7677), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8827, 8830), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4123), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8832, 7613), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8833, 7677), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8831, 8834), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8825, 7677), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8835, 8836), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4124, 7614), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7678), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8838, 8839), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7614), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4124, 8841), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8842, 7678), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8840, 8843), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4124), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8845, 7614), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8846, 7678), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8844, 8847), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8838, 7678), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8848, 8849), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4125, 7615), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7679), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8851, 8852), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7615), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4125, 8854), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8855, 7679), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8853, 8856), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4125), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8858, 7615), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8859, 7679), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8857, 8860), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8851, 7679), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8861, 8862), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4126, 7616), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7680), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8864, 8865), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7616), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4126, 8867), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8868, 7680), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8866, 8869), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4126), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8871, 7616), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8872, 7680), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8870, 8873), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8864, 7680), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8874, 8875), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4127, 7617), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7681), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8877, 8878), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7617), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4127, 8880), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8881, 7681), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8879, 8882), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4127), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8884, 7617), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8885, 7681), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8883, 8886), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8877, 7681), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8887, 8888), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4128, 7618), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7682), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8890, 8891), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7618), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4128, 8893), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8894, 7682), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8892, 8895), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4128), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8897, 7618), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8898, 7682), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8896, 8899), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8890, 7682), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8900, 8901), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4129, 7619), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7683), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8903, 8904), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7619), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4129, 8906), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8907, 7683), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8905, 8908), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4129), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8910, 7619), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8911, 7683), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8909, 8912), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8903, 7683), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8913, 8914), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4130, 7620), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7684), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8916, 8917), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7620), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4130, 8919), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8920, 7684), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8918, 8921), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4130), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8923, 7620), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8924, 7684), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8922, 8925), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8916, 7684), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8926, 8927), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4131, 7621), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7685), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8929, 8930), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7621), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4131, 8932), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8933, 7685), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8931, 8934), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4131), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8936, 7621), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8937, 7685), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8935, 8938), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8929, 7685), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8939, 8940), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4132, 7622), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7686), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8942, 8943), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7622), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4132, 8945), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8946, 7686), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8944, 8947), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4132), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8949, 7622), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8950, 7686), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8948, 8951), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8942, 7686), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8952, 8953), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4133, 7623), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7687), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8955, 8956), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7623), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4133, 8958), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8959, 7687), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8957, 8960), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4133), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8962, 7623), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8963, 7687), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8961, 8964), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8955, 7687), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8965, 8966), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4134, 7624), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7688), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8968, 8969), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7624), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4134, 8971), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8972, 7688), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8970, 8973), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4134), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8975, 7624), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8976, 7688), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8974, 8977), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8968, 7688), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8978, 8979), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4135, 7625), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7689), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8981, 8982), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7625), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4135, 8984), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8985, 7689), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8983, 8986), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4135), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8988, 7625), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8989, 7689), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8987, 8990), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8981, 7689), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8991, 8992), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4136, 7626), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7690), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8994, 8995), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7626), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4136, 8997), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8998, 7690), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8996, 8999), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4136), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9001, 7626), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9002, 7690), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9000, 9003), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8994, 7690), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9004, 9005), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4137, 7627), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7691), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9007, 9008), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7627), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4137, 9010), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9011, 7691), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9009, 9012), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4137), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9014, 7627), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9015, 7691), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9013, 9016), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9007, 7691), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9017, 9018), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4145, 7628), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7692), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9020, 9021), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7628), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4145, 9023), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9024, 7692), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9022, 9025), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4145), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9027, 7628), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9028, 7692), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9026, 9029), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9020, 7692), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9030, 9031), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4142, 7629), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7693), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9033, 9034), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7629), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4142, 9036), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9037, 7693), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9035, 9038), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4142), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9040, 7629), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9041, 7693), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9039, 9042), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9033, 7693), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9043, 9044), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4139, 7630), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7694), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9046, 9047), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7630), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4139, 9049), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9050, 7694), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9048, 9051), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4139), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9053, 7630), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9054, 7694), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9052, 9055), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9046, 7694), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9056, 9057), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4138, 7631), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7695), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:21) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9059, 9060), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 7631), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:14) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4138, 9062), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:9) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9063, 7695), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9061, 9064), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :16:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1, 4138), // loc(callsite( builtin Sub at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:7) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9066, 7631), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:15) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9067, 7695), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9065, 9068), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :17:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9059, 7695), // loc(callsite( builtin Mul at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :19:16) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9069, 9070), // loc(callsite( builtin Add at callsite( MajU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :18:29) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:50) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(8681, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8694, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8707, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8720, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8733, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8746, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8759, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8772, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8785, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8798, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8811, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8824, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8837, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8850, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8863, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8668, 9072), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9087, 9073), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9088, 9074), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9089, 9075), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9090, 9076), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9091, 9077), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9092, 9078), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9093, 9079), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9094, 9080), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9095, 9081), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9096, 9082), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9097, 9083), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9098, 9084), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9099, 9085), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9100, 9086), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8889, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8902, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8915, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8928, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8941, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8954, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8967, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8980, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8993, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9006, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9019, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9032, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9045, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9058, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9071, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8876, 9102), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9117, 9103), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9118, 9104), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9119, 9105), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9120, 9106), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9121, 9107), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9122, 9108), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9123, 9109), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9124, 9110), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9125, 9111), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9126, 9112), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9127, 9113), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9128, 9114), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9129, 9115), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9130, 9116), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:43) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7993, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7996, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7999, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8002, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8005, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8008, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8011, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8014, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8017, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8020, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8023, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8026, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8029, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8032, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8035, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7990, 9132), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9147, 9133), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9148, 9134), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9149, 9135), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9150, 9136), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9151, 9137), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9152, 9138), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9153, 9139), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9154, 9140), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9155, 9141), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9156, 9142), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9157, 9143), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9158, 9144), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9159, 9145), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9160, 9146), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8041, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8044, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8047, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8050, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8053, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8056, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8059, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8062, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8065, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8068, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8071, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8074, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8077, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8080, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(8083, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8038, 9162), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9177, 9163), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9178, 9164), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9179, 9165), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9180, 9166), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9181, 9167), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9182, 9168), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9183, 9169), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9184, 9170), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9185, 9171), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9186, 9172), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9187, 9173), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9188, 9174), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9189, 9175), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9190, 9176), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:68) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9101, 9161), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:36) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9131, 9191), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:36) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8654, 9192), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8655, 9193), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :99:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(7729, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7730, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7731, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7732, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7733, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7734, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7735, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7736, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7737, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7738, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7739, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7740, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7741, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7742, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7743, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7728, 9196), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9211, 9197), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9212, 9198), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9213, 9199), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9214, 9200), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9215, 9201), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9216, 9202), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9217, 9203), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9218, 9204), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9219, 9205), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9220, 9206), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9221, 9207), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9222, 9208), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9223, 9209), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9224, 9210), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7745, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7746, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7747, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7748, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7749, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7750, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7751, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7752, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7753, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7754, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7755, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7756, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7757, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7758, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(7759, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7744, 9226), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9241, 9227), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9242, 9228), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9243, 9229), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9244, 9230), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9245, 9231), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9246, 9232), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9247, 9233), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9248, 9234), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9249, 9235), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9250, 9236), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9251, 9237), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9252, 9238), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9253, 9239), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9254, 9240), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:38) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8654, 9225), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8655, 9255), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeAE ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :100:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :139:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5509, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5510, 1095), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5511, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1096, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1093, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9258, 9259), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9260, 1090), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9261, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(9194, 9262), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9195, 9261), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5512, 3995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5513, 4190), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5514, 4001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(2744, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2737, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9265, 9266), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9267, 2736), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9268, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(9264, 9269), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5515, 7478), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5516, 7480), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5517, 7481), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5518, 7482), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5519, 7484), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5520, 1377), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5521, 2799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5522, 2805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5523, 1387), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5524, 2815), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5525, 2821), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5526, 1396), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5527, 2827), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5528, 2833), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5529, 1406), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5530, 1413), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5531, 2839), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5532, 2845), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5533, 2851), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5534, 2857), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5535, 7486), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5536, 2772), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5537, 7488), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5538, 7490), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5539, 2780), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5540, 7492), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5541, 7494), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5542, 7496), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5543, 7498), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5544, 7500), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5545, 7502), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5546, 7504), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1391, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1392, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1394, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1401, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1402, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1404, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1410, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7435, 1814), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9278, 9271), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9279, 9272), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9280, 9273), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9281, 9274), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9282, 9275), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9283, 9276), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9284, 9277), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1430, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1431, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1432, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1439, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1440, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1900, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(538, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(2278, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7463, 9286), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9294, 9287), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9295, 9288), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9296, 9289), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9297, 9290), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9298, 9291), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9299, 9292), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9300, 9293), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9285, 9263), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5547, 9302), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(9301, 9270), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5548, 9303), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :142:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5549, 4003), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5550, 4009), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5551, 4150), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(2751, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9304, 4880), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9305, 2745), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9306, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(9256, 9307), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9257, 9306), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5552, 2755), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5553, 4853), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5554, 4861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(2761, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2760, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9310, 9311), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9312, 2753), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(9313, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(9309, 9314), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5555, 7562), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5556, 593), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5557, 596), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5558, 603), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5559, 610), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5560, 617), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5561, 624), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5562, 631), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5563, 634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5564, 641), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5565, 648), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5566, 651), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5567, 654), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5568, 661), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5569, 668), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5570, 675), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5571, 1679), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5572, 546), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5573, 7564), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5574, 1634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5575, 558), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5576, 2927), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5577, 1642), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5578, 2089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5579, 2091), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5580, 2097), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5581, 2103), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5582, 2109), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5583, 2115), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5584, 2121), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5585, 2123), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5586, 2129), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(632, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(639, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(646, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(649, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(659, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(666, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(673, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7522, 9316), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9323, 9317), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9324, 9318), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9325, 9319), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9326, 697), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9327, 9320), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9328, 9321), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9329, 9322), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(571, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(570, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(572, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(573, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(574, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(575, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(576, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(577, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(7547, 9331), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9339, 9332), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9340, 9333), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9341, 9334), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9342, 9335), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9343, 9336), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9344, 9337), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9345, 9338), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:25) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9330, 9308), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5587, 9347), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(9346, 9315), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5588, 9348), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :143:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1084, 51), // loc(callsite( builtin Mul at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :154:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1085, 313), // loc(callsite( builtin Mul at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :154:48) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(9349, 9350), // loc(callsite( builtin Add at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :154:30) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5589, 4095), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5590, 4096), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(4732, 808), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5591, 9352), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5592, 4098), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5593, 4099), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5594, 7420), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(9351, 810), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5595, 9353), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaLoadData ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :144:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :231:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5596, 899), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5597, 914), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5598, 926), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5599, 972), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5600, 984), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5601, 999), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5602, 1054), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5603, 1060), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5604, 1066), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(5454, 383, 5605), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(552), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(557), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(562), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(567), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(572), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(577), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(582), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(587), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(592), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(597), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(602), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(607), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(612), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(617), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(622), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(627), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(632), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(637), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(642), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(647), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(652), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(657), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(662), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(667), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(672), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(677), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(682), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(687), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(692), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(697), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(702), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(707), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:35) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(553), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(558), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(563), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(568), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(573), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(578), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(583), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(588), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(593), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(598), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(603), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(608), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(613), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(618), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(623), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(628), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(633), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(638), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(643), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(648), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(653), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(658), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(663), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(668), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(673), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(678), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(683), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(688), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(693), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(698), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(703), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(708), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:62) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(554), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(559), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(564), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(569), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(574), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(579), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(584), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(589), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(594), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(599), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(604), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(609), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(614), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(619), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(624), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(629), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(634), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(639), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(644), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(649), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(654), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(659), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(664), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(669), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(674), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(679), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(684), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(689), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(694), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(699), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(704), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(709), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:71) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(555), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(560), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(565), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(570), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(575), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(580), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(585), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(590), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(595), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(600), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(605), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(610), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(615), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(620), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(625), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(630), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(635), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(640), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(645), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(650), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(655), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(660), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(665), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(670), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(675), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(680), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(685), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(690), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(695), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(700), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(705), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(710), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :29:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:81) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(314, 4036), // loc(callsite( builtin Sub at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(9482, 1087), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(9483, 1085), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5300, 9484), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1084, 9482), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5607, 9485), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5608, 7391), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :163:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(4035, 23), // loc(callsite( builtin Add at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:32) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(9486, 4036), // loc(callsite( builtin Add at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:40) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5609, 7331), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5610, 3893), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5611, 7332), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5612, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(817, 9487), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5613, 9488), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5614, 4091), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5615, 7334), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5616, 4828), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5617, 7336), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :164:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9436, 9421), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9436, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9490, 9421), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9489, 9491), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9437, 9422), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9437, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9494, 9422), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9493, 9495), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9438, 9423), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9438, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9498, 9423), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9497, 9499), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9439, 9424), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9439, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9502, 9424), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9501, 9503), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9440, 9425), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9440, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9506, 9425), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9505, 9507), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9441, 9426), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9441, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9510, 9426), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9509, 9511), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9442, 9427), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9442, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9514, 9427), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9513, 9515), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9443, 9428), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9443, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9518, 9428), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9517, 9519), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9444, 9429), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9444, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9522, 9429), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9521, 9523), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9445, 9430), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9445, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9526, 9430), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9525, 9527), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9446, 9431), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9446, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9530, 9431), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9529, 9531), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9447, 9432), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9447, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9534, 9432), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9533, 9535), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9448, 9433), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9448, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9538, 9433), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9537, 9539), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9449, 9434), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9449, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9542, 9434), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9541, 9543), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9418, 9435), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9418, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9546, 9435), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9545, 9547), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9419, 9436), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9419, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9550, 9436), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9549, 9551), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9420, 9437), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9420, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9554, 9437), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9553, 9555), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9421, 9438), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9421, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9558, 9438), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9557, 9559), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9422, 9439), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9422, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9562, 9439), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9561, 9563), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9423, 9440), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9423, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9566, 9440), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9565, 9567), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9424, 9441), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9424, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9570, 9441), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9569, 9571), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9425, 9442), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9425, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9574, 9442), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9573, 9575), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9426, 9443), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9426, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9578, 9443), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9577, 9579), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9427, 9444), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9427, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9582, 9444), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9581, 9583), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9428, 9445), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9428, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9586, 9445), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9585, 9587), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9429, 9446), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9429, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9590, 9446), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9589, 9591), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9430, 9447), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9430, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9594, 9447), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9593, 9595), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9431, 9448), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9431, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9598, 9448), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9597, 9599), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9432, 9449), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9432, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9602, 9449), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9601, 9603), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9425, 9492), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9574, 9492), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9605, 9606), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9426, 9496), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9578, 9496), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9608, 9609), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9427, 9500), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9582, 9500), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9611, 9612), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9428, 9504), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9586, 9504), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9614, 9615), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9429, 9508), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9590, 9508), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9617, 9618), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9430, 9512), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9594, 9512), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9620, 9621), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9431, 9516), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9598, 9516), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9623, 9624), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9432, 9520), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9602, 9520), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9626, 9627), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9433, 9524), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9433, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9630, 9524), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9629, 9631), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9434, 9528), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9434, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9634, 9528), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9633, 9635), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9435, 9532), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9435, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9638, 9532), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9637, 9639), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9436, 9536), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9490, 9536), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9641, 9642), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9437, 9540), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9494, 9540), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9644, 9645), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9438, 9544), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9498, 9544), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9647, 9648), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9439, 9548), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9502, 9548), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9650, 9651), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9440, 9552), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9506, 9552), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9653, 9654), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9441, 9556), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9510, 9556), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9656, 9657), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9442, 9560), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9514, 9560), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9659, 9660), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9443, 9564), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9518, 9564), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9662, 9663), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9444, 9568), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9522, 9568), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9665, 9666), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9445, 9572), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9526, 9572), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9668, 9669), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9446, 9576), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9530, 9576), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9671, 9672), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9447, 9580), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9534, 9580), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9674, 9675), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9448, 9584), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9538, 9584), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9677, 9678), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9449, 9588), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9542, 9588), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9680, 9681), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9418, 9592), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9546, 9592), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9683, 9684), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9419, 9596), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9550, 9596), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9686, 9687), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9420, 9600), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9554, 9600), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9689, 9690), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9421, 9604), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9558, 9604), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9692, 9693), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9422, 9433), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9562, 9433), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9695, 9696), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9423, 9434), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9566, 9434), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9698, 9699), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9424, 9435), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9570, 9435), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9701, 9702), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :84:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9373, 9364), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9373, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9705, 9364), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9704, 9706), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9374, 9365), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9374, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9709, 9365), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9708, 9710), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9375, 9366), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9375, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9713, 9366), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9712, 9714), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9376, 9367), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9376, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9717, 9367), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9716, 9718), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9377, 9368), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9377, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9721, 9368), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9720, 9722), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9378, 9369), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9378, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9725, 9369), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9724, 9726), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9379, 9370), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9379, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9729, 9370), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9728, 9730), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9380, 9371), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9380, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9733, 9371), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9732, 9734), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9381, 9372), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9381, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9737, 9372), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9736, 9738), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9382, 9373), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9382, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9741, 9373), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9740, 9742), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9383, 9374), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9383, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9745, 9374), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9744, 9746), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9384, 9375), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9384, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9749, 9375), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9748, 9750), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9385, 9376), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9385, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9753, 9376), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9752, 9754), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9354, 9377), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9354, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9757, 9377), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9756, 9758), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9355, 9378), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9355, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9761, 9378), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9760, 9762), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9356, 9379), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9356, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9765, 9379), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9764, 9766), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9357, 9380), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9357, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9769, 9380), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9768, 9770), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9358, 9381), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9358, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9773, 9381), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9772, 9774), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9359, 9382), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9359, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9777, 9382), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9776, 9778), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9360, 9383), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9360, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9781, 9383), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9780, 9782), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9361, 9384), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9361, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9785, 9384), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9784, 9786), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9362, 9385), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9362, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9789, 9385), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9788, 9790), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:48) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9371, 9707), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9371, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9793, 9707), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9792, 9794), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9372, 9711), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9372, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9797, 9711), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9796, 9798), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9373, 9715), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9705, 9715), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9800, 9801), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9374, 9719), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9709, 9719), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9803, 9804), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9375, 9723), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9713, 9723), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9806, 9807), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9376, 9727), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9717, 9727), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9809, 9810), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9377, 9731), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9721, 9731), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9812, 9813), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9378, 9735), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9725, 9735), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9815, 9816), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9379, 9739), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9729, 9739), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9818, 9819), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9380, 9743), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9733, 9743), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9821, 9822), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9381, 9747), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9737, 9747), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9824, 9825), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9382, 9751), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9741, 9751), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9827, 9828), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9383, 9755), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9745, 9755), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9830, 9831), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9384, 9759), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9749, 9759), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9833, 9834), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9385, 9763), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9753, 9763), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9836, 9837), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9354, 9767), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9757, 9767), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9839, 9840), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9355, 9771), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9761, 9771), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9842, 9843), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9356, 9775), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9765, 9775), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9845, 9846), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9357, 9779), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9769, 9779), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9848, 9849), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9358, 9783), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9773, 9783), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9851, 9852), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9359, 9787), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9777, 9787), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9854, 9855), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9360, 9791), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9781, 9791), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9857, 9858), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9361, 9363), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9785, 9363), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9860, 9861), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9362, 9364), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9789, 9364), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9863, 9864), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9363, 9365), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9363, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9867, 9365), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9866, 9868), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9364, 9366), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9364, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9871, 9366), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9870, 9872), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9365, 9367), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9365, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9875, 9367), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9874, 9876), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9366, 9368), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9366, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9879, 9368), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9878, 9880), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9367, 9369), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9367, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9883, 9369), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9882, 9884), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9368, 9370), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9368, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9887, 9370), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9886, 9888), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9369, 9371), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9369, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9891, 9371), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9890, 9892), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9370, 9372), // loc(callsite( builtin Add at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:4) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9370, 7), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:12) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9895, 9372), // loc(callsite( builtin Mul at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:16) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9894, 9896), // loc(callsite( builtin Sub at callsite( BitXor ( zirgen/circuit/rv32im/v2/dsl/bits.zir :51:8) at callsite( XorU32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :10:12) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :85:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9610, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9613, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9616, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9619, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9622, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9625, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9628, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9632, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9636, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9640, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9643, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9646, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9649, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9652, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9655, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9607, 9898), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9913, 9899), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9914, 9900), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9915, 9901), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9916, 9902), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9917, 9903), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9918, 9904), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9919, 9905), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9920, 9906), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9921, 9907), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9922, 9908), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9923, 9909), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9924, 9910), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9925, 9911), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9926, 9912), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9661, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9664, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9667, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9670, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9673, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9676, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9679, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9682, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9685, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9688, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9691, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9694, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9697, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9700, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9703, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9658, 9928), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9943, 9929), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9944, 9930), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9945, 9931), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9946, 9932), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9947, 9933), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9948, 9934), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9949, 9935), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9950, 9936), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9951, 9937), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9952, 9938), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9953, 9939), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9954, 9940), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9955, 9941), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9956, 9942), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9799, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9802, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9805, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9808, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9811, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9814, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9817, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9820, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9823, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9826, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9829, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9832, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9835, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9838, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9841, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9795, 9958), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9973, 9959), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9974, 9960), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9975, 9961), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9976, 9962), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9977, 9963), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9978, 9964), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9979, 9965), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9980, 9966), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9981, 9967), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9982, 9968), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9983, 9969), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9984, 9970), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9985, 9971), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9986, 9972), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9847, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9850, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9853, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9856, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9859, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9862, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9865, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9869, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9873, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9877, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9881, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9885, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9889, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9893, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9897, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9844, 9988), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10003, 9989), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10004, 9990), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10005, 9991), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10006, 9992), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10007, 9993), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10008, 9994), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10009, 9995), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10010, 9996), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10011, 9997), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10012, 9998), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10013, 9999), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10014, 10000), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10015, 10001), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10016, 10002), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:40) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9451, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9452, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9453, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9454, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9455, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9456, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9457, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9458, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9459, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9460, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9461, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9462, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9463, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9464, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9465, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9450, 10018), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10033, 10019), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10034, 10020), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10035, 10021), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10036, 10022), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10037, 10023), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10038, 10024), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10039, 10025), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10040, 10026), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10041, 10027), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10042, 10028), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10043, 10029), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10044, 10030), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10045, 10031), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10046, 10032), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9467, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9468, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9469, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9470, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9471, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9472, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9473, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9474, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9475, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9476, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9477, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9478, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9479, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9480, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9481, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9466, 10048), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10063, 10049), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10064, 10050), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10065, 10051), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10066, 10052), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10067, 10053), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10068, 10054), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10069, 10055), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10070, 10056), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10071, 10057), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10072, 10058), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10073, 10059), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10074, 10060), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10075, 10061), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10076, 10062), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:57) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9387, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9388, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9389, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9390, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9391, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9392, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9393, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9394, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9395, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9396, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9397, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9398, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9399, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9400, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9401, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9386, 10078), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10093, 10079), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10094, 10080), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10095, 10081), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10096, 10082), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10097, 10083), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10098, 10084), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10099, 10085), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10100, 10086), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10101, 10087), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10102, 10088), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10103, 10089), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10104, 10090), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10105, 10091), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10106, 10092), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9403, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9404, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9405, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9406, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9407, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9408, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9409, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9410, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9411, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9412, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9413, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9414, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9415, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9416, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(9417, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(9402, 10108), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10123, 10109), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10124, 10110), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10125, 10111), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10126, 10112), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10127, 10113), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10128, 10114), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10129, 10115), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10130, 10116), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10131, 10117), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10132, 10118), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10133, 10119), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10134, 10120), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10135, 10121), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10136, 10122), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:70) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10047, 10107), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:50) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10077, 10137), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:50) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9987, 10138), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:33) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10017, 10139), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:33) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9927, 10140), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9957, 10141), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ComputeWBack ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :86:16) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :165:24) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5618, 1092), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5619, 1095), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5620, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(10142, 9262), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10143, 9261), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5621, 3995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5622, 4190), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5623, 4001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(10145, 9269), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5624, 2135), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5625, 2137), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5626, 2139), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5627, 2145), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5628, 2151), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5629, 2157), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5630, 3068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5631, 2068), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5632, 3574), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5633, 3074), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5634, 2075), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5635, 3079), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5636, 2969), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5637, 3001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5638, 3085), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5639, 3626), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5640, 3628), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5641, 3639), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5642, 3679), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5643, 3683), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5644, 7855), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5645, 7857), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5646, 7859), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5647, 7861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5648, 3745), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5649, 734), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5650, 4987), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5651, 1735), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5652, 4989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5653, 3022), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5654, 4991), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5655, 3872), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(8323, 10144), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5656, 10147), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(8339, 10146), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5657, 10148), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :166:27) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5658, 4003), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5659, 4009), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5660, 4150), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9194, 9307), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9195, 9306), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5661, 2755), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5662, 4853), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5663, 4861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(10150, 9314), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5664, 7478), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5665, 7480), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5666, 7481), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5667, 7482), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5668, 7484), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5669, 1377), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5670, 2799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5671, 2805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5672, 1387), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5673, 2815), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5674, 2821), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5675, 1396), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5676, 2827), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5677, 2833), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5678, 1406), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5679, 1413), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5680, 2839), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5681, 2845), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5682, 2851), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5683, 2857), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5684, 7486), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5685, 2772), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5686, 7488), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5687, 7490), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5688, 2780), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5689, 7492), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5690, 7494), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5691, 7496), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5692, 7498), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5693, 7500), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5694, 7502), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5695, 7504), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9285, 10149), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5696, 10152), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(9301, 10151), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5697, 10153), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :170:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5698, 2765), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(785), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 10154), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(10154, 10155), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(5699, 10156), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(786), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 10157), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(10157, 10158), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(5700, 10159), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(10157, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10154, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10160, 10161), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10162, 2763), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10163, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(9256, 10164), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9257, 10163), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Get(787), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 10167), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(10167, 10168), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(5701, 10169), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(788), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 10170), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(10170, 10171), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(5702, 10172), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Get(789), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 10173), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(10173, 10174), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(5703, 10175), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(10173, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10170, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10176, 10177), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10178, 10167), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10179, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(10166, 10180), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5704, 7562), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5705, 593), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5706, 596), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5707, 603), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5708, 610), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5709, 617), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5710, 624), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5711, 631), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5712, 634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5713, 641), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5714, 648), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5715, 651), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5716, 654), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5717, 661), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5718, 668), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5719, 675), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5720, 1679), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5721, 546), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5722, 7564), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5723, 1634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5724, 558), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5725, 2927), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5726, 1642), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5727, 2089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5728, 2091), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5729, 2097), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5730, 2103), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5731, 2109), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5732, 2115), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5733, 2121), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5734, 2123), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5735, 2129), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9330, 10165), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5736, 10182), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(9346, 10181), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5737, 10183), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :171:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1084, 315), // loc(callsite( builtin Mul at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :182:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1085, 51), // loc(callsite( builtin Mul at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :182:55) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(10184, 10185), // loc(callsite( builtin Add at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :182:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5738, 4095), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5739, 4096), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5740, 4097), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5741, 4098), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5742, 4099), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5743, 7420), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10186, 810), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5744, 10187), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaMix ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :172:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :232:12) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5745, 841), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5746, 856), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5747, 899), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5748, 914), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5749, 926), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5750, 972), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5751, 984), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5752, 999), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5753, 1017), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5754, 1054), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5755, 1060), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5756, 1066), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(5606, 386, 5757), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(172), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(178), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(184), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(190), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(196), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(202), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(208), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(214), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(220), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(226), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(232), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(238), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(244), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(250), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(256), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(262), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(268), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(274), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(280), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(286), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(292), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(298), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(304), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(310), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(316), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(322), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(328), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(334), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(340), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(346), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(352), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(358), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :27:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(364), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(370), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(376), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(382), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(388), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(394), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(400), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(406), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(412), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(418), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(424), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(430), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(436), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(442), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(448), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(454), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(460), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(466), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(472), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(478), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(484), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(490), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(496), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(502), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(508), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(514), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(520), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(526), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(532), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(538), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(544), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Get(550), // loc(callsite( builtin NondetReg at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :28:37) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:50) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(4034, 1084), // loc(callsite( builtin Sub at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :192:21) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(10252, 1093), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10253, 1091), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5304, 10254), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1090, 10252), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5759, 10255), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5760, 7395), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :193:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1084, 313), // loc(callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :197:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1085, 315), // loc(callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :197:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10256, 10257), // loc(callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :197:6) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10258, 1091), // loc(callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :194:17) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(7396, 10259), // loc(callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :194:17) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10189, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10190, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10191, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10192, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10193, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10194, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10195, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10196, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10197, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10198, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10199, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10200, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10201, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10202, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10203, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10188, 10261), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10276, 10262), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10277, 10263), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10278, 10264), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10279, 10265), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10280, 10266), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10281, 10267), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10282, 10268), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10283, 10269), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10284, 10270), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10285, 10271), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10286, 10272), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10287, 10273), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10288, 10274), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10289, 10275), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10205, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10206, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10207, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10208, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10209, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10210, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10211, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10212, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10213, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10214, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10215, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10216, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10217, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10218, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10219, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10204, 10291), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10306, 10292), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10307, 10293), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10308, 10294), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10309, 10295), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10310, 10296), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10311, 10297), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10312, 10298), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10313, 10299), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10314, 10300), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10315, 10301), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10316, 10302), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10317, 10303), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10318, 10304), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10319, 10305), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(9225, 10290), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(9255, 10320), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5761, 1098), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5762, 3995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5763, 4190), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(2737, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10323, 4909), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10324, 1096), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10325, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(10321, 10326), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10322, 10325), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5764, 4001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5765, 4003), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5766, 4009), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(2750, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2745, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10329, 10330), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10331, 2744), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10332, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(10328, 10333), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5767, 7478), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5768, 7480), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5769, 7481), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5770, 7482), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5771, 7484), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5772, 1377), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5773, 2799), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5774, 2805), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5775, 1387), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5776, 2815), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5777, 2821), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5778, 1396), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5779, 2827), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5780, 2833), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5781, 1406), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5782, 1413), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5783, 2839), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5784, 2845), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5785, 2851), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5786, 2857), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5787, 7486), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5788, 2772), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5789, 7488), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5790, 7490), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5791, 2780), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5792, 7492), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5793, 7494), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5794, 7496), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5795, 7498), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5796, 7500), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5797, 7502), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5798, 7504), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9285, 10327), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5799, 10335), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(9301, 10334), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5800, 10336), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :203:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10221, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10222, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10223, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10224, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10225, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10226, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10227, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10228, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10229, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10230, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10231, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10232, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10233, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10234, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10235, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10220, 10337), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10352, 10338), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10353, 10339), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10354, 10340), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10355, 10341), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10356, 10342), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10357, 10343), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10358, 10344), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10359, 10345), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10360, 10346), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10361, 10347), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10362, 10348), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10363, 10349), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10364, 10350), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10365, 10351), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10237, 7), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10238, 5), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10239, 12), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10240, 23), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10241, 24), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10242, 19), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10243, 25), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10244, 20), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10245, 26), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10246, 21), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10247, 27), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10248, 22), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10249, 28), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10250, 14), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10251, 29), // loc(callsite( builtin Mul at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:33) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10236, 10367), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10382, 10368), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10383, 10369), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10384, 10370), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10385, 10371), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10386, 10372), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10387, 10373), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10388, 10374), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10389, 10375), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10390, 10376), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10391, 10377), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10392, 10378), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10393, 10379), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10394, 10380), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10395, 10381), // loc(callsite( builtin Add at callsite( Pack ( zirgen/circuit/rv32im/v2/dsl/pack.zir :19:6) at callsite( Pack32 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :72:52) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:49) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(8369, 10366), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(8399, 10396), // loc(callsite( builtin Add at callsite( Add2 ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :30:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:28) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5801, 4150), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5802, 2755), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5803, 4853), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(2760, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2753, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10399, 10400), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10401, 2751), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10402, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(10397, 10403), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :42:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10398, 10402), // loc(callsite( builtin Add at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:34) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5804, 4861), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :34:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5805, 2765), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :35:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5806, 10156), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :36:24) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(10154, 5), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:20) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(2763, 7), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:31) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10406, 10407), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:27) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10408, 2761), // loc(callsite( builtin Add at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :37:38) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10409, 33), // loc(callsite( builtin Mul at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:23) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(10405, 10410), // loc(callsite( builtin Sub at callsite( CarryExtract ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :38:18) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :43:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5807, 7562), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5808, 593), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5809, 596), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5810, 603), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5811, 610), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5812, 617), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5813, 624), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5814, 631), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5815, 634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5816, 641), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5817, 648), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5818, 651), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5819, 654), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5820, 661), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5821, 668), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5822, 675), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5823, 1679), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5824, 546), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5825, 7564), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5826, 1634), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5827, 558), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5828, 2927), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5829, 1642), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5830, 2089), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5831, 2091), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5832, 2097), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5833, 2103), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5834, 2109), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5835, 2115), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5836, 2121), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5837, 2123), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5838, 2129), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :35:39) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(9330, 10404), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5839, 10412), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(9346, 10411), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5840, 10413), // loc(callsite( EqArr ( zirgen/circuit/rv32im/v2/dsl/arr.zir :32:11) at callsite( UnpackReg ( zirgen/circuit/rv32im/v2/dsl/pack.zir :36:14) at callsite( CarryAndExpand ( zirgen/circuit/rv32im/v2/dsl/sha2.zir :44:28) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :204:23) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5841, 4095), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :20:29) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5842, 4096), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :21:30) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5843, 4097), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :22:26) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10252, 1143), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5844, 10414), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :23:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5845, 4099), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :24:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5846, 7420), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :25:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10260, 810), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5847, 10415), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :205:19) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5848, 7331), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5849, 3893), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(832, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5850, 10416), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5851, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(817, 7408), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5852, 10417), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5853, 4828), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5854, 7336), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5855, 7507), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5856, 7510), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :219:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5857, 7340), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5858, 3992), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(859, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5859, 10418), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5860, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(844, 7413), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5861, 10419), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5862, 7347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5863, 7348), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5864, 7567), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5865, 7570), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( ShaStoreState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :220:15) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :233:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5866, 899), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5867, 914), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5868, 926), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5869, 972), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5870, 984), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5871, 999), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5872, 1054), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5873, 1060), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5874, 1066), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(5758, 389, 5875), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(4191, 4954), // loc(callsite( Reg ( :6:7) at callsite( ShaState ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :26:27) at callsite( ShaInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :34:12) at callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :234:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5877, 814), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5878, 829), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5879, 841), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5880, 856), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5881, 899), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5882, 914), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5883, 926), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5884, 972), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5885, 984), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5886, 999), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5887, 1011), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5888, 1017), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5889, 1054), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5890, 1060), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5891, 1066), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(5876, 392, 5892), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(5893, 395, 5892), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(5894, 398, 5892), // loc(callsite( Sha0 ( zirgen/circuit/rv32im/v2/dsl/inst_sha.zir :228:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :85:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(5243, 455, 5895), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(376, 53), // loc(callsite( builtin Add at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :172:40) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(371, 10420), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :172:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(935, 540), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :171:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 10422), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :21:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :171:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(972, 542), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :171:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5897, 10423), // loc(callsite( DoCycleTable ( zirgen/circuit/rv32im/v2/dsl/inst.zir :22:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :171:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5898, 10421), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :172:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1410, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(0, 10424), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1428, 1), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5900, 10425), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1829, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5901, 10426), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5902, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1411, 316), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5903, 10427), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1427, 1830), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5904, 10428), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1426, 1429), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5905, 10429), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1831, 1424), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5906, 3306), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(742, 10430), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5907, 10431), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :41:22) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5908, 1429), // loc(callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :42:14) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(1430, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5909, 10432), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5910, 1901), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5911, 541), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5912, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1431, 317), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5913, 10433), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1439, 2278), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5914, 10434), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(1440, 539), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5915, 10435), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(538, 1), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(10436, 1432), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5916, 2955), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(744, 10437), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5917, 10438), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :78:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(539, 14), // loc(callsite( builtin Mul at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:11) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(2278, 63), // loc(callsite( builtin Mul at callsite( Div ( :19:5) at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:34) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10439, 10440), // loc(callsite( builtin Add at callsite( ReadAddr ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :79:18) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :44:18) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10441, 1), // loc(callsite( builtin Sub at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :49:13) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 807), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(807, 10443), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(5918, 10444), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(5919, 10443), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1, 1137), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(1137, 10445), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(5920, 10446), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1830, 1137), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5921, 10447), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10442, 808), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :16:20) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5922, 10448), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :16:20) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5923, 4727), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :17:24) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5924, 4728), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :18:23) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5925, 4027), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5926, 4729), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5927, 3918), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5928, 3919), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5929, 3920), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5930, 4730), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5931, 3922), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5932, 3923), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5933, 3924), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5934, 3925), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5935, 3926), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5936, 3927), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5937, 3928), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5938, 3929), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5939, 3930), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5940, 3931), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(318, 1404), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5941, 10449), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntEcall ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :46:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :175:17) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5942, 591), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5943, 622), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5944, 646), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5945, 673), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5946, 552), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5947, 571), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5948, 574), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5949, 587), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5950, 745), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5951, 747), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5952, 766), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5953, 768), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5954, 761), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5955, 771), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5956, 756), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5957, 762), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5958, 732), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5959, 764), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5960, 800), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5961, 804), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5962, 817), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5963, 823), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5964, 829), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5965, 835), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5966, 841), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5967, 847), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5968, 853), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5969, 859), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5970, 896), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5971, 902), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5972, 908), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5973, 914), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5974, 920), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(5975, 926), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(5899, 377, 5976), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1411, 4732), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5903, 10450), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5978, 10428), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5979, 10429), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5980, 3306), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5981, 10431), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :118:26) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(5982, 774), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5983, 1751), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(772, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(10451, 770), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1429, 10452), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5984, 10453), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :119:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(978, 23), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :126:4) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(10454, 975), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :126:12) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(10455, 772), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :126:24) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5985, 10456), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :126:24) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5986, 983), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :128:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5987, 986), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :128:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5988, 989), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :128:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5989, 992), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :128:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5990, 995), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :128:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(987, 5), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(990, 12), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(993, 23), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:42) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2322, 10457), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:11) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(10460, 10458), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:11) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(10461, 10459), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :129:11) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5991, 998), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :131:44) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5992, 1001), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :131:44) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5993, 1004), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :131:44) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(1002, 5), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :132:46) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2483, 10463), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :132:13) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(10464, 24), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :133:4) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(10465, 10462), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :133:9) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(10466, 770), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :133:21) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(5994, 10467), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :133:21) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10462, 30), // loc(callsite( builtin Add at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:52) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(5995, 10432), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5996, 1901), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5997, 541), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5998, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(1431, 10468), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(5999, 10469), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6000, 10434), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6001, 10435), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6002, 2955), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6003, 10438), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :138:29) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1830, 5), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:59) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(10470, 5), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:68) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(2278, 10471), // loc(callsite( builtin Add at callsite( AddU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :27:21) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:38) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(908, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6004, 10473), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6005, 1007), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :45:28) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2652, 911), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:23) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10472, 10474), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(6006, 10475), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :46:10) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(539, 1005), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :48:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6007, 7353), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6008, 1010), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :51:29) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(2656, 917), // loc(callsite( builtin Add at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:23) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10476, 10477), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(6009, 10478), // loc(callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :52:9) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :139:31) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(6010, 1013), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6011, 1016), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6012, 1019), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(1011, 1014), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(10479, 1017), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10480, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(6013, 10481), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1017, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Add(1014, 10482), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10483, 978), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(6014, 10484), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :143:28) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(917, 15), // loc(callsite( builtin Sub at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:19) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(4032, 16), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:24) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(1, 4032), // loc(callsite( builtin Sub at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:41) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(10487, 15), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:49) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10486, 10488), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:31) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(10489, 917), // loc(callsite( builtin Sub at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:53) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(917, 14), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:19) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(0, 1065), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(10485, 1066), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(10492, 1064), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6016, 10493), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(1063, 10485), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6017, 10494), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6018, 3362), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6019, 1063), // loc(callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :65:34) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6020, 1053), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :81:31) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(6021, 1056), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :82:31) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(6022, 4777), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :50:23) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(923, 10490), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6023, 10495), // loc(callsite( U16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :51:8) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :85:23) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6024, 1059), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Mul(917, 1060), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::Sub(10496, 1058), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6025, 10497), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(1057, 917), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))))) +PolyExtStep::AndEqz(6026, 10498), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6027, 3385), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:10) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6028, 1057), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :87:19) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(926, 1), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6029, 10499), // loc(callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :43:14) at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :89:25) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(929, 5), // loc(callsite( builtin Mul at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:4) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10500, 1114), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:12) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(10501, 911), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6030, 10502), // loc(callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :91:21) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10491, 929), // loc(callsite( builtin Add at callsite( AddrDecomposeBits ( zirgen/circuit/rv32im/v2/dsl/u32.zir :93:30) at callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :66:29) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6031, 1114), // loc(callsite( BigIntAddr ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :67:14) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :74:22) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(591, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6032, 10504), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6033, 3958), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(629, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6034, 10505), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6035, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(594, 10503), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6036, 10506), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6037, 3957), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(615, 639), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6038, 10507), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2295, 601), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6039, 754), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(746, 10508), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6040, 10509), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6041, 758), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6042, 782), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(8324, 757), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(632, 10510), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6043, 10511), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6044, 1758), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6045, 3020), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(798, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10512, 737), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(639, 10513), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6046, 10514), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10503, 1), // loc(callsite( builtin Add at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:33) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(646, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6047, 10516), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6048, 2346), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(676, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6049, 10517), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6050, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(649, 10515), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6051, 10518), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6052, 3969), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6053, 3700), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(2921, 652), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6054, 1745), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(760, 10519), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6055, 10520), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(800, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6056, 10521), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6057, 2216), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(814, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10522, 802), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(544, 10523), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6058, 10524), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(817, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6059, 10525), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6060, 3144), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(826, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10526, 820), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(551, 10527), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6061, 10528), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10503, 7), // loc(callsite( builtin Add at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:33) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(552, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6062, 10530), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6063, 1647), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6064, 3555), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6065, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(555, 10529), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6066, 10531), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6067, 3981), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(564, 573), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6068, 10532), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3034, 556), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6069, 3339), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(767, 10533), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6070, 10534), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6071, 3893), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6072, 2223), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(869, 832), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(572, 10535), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6073, 10536), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(841, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6074, 10537), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6075, 2218), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(850, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10538, 844), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(573, 10539), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6076, 10540), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Add(10503, 6), // loc(callsite( builtin Add at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:33) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(574, 17), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6077, 10542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6078, 589), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(588, 540), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6079, 10543), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6080, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(575, 10541), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6081, 10544), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6082, 3990), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :79:22) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(578, 740), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6083, 10545), // loc(callsite( IsRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :80:23) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :90:10) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(3564, 576), // loc(callsite( builtin Sub at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6084, 3347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(769, 10546), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6085, 10547), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :91:13) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6086, 2230), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6087, 7345), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(893, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10548, 856), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(739, 10549), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6088, 10550), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :58:20) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(896, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6089, 10551), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :34:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(902, 1), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6090, 10552), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :35:31) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(905, 20), // loc(callsite( builtin Mul at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:11) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Add(10553, 899), // loc(callsite( builtin Add at callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:19) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Sub(740, 10554), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6091, 10555), // loc(callsite( SplitWord ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :36:9) at callsite( SplitU32 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :59:21) at callsite( BigIntRead ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :76:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :145:16) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndCond(6015, 1011, 6092), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(6032, 758), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6094, 782), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6095, 1758), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6096, 3020), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6097, 10521), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6098, 2216), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6099, 10525), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6100, 3144), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6101, 3893), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6102, 2223), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6103, 10537), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6104, 2218), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6105, 2230), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6106, 7345), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6107, 10551), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6108, 10552), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :95:26) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6109, 10504), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6110, 3958), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(629, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6111, 10556), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6112, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6113, 10506), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6114, 754), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6115, 10509), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6116, 10511), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6117, 10514), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6118, 10516), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6119, 2346), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(676, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6120, 10557), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6121, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6122, 10518), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6123, 1745), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6124, 10520), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6125, 10524), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6126, 10528), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6127, 10530), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6128, 1647), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(570, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6129, 10558), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6130, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6131, 10531), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6132, 3339), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6133, 10534), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6134, 10536), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6135, 10540), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6136, 10542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :69:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6137, 589), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :70:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Sub(588, 542), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6138, 10559), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :71:17) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6139, 0), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :73:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6140, 10544), // loc(callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :74:16) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :97:25) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6141, 3347), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :61:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6142, 10547), // loc(callsite( IsCycle ( zirgen/circuit/rv32im/v2/dsl/mem.zir :62:14) at callsite( IsForward ( zirgen/circuit/rv32im/v2/dsl/mem.zir :84:11) at callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :98:13) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6143, 10550), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :99:22) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6144, 10555), // loc(callsite( MemoryWrite ( zirgen/circuit/rv32im/v2/dsl/mem.zir :100:23) at callsite( BigIntWrite ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :101:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :146:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(6093, 1014, 6145), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(0, 758), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6147, 782), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6148, 1758), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6149, 3020), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6150, 10521), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6151, 2216), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6152, 10525), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6153, 3144), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6154, 3893), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6155, 2223), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6156, 10537), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6157, 2218), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6158, 2230), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6159, 7345), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6160, 10551), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6161, 10552), // loc(callsite( NondetU8Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :19:14) at callsite( BigIntWitness ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :88:29) at callsite( BigIntCheck ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :108:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :147:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::AndEqz(6162, 920), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(6163, 926), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(6164, 591), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(6165, 622), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(6166, 646), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(6167, 673), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(6168, 552), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(6169, 571), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(6170, 574), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(6171, 587), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(6172, 745), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(6173, 747), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(6174, 766), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(6175, 768), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndCond(6146, 1017, 6176), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1771, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1771, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1771, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10560, 10561), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10563, 10562), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(3793, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(3793, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(3793, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10565, 10566), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10568, 10567), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(3794, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(3794, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(3794, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10570, 10571), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10573, 10572), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(4348, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(4348, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(4348, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10575, 10576), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10578, 10577), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(4340, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(4340, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(4340, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10580, 10581), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10583, 10582), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1182, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1182, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1182, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10585, 10586), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10588, 10587), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1184, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1184, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1184, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10590, 10591), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10593, 10592), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1186, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1186, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1186, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10595, 10596), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10598, 10597), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1188, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1188, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1188, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10600, 10601), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10603, 10602), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1190, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1190, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1190, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10605, 10606), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10608, 10607), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1192, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1192, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1192, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10610, 10611), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10613, 10612), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1194, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1194, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1194, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10615, 10616), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10618, 10617), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1196, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1196, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1196, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10620, 10621), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10623, 10622), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1198, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1198, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1198, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10625, 10626), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10628, 10627), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1200, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1200, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1200, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10630, 10631), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10633, 10632), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1202, 1011), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1202, 1014), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1202, 1017), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10635, 10636), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10638, 10637), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :144:25) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(6177, 1071), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :14:13) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(975, 1072), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:4) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10640, 1070), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(6178, 10641), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :16:14) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1069, 975), // loc(callsite( builtin Mul at callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:4) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6179, 10642), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :18:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::AndEqz(6180, 2729), // loc(callsite( IsZero ( zirgen/circuit/rv32im/v2/dsl/is_zero.zir :20:17) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:20) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1069, 4740), // loc(callsite( builtin Mul at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :151:27) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 10643), // loc(callsite( builtin Sub at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :152:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(10643, 13), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :152:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10644, 318), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :152:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10645, 10646), // loc(callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :152:17) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::AndEqz(6181, 10444), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6182, 3911), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6183, 10446), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6184, 4096), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6185, 9352), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :16:20) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(975, 1143), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :17:24) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6186, 10648), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :17:24) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10464, 809), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :18:23) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6187, 10649), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :18:23) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10564, 1148), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6188, 10650), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10569, 810), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6189, 10651), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10574, 1154), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6190, 10652), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10579, 811), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6191, 10653), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10584, 1160), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6192, 10654), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10589, 1372), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6193, 10655), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10594, 1373), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6194, 10656), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10599, 1375), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6195, 10657), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10604, 1382), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6196, 10658), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10609, 1383), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6197, 10659), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10614, 1385), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6198, 10660), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10619, 1391), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6199, 10661), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10624, 1392), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6200, 10662), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10629, 1394), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6201, 10663), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10634, 1401), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6202, 10664), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10639, 1402), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6203, 10665), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(10647, 1404), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6204, 10666), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :158:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :176:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndCond(5977, 380, 6205), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(1228, 10444), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6207, 3911), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :14:28) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6208, 10446), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :19:23) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::AndEqz(6209, 3912), // loc(callsite( BitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :20:8) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :15:25) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6210, 4726), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :16:20) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6211, 4727), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :17:24) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6212, 4728), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :18:23) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6213, 4027), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6214, 4729), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6215, 3918), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6216, 3919), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6217, 3920), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6218, 4730), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6219, 3922), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6220, 3923), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6221, 3924), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6222, 3925), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6223, 3926), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6224, 3927), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6225, 3928), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6226, 3929), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6227, 3930), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6228, 3931), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Sub(13, 1404), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6229, 10667), // loc(callsite( Reg ( :6:7) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigIntInvalid ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :27:15) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :177:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::AndEqz(6230, 1410), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6231, 1428), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6232, 1430), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6233, 1900), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6234, 591), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6235, 622), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6236, 646), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6237, 673), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6238, 552), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6239, 571), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6240, 574), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6241, 587), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6242, 741), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6243, 743), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6244, 745), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6245, 747), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6246, 766), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6247, 768), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6248, 761), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6249, 771), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6250, 756), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6251, 762), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6252, 732), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6253, 764), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6254, 800), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6255, 804), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6256, 817), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6257, 823), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6258, 829), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6259, 835), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6260, 841), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6261, 847), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6262, 853), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6263, 859), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6264, 896), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6265, 902), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6266, 908), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6267, 914), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6268, 920), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6269, 926), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(6206, 383, 6270), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(6271, 386, 6270), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(6272, 389, 6270), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(6273, 392, 6270), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(6274, 395, 6270), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(6275, 398, 6270), // loc(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndCond(5896, 458, 6276), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(3810, 422), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(3810, 425), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(3810, 428), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(1285, 431), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Get(780), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :44:25) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10672, 434), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(4348, 437), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(1191, 440), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Sub(1, 1298), // loc(callsite( builtin Sub at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(2015, 1298), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(368, 10676), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10677, 10678), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10679, 380), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(221), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :28:31) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlUserECALL ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :81:29) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :200:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(10681, 383), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1771, 386), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1, 1301), // loc(callsite( builtin Sub at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Add(1300, 23), // loc(callsite( builtin Add at callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :158:14) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(10685, 10676), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :160:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10686, 1301), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10686, 10684), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10687, 10688), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10689, 395), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(10680, 10682), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(10691, 10683), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(10692, 10690), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(10693, 443), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(1188, 446), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(368, 449), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(368, 452), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(368, 455), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(368, 458), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10668, 10669), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10700, 10670), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10701, 10671), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10702, 10673), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10703, 10674), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10704, 10675), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10705, 10694), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10706, 10695), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10707, 10696), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10708, 10697), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10709, 10698), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10710, 10699), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Get(245), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( FinalizeMisc ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :24:27) at callsite( Misc0 ( zirgen/circuit/rv32im/v2/dsl/inst_misc.zir :42:16) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :74:47) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(10712, 422), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(10712, 425), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(10712, 428), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(1288, 431), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Get(783), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Div0 ( zirgen/circuit/rv32im/v2/dsl/inst_div.zir :36:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :78:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10717, 434), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Get(706), // loc(callsite( builtin NondetReg at callsite( ArgU16 ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :34:27) at callsite( NondetU16Reg ( zirgen/circuit/rv32im/v2/dsl/lookups.zir :42:24) at callsite( NormalizeU32 ( zirgen/circuit/rv32im/v2/dsl/u32.zir :50:26) at callsite( Mem0 ( zirgen/circuit/rv32im/v2/dsl/inst_mem.zir :63:26) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :79:10) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))))) +PolyExtStep::Mul(10719, 437), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(1194, 440), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Get(173), // loc(callsite( builtin NondetReg at callsite( MemoryArg ( zirgen/circuit/rv32im/v2/dsl/mem.zir :29:32) at callsite( MemoryIO ( zirgen/circuit/rv32im/v2/dsl/mem.zir :68:30) at callsite( MemoryRead ( zirgen/circuit/rv32im/v2/dsl/mem.zir :89:18) at callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :59:22) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))))) +PolyExtStep::Mul(10722, 1298), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(370, 10676), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10723, 10724), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10725, 380), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(3810, 383), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(3793, 386), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(10726, 10727), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(10729, 10728), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(10730, 443), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(1191, 446), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(370, 449), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(370, 452), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(370, 455), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(370, 458), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10713, 10714), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10737, 10715), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10738, 10716), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10739, 10718), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10740, 10720), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10741, 10721), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10742, 10731), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10743, 10732), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10744, 10733), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10745, 10734), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10746, 10735), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10747, 10736), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(422, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(425, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(428, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(431, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(434, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(437, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(440, 13), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Get(120), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :49:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(1, 10756), // loc(callsite( builtin Sub at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :32:8) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Sub(1, 10757), // loc(callsite( builtin Sub at callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :32:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(10758, 23), // loc(callsite( ControlLoadRootAndNonce ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :32:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :198:29) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10759, 377), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(10676, 13), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(1298, 10761), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10762, 380), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(383, 13), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Sub(1, 1299), // loc(callsite( builtin Sub at callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))))) +PolyExtStep::Mul(1299, 23), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10765, 5), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10766, 10767), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10768, 389), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(392, 3), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1298, 2), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :160:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10676, 3), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :160:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10771, 10772), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :160:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10773, 1301), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1298, 3), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10775, 10772), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :174:6) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10776, 10684), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10774, 10777), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10778, 395), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(10760, 10763), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(10780, 10764), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(10781, 3554), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(10782, 10769), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(10783, 10770), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(10784, 10779), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(10785, 414), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(10786, 443), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(3809, 446), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Get(166), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :41:27) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(10789, 449), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(10789, 452), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(10789, 455), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Get(251), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :20:27) at callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(10793, 458), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10749, 10750), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10795, 10751), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10796, 10752), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10797, 10753), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10798, 10754), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10799, 10755), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10800, 10787), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10801, 10788), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10802, 10790), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10803, 10791), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10804, 10792), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10805, 10794), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(374, 422), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(374, 425), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(374, 428), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(374, 431), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(374, 434), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(374, 437), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(374, 440), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(10681, 1298), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(374, 10676), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10814, 10815), // loc(callsite( ControlResume ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :57:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :199:19) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10816, 380), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(1299, 6), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(374, 10765), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10818, 10819), // loc(callsite( ControlSuspend ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :103:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :202:20) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10820, 389), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(10676, 1301), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(1298, 10684), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Add(10822, 10823), // loc(callsite( ControlTable ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :151:4) at callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :204:18) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Mul(10824, 395), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(10817, 383), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(10826, 10821), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(10827, 10825), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Add(10828, 398), // loc(callsite( Control0 ( zirgen/circuit/rv32im/v2/dsl/inst_control.zir :197:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :81:14) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Mul(10829, 443), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Get(185), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( PoseidonState ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :45:22) at callsite( Poseidon0 ( zirgen/circuit/rv32im/v2/dsl/inst_p2.zir :472:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :83:15) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))))) +PolyExtStep::Mul(10831, 449), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(10831, 452), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(374, 455), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Mul(374, 458), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10807, 10808), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10836, 10809), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10837, 10810), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10838, 10811), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10839, 10812), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10840, 10813), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10841, 10830), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10842, 446), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10843, 10832), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10844, 10833), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10845, 10834), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Add(10846, 10835), // loc(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))) +PolyExtStep::Get(135), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :91:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(10711, 10848), // loc(callsite( Reg ( :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :91:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6277, 10849), // loc(callsite( Reg ( :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :91:22) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(137), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :92:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(10748, 10850), // loc(callsite( Reg ( :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :92:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6278, 10851), // loc(callsite( Reg ( :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :92:23) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(139), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :93:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(10806, 10852), // loc(callsite( Reg ( :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :93:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6279, 10853), // loc(callsite( Reg ( :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :93:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::Get(141), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :94:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints ))))) +PolyExtStep::Sub(10847, 10854), // loc(callsite( Reg ( :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :94:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::AndEqz(6280, 10855), // loc(callsite( Reg ( :6:7) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :94:28) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :24:2) at All Constraints )))) +PolyExtStep::GetGlobal(1, 35), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 34), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(10856, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(10857, 10858), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 33), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(10859, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(10860, 10861), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 32), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(10862, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(10863, 10864), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(2013, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Get(162), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :18:23) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Mul(10867, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Mul(2010, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Mul(10789, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Mul(2015, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Mul(10722, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Mul(2027, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Mul(10831, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Get(191), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Mul(10875, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Get(197), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Mul(10877, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Get(203), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Mul(10879, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Get(209), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Mul(10881, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Get(215), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Mul(10883, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Mul(10681, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Mul(3810, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Get(233), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Mul(10887, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Get(239), // loc(callsite( builtin NondetReg at callsite( Reg ( :5:21) at callsite( BigIntState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :19:39) at callsite(callsite( BigInt0 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :174:37) at callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :86:13) at unknown)) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Mul(10889, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Mul(10712, 458), // loc(callsite(callsite( Top ( zirgen/circuit/rv32im/v2/dsl/top.zir :73:32) at unknown) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))) +PolyExtStep::Get(24), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Sub(1, 10892), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10892, 10893), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6281, 10894), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(25), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Sub(1, 10895), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10895, 10896), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6282, 10897), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(26), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Sub(1, 10898), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10898, 10899), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6283, 10900), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(27), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Sub(1, 10901), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10901, 10902), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6284, 10903), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(28), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Sub(1, 10904), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10904, 10905), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6285, 10906), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(29), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Sub(1, 10907), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10907, 10908), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6286, 10909), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(30), // loc(callsite( builtin NondetReg at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :13:20) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Sub(1, 10910), // loc(callsite( builtin Sub at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:11) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10910, 10911), // loc(callsite( builtin Mul at callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:4) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6287, 10912), // loc(callsite( AssertBit ( zirgen/circuit/rv32im/v2/dsl/bits.zir :7:20) at callsite( NondetBitReg ( zirgen/circuit/rv32im/v2/dsl/bits.zir :14:13) at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :7:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(10892, 10895), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Add(10913, 10898), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Add(10914, 10901), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Add(10915, 10904), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Add(10916, 10907), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Add(10917, 10910), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Sub(10918, 1), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))) +PolyExtStep::AndEqz(6288, 10919), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :9:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))) +PolyExtStep::Mul(10898, 7), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Mul(10901, 6), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Mul(10904, 5), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Mul(10907, 4), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Mul(10910, 3), // loc(callsite( builtin Mul at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:32) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Add(10895, 10920), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Add(10925, 10921), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Add(10926, 10922), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Add(10927, 10923), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Add(10928, 10924), // loc(callsite( builtin Add at callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:4) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Sub(10929, 10866), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))) +PolyExtStep::AndEqz(6289, 10930), // loc(callsite( OneHot ( zirgen/circuit/rv32im/v2/dsl/one_hot.zir :11:56) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :195:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))) +PolyExtStep::Get(6), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Get(4), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10931, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Add(10932, 10933), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Get(2), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10934, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Add(10935, 10936), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Get(0), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10937, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Add(10938, 10939), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Sub(10940, 58), // loc(callsite( builtin ExtSub at callsite( ExtReg ( :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(0, 10941), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Get(14), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Get(12), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10942, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Add(10943, 10944), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Get(10), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10945, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Add(10946, 10947), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Get(8), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10948, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Add(10949, 10950), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Sub(10951, 67), // loc(callsite( builtin ExtSub at callsite( ExtReg ( :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6291, 10952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Get(22), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Get(20), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10953, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Add(10954, 10955), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Get(18), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10956, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Add(10957, 10958), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Get(16), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10959, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Add(10960, 10961), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Sub(10962, 58), // loc(callsite( builtin ExtSub at callsite( ExtReg ( :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6292, 10963), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpNop ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :251:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :198:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndCond(6290, 10892, 6293), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))) +PolyExtStep::Mul(10865, 67), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :210:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10964, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :211:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10965, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :212:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10966, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :213:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10967, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :214:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10968, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :215:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10969, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :216:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10970, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :217:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10971, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :218:21) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10972, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :219:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10973, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :220:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10974, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :221:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10975, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :222:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10976, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :223:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10977, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :224:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Mul(10978, 10865), // loc(callsite( builtin ExtMul at callsite( BigIntAccumPowers ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :225:22) at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :236:38) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Add(10869, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10980, 67), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(10870, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10964, 10982), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(10871, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10965, 10984), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(10872, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10966, 10986), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(10873, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10967, 10988), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(10874, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10968, 10990), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(10876, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10969, 10992), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(10878, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10970, 10994), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(10880, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10971, 10996), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(10882, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10972, 10998), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(10884, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10973, 11000), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(10885, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10974, 11002), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(10886, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10975, 11004), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(10888, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10976, 11006), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(10890, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10977, 11008), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(10891, 58), // loc(callsite( builtin MakeExt at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:31) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10978, 11010), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :239:12) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(10981, 58), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11012, 10983), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11013, 10985), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11014, 10987), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11015, 10989), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11016, 10991), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11017, 10993), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11018, 10995), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11019, 10997), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11020, 10999), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11021, 11001), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11022, 11003), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11023, 11005), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11024, 11007), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11025, 11009), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11026, 11011), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :238:24) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(7), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(5), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(11028, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11029, 11030), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(3), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(11031, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11032, 11033), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(1), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(11034, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11035, 11036), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(15), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(13), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(11038, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11039, 11040), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(11), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(11041, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11042, 11043), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(9), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(11044, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11045, 11046), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(23), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(21), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(11048, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11049, 11050), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(19), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(11051, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11052, 11053), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(17), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(11054, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11055, 11056), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:39) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11037, 11027), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :246:28) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :260:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(11058, 10979), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :262:21) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Sub(10940, 11059), // loc(callsite( builtin ExtSub at callsite( ExtReg ( :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(0, 11060), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Sub(10951, 11047), // loc(callsite( builtin ExtSub at callsite( ExtReg ( :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6295, 11061), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Sub(10962, 11057), // loc(callsite( builtin ExtSub at callsite( ExtReg ( :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6296, 11062), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpShift ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :261:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :199:23) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndCond(6294, 10895, 6297), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))) +PolyExtStep::Sub(10951, 11058), // loc(callsite( builtin ExtSub at callsite( ExtReg ( :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpSetTerm ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :271:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :200:25) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6291, 11063), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpSetTerm ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :271:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :200:25) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6299, 11062), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpSetTerm ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :271:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :200:25) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndCond(6298, 10898, 6300), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))) +PolyExtStep::Sub(10868, 5), // loc(callsite( builtin Sub at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :280:30) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Add(11064, 58), // loc(callsite( builtin MakeExt at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :280:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Mul(11065, 11047), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:24) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Get(34), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(33), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(11067, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11068, 11069), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(32), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(11070, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11071, 11072), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Get(31), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(11073, 356), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11074, 11075), // loc(callsite( builtin NondetExtReg at callsite( ExtReg ( :12:24) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Sub(11076, 11066), // loc(callsite( builtin ExtSub at callsite( ExtReg ( :13:18) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::AndEqz(0, 11077), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :282:17) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(11076, 11058), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :286:41) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Add(11057, 11078), // loc(callsite( builtin ExtAdd at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :286:22) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::AndEqz(6302, 10941), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :283:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6303, 10952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :283:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::Sub(10962, 11079), // loc(callsite( builtin ExtSub at callsite( ExtReg ( :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :283:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6304, 11080), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpAddTotal ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :283:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :201:26) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndCond(6301, 10901, 6305), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))) +PolyExtStep::Mul(10964, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10965, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10966, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10967, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10968, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10969, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10970, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10971, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10972, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10973, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10974, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10975, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10976, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10977, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Mul(10978, 319), // loc(callsite( builtin ExtMul at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :243:12) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11081, 319), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11096, 11082), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11097, 11083), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11098, 11084), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11099, 11085), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11100, 11086), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11101, 11087), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11102, 11088), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11103, 11089), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11104, 11090), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11105, 11091), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11106, 11092), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11107, 11093), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11108, 11094), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Add(11109, 11095), // loc(callsite( builtin ExtAdd at callsite( BigIntAccumStep ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :242:22) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :292:27) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))))))))) +PolyExtStep::Sub(11027, 11110), // loc(callsite( builtin ExtSub at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :294:46) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Mul(11111, 320), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :294:39) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Add(11037, 11112), // loc(callsite( builtin ExtAdd at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :294:21) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Sub(10940, 11113), // loc(callsite( builtin ExtSub at callsite( ExtReg ( :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :293:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(0, 11114), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :293:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6307, 11061), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :293:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6308, 11062), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpCarry1 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :293:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :202:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndCond(6306, 10904, 6309), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))) +PolyExtStep::Mul(11027, 321), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :304:39) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Add(11037, 11115), // loc(callsite( builtin ExtAdd at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :304:21) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Sub(10940, 11116), // loc(callsite( builtin ExtSub at callsite( ExtReg ( :13:18) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :303:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(0, 11117), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :303:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6311, 11061), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :303:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6312, 11062), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpCarry2 ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :303:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :203:24) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndCond(6310, 10907, 6313), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))) +PolyExtStep::Sub(10964, 321), // loc(callsite( builtin ExtSub at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :313:22) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Mul(11058, 11118), // loc(callsite( builtin ExtMul at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :314:41) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::Add(11057, 11119), // loc(callsite( builtin ExtAdd at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :314:22) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::AndEqz(0, 11120), // loc(callsite( builtin EqzExt at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :315:10) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))) +PolyExtStep::AndEqz(6315, 10941), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :189:25) at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :316:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6316, 10952), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :190:25) at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :316:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndEqz(6317, 10963), // loc(callsite( builtin EqzExt at callsite( ExtReg ( :13:11) at callsite( BigIntAccumState ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :191:26) at callsite( BigIntPolyOpEqz ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :316:20) at callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :204:21) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))))))) +PolyExtStep::AndCond(6314, 10910, 6318), // loc(callsite( BigIntAccum ( zirgen/circuit/rv32im/v2/dsl/inst_bigint.zir :197:20) at callsite( Accum ( zirgen/circuit/rv32im/v2/dsl/top.zir :100:15) at callsite(unknown at callsite( zirgen/dsl/passes/GenerateAccum.cpp :554:18 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints )))))) +PolyExtStep::GetGlobal(1, 7), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 6), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11121, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11122, 11123), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 5), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11124, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11125, 11126), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 4), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11127, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11128, 11129), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 11), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 10), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11131, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11132, 11133), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 9), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11134, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11135, 11136), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 8), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11137, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11138, 11139), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 15), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 14), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11141, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11142, 11143), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 13), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11144, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11145, 11146), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 12), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11147, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11148, 11149), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 19), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 18), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11151, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11152, 11153), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 17), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11154, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11155, 11156), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 16), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11157, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11158, 11159), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 23), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 22), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11161, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11162, 11163), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 21), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11164, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11165, 11166), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 20), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11167, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11168, 11169), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 27), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 26), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11171, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11172, 11173), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 25), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11174, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11175, 11176), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 24), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11177, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11178, 11179), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 31), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 30), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11181, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11182, 11183), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 29), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11184, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11185, 11186), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 28), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11187, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11188, 11189), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :84:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(118), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(116), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11191, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11192, 11193), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(114), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11194, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11195, 11196), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(112), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11197, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11198, 11199), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :93:55 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1373), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11201, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11203, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11202, 11204), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11202, 1382), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1372, 11204), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1392), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11208, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11205, 11209), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11205, 1391), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11207, 11209), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11206, 11209), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(38), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(37), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11214, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11215, 11216), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(36), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11217, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11218, 11219), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(35), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11220, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11221, 11222), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11223, 11200), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11224, 11210), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11225, 11212), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11226, 11213), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11227, 11211), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(0, 11228), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11229, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 1427), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 1428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11231, 11232), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 1829), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11233, 11234), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 1830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11235, 11236), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11237, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11230, 11238), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11230, 1426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1401, 11238), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 1430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11231, 11242), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 1431), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11243, 11244), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 1432), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11245, 11246), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11247, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11239, 11248), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11239, 1429), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11241, 11248), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11240, 11248), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(42), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(41), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11253, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11254, 11255), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(40), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11256, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11257, 11258), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(39), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11259, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11260, 11261), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11262, 11223), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11263, 11249), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11264, 11251), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11265, 11252), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11266, 11250), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6320, 11267), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 1440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11268, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 538), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11270, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11269, 11271), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11269, 1900), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1439, 11271), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11275, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11272, 11276), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11272, 2278), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11274, 11276), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11273, 11276), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(46), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(45), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11281, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11282, 11283), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(44), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11284, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11285, 11286), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(43), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11287, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11288, 11289), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11290, 11262), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11291, 11277), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11292, 11279), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11293, 11280), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11294, 11278), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6321, 11295), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11296, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 564), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11298, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11297, 11299), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11297, 563), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(551, 11299), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 571), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11303, 11304), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11305, 11306), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 574), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11307, 11308), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11309, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11300, 11310), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11300, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11302, 11310), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11301, 11310), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(50), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(49), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11315, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11316, 11317), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(48), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11318, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11319, 11320), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(47), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11321, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11322, 11323), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11324, 11290), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11325, 11311), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11326, 11313), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11327, 11314), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11328, 11312), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6322, 11329), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 576), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11303, 11330), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 577), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11331, 11332), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 578), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11333, 11334), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11335, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11337, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11336, 11338), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11336, 587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(575, 11338), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 740), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 741), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11342, 11343), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 742), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11344, 11345), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 743), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11346, 11347), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11348, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11339, 11349), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11339, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11341, 11349), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11340, 11349), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(54), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(53), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11354, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11355, 11356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(52), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11357, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11358, 11359), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(51), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11360, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11361, 11362), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11363, 11324), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11364, 11350), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11365, 11352), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11366, 11353), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11367, 11351), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6323, 11368), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 745), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11342, 11369), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 746), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11370, 11371), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 747), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11372, 11373), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11374, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 766), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 767), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11376, 11377), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 768), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11378, 11379), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11380, 11381), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11382, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11375, 11383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11375, 760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(744, 11383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11376, 11387), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11388, 11389), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 772), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11390, 11391), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11392, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11384, 11393), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11384, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11386, 11393), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11385, 11393), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(58), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(57), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11398, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11399, 11400), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(56), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11401, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11402, 11403), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(55), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11404, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11405, 11406), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11407, 11363), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11408, 11394), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11409, 11396), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11410, 11397), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11411, 11395), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6324, 11412), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11413, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 781), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11415, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11414, 11416), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11414, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(756, 11416), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1137), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11420, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11417, 11421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11417, 807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11419, 11421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11418, 11421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(62), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(61), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11426, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11427, 11428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(60), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11429, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11430, 11431), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(59), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11432, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11433, 11434), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11435, 11407), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11436, 11422), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11437, 11424), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11438, 11425), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11439, 11423), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6325, 11440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1143), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11441, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1148), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11443, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11442, 11444), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11442, 809), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(808, 11444), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1154), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11448, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11445, 11449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11445, 810), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11447, 11449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11446, 11449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(66), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(65), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11454, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11455, 11456), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(64), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11457, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11458, 11459), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(63), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11460, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11461, 11462), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11463, 11435), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11464, 11450), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11465, 11452), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11466, 11453), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11467, 11451), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6326, 11468), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1160), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11469, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(70), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(69), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11471, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11472, 11473), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(68), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11474, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11475, 11476), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(67), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11477, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11478, 11479), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11480, 11463), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11481, 11470), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11482, 811), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6327, 11483), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(117), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(115), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11484, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11485, 11486), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(113), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11487, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11488, 11489), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(111), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11490, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11491, 11492), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :123:43 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11493, 11480), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6328, 11494), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndCond(6319, 422, 6329), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndCond(6330, 425, 6329), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndCond(6331, 428, 6329), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 3), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 2), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11495, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11496, 11497), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 1), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11498, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11499, 11500), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::GetGlobal(1, 0), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11501, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11502, 11503), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :47:44 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 594), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11505, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11276, 11506), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11276, 591), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(2278, 11506), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 556), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11510, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11507, 11511), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11507, 555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11509, 11511), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11508, 11511), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11224, 11512), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11516, 11514), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11517, 11515), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11518, 11513), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(0, 11519), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11520, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 574), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11522, 11523), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11524, 11525), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 576), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11526, 11527), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11528, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11521, 11529), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11521, 573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(571, 11529), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 578), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11522, 11533), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11534, 11535), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11536, 11537), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11538, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11530, 11539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11530, 577), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11532, 11539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11531, 11539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11263, 11540), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11544, 11542), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11545, 11543), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11546, 11541), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6333, 11547), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 740), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11548, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 742), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 743), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11550, 11551), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 744), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11552, 11553), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 745), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11554, 11555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11556, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11549, 11557), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11549, 741), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(739, 11557), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 747), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11550, 11561), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11562, 11563), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 766), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11564, 11565), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11566, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11558, 11567), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11558, 746), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11560, 11567), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11559, 11567), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11291, 11568), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11572, 11570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11573, 11571), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11574, 11569), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6334, 11575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 768), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11576, 11577), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11578, 11579), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11580, 11581), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11582, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 772), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11576, 11584), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11585, 11586), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11587, 11588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11589, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11583, 11590), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11583, 771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(767, 11590), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11591, 11416), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11591, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11593, 11416), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11592, 11416), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11325, 11594), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11598, 11596), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11599, 11597), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11600, 11595), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6335, 11601), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11602, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11603, 11421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11603, 807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(732, 11421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11604, 11442), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11604, 808), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11606, 11442), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11605, 11442), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11364, 11607), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11611, 11609), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11612, 11610), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11613, 11608), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6336, 11614), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11444, 11449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11444, 810), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(809, 11449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11615, 11470), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11615, 811), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11617, 11470), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11616, 11470), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11408, 11618), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11622, 11620), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11623, 11621), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11624, 11619), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6337, 11625), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1382), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11626, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11202, 11627), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11202, 1375), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1372, 11627), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1385), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11631, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11628, 11632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11628, 1383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11630, 11632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11629, 11632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11436, 11633), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11637, 11635), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11638, 11636), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11639, 11634), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6338, 11640), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1392), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11641, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1401), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11643, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11642, 11644), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11642, 1394), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1391, 11644), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1404), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11648, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11645, 11649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11645, 1402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11647, 11649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11646, 11649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11464, 11650), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11654, 11652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11655, 11653), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11656, 11651), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6339, 11657), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1411), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11658, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1427), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11660, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11659, 11661), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11659, 1424), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1410, 11661), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11665, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11662, 11666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11662, 1426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11664, 11666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11663, 11666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11481, 11667), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11671, 11669), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11672, 11670), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11673, 11668), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6340, 11674), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11675, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11677, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11676, 11678), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11676, 1429), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1829, 11678), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1432), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11682, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11679, 11683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11679, 1431), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11681, 11683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11680, 11683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(74), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(73), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11688, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11689, 11690), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(72), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11691, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11692, 11693), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(71), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11694, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11695, 11696), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11697, 11480), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11698, 11684), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11699, 11686), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11700, 11687), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11701, 11685), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6341, 11702), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11703, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 538), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11705, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11704, 11706), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11704, 1900), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1439, 11706), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 917), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 923), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11710, 11711), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 926), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11712, 11713), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11714, 11715), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11716, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11707, 11717), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11707, 920), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11709, 11717), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11708, 11717), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(78), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(77), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11722, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11723, 11724), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(76), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11725, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11726, 11727), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(75), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11728, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11729, 11730), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11731, 11697), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11732, 11718), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11733, 11720), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11734, 11721), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11735, 11719), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6342, 11736), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 935), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11710, 11737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 938), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11738, 11739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 972), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11740, 11741), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11742, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 978), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11744, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11743, 11745), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11743, 975), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(932, 11745), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 984), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11749, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11746, 11750), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11746, 981), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11748, 11750), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11747, 11750), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(82), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(81), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11755, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11756, 11757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(80), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11758, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11759, 11760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(79), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11761, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11762, 11763), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11764, 11731), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11765, 11751), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11766, 11753), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11767, 11754), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11768, 11752), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6343, 11769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 993), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11770, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(86), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(85), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11772, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11773, 11774), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(84), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11775, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11776, 11777), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(83), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11778, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11779, 11780), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11781, 11764), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11782, 11771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11783, 990), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6344, 11784), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11493, 11781), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6345, 11785), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndCond(6332, 431, 6346), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11786, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 563), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11788, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11787, 11789), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11787, 556), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(552, 11789), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 745), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11793, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11790, 11794), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11790, 744), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11792, 11794), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11791, 11794), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11224, 11795), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11799, 11797), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11800, 11798), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11801, 11796), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(0, 11802), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 766), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11803, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 767), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11805, 11577), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11806, 11579), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11807, 11581), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11808, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11804, 11809), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11804, 768), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(760, 11809), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11805, 11584), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11813, 11586), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11814, 11588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11815, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11810, 11816), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11810, 771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11812, 11816), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11811, 11816), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11263, 11817), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11821, 11819), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11822, 11820), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11823, 11818), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6348, 11824), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 764), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11825, 11826), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 798), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11827, 11828), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11829, 11830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11831, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11416, 11832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11416, 732), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(762, 11832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 804), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11825, 11836), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 814), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11837, 11838), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 817), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11839, 11840), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11841, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11833, 11842), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11833, 802), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11835, 11842), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11834, 11842), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11291, 11843), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11847, 11845), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11848, 11846), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11849, 11844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6349, 11850), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 823), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 826), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11851, 11852), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 829), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11853, 11854), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11855, 11856), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11857, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 838), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11851, 11859), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 841), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11860, 11861), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11862, 11863), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11864, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11858, 11865), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11858, 835), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(820, 11865), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 850), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11869, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11866, 11870), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11866, 847), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11868, 11870), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11867, 11870), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11325, 11871), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11875, 11873), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11876, 11874), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11877, 11872), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6350, 11878), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 856), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11879, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11880, 11421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11880, 807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(853, 11421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11881, 11442), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11881, 808), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11883, 11442), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11882, 11442), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11364, 11884), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11888, 11886), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11889, 11887), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11890, 11885), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6351, 11891), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6352, 11625), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1382), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11892, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11202, 11893), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1372, 11893), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1385), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11896, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11894, 11897), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11894, 1383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11895, 11897), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11629, 11897), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11436, 11898), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11902, 11900), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11903, 11901), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11904, 11899), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6353, 11905), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1401), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11906, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11209, 11907), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11209, 1394), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1391, 11907), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1404), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11911, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11908, 11912), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11908, 1402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11910, 11912), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11909, 11912), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11464, 11913), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11917, 11915), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11918, 11916), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11919, 11914), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6354, 11920), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1411), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11921, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1427), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11923, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11922, 11924), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11922, 1424), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1410, 11924), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11928, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11925, 11929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11925, 1426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11927, 11929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11926, 11929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11481, 11930), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11934, 11932), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11935, 11933), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11936, 11931), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6355, 11937), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11938, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11940, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11939, 11941), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11939, 1429), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1829, 11941), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11942, 11683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11942, 1431), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11944, 11683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11943, 11683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11698, 11945), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11949, 11947), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11950, 11948), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11951, 11946), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6356, 11952), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11953, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11707, 11954), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11707, 2278), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11709, 11954), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11708, 11954), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11732, 11955), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11959, 11957), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11960, 11958), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11961, 11956), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6357, 11962), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 594), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11963, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 608), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11965, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11964, 11966), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11964, 601), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(591, 11966), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 622), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11970, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11967, 11971), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11967, 615), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11969, 11971), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11968, 11971), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11765, 11972), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11976, 11974), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11977, 11975), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11978, 11973), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6358, 11979), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11980, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 646), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11982, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11981, 11983), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11981, 639), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(629, 11983), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11987, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11984, 11988), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11984, 649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11986, 11988), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11985, 11988), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11782, 11989), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11993, 11991), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11994, 11992), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11995, 11990), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6359, 11996), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11997, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 676), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11999, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11998, 12000), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11998, 673), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(659, 12000), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 551), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12004, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12001, 12005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12001, 544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12003, 12005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12002, 12005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(90), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(89), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12010, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12011, 12012), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(88), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12013, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12014, 12015), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(87), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12016, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12017, 12018), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12019, 11781), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12020, 12006), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12021, 12008), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12022, 12009), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12023, 12007), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6360, 12024), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 1078), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 1084), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12025, 12026), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 1087), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12027, 12028), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 1090), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12029, 12030), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12031, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 1096), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12025, 12033), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 2736), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12034, 12035), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 2737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12036, 12037), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12038, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12032, 12039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12032, 1093), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1081, 12039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 2745), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12043, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12040, 12044), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12040, 2744), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12042, 12044), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12041, 12044), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(94), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(93), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12049, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12050, 12051), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(92), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12052, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12053, 12054), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(91), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12055, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12056, 12057), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12058, 12019), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12059, 12045), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12060, 12047), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12061, 12048), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12062, 12046), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6361, 12063), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 2751), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12064, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 2761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12066, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12065, 12067), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12065, 2760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(2750, 12067), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(98), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(97), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12071, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12072, 12073), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(96), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12074, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12075, 12076), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(95), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12077, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12078, 12079), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12080, 12058), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12081, 12068), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12082, 12070), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12083, 12069), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6362, 12084), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11493, 12080), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6363, 12085), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndCond(6347, 434, 6364), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 1160), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12086, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 1373), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12088, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12087, 12089), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12087, 1372), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(811, 12089), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1429), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12093, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12090, 12094), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12090, 1830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12092, 12094), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12091, 12094), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11224, 12095), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12099, 12097), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12100, 12098), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12101, 12096), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(0, 12102), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1439), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12103, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 1440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 538), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12105, 12106), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 2278), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12107, 12108), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12109, 12110), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12111, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12104, 12112), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12104, 1900), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1432, 12112), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 594), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12105, 12116), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 601), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12117, 12118), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 608), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12119, 12120), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12121, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12113, 12122), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12113, 591), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12115, 12122), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12114, 12122), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11263, 12123), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12127, 12125), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12128, 12126), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12129, 12124), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6366, 12130), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 622), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12131, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 629), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 639), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12133, 12134), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 646), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12135, 12136), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12137, 12138), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12139, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12132, 12140), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12132, 632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(615, 12140), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 659), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12133, 12144), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12145, 12146), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 673), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12147, 12148), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12149, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12141, 12150), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12141, 652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12143, 12150), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12142, 12150), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11291, 12151), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12155, 12153), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12156, 12154), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12157, 12152), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6367, 12158), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12159, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12161, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12160, 12162), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12160, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(676, 12162), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12163, 11299), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12163, 563), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12165, 11299), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12164, 11299), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11325, 12166), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12170, 12168), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12171, 12169), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12172, 12167), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6368, 12173), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 574), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12174, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 578), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12176, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12175, 12177), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12175, 577), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(573, 12177), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12181, 12182), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 740), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12183, 12184), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 741), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12185, 12186), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12187, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12178, 12188), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12178, 588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12180, 12188), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12179, 12188), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11364, 12189), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12193, 12191), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12194, 12192), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12195, 12190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6369, 12196), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12181, 11551), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12197, 11553), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12198, 11555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12199, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 747), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12201, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12200, 12202), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12200, 746), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(742, 12202), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1137), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12206, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12203, 12207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12203, 807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12205, 12207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12204, 12207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11408, 12208), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12212, 12210), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12213, 12211), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12214, 12209), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6370, 12215), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1143), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12216, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1148), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12218, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12217, 12219), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12217, 809), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(808, 12219), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12220, 11449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12220, 810), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12222, 11449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12221, 11449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11436, 12223), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12227, 12225), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12228, 12226), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12229, 12224), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6371, 12230), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12231, 11387), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12232, 11389), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12233, 11391), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12234, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12231, 12236), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12237, 12238), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 781), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12239, 12240), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12241, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12235, 12242), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12235, 756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(761, 12242), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12243, 11603), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12243, 732), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12245, 11603), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12244, 11603), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11464, 12246), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12250, 12248), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12251, 12249), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12252, 12247), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6372, 12253), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 798), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12254, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 804), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12256, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12255, 12257), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12255, 802), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(764, 12257), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11481, 12258), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12261, 12260), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12262, 12259), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6373, 12263), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6374, 11494), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndCond(6365, 437, 6375), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12264, 12134), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12265, 12136), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12266, 12138), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12267, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12132, 12268), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12132, 629), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(615, 12268), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12264, 12144), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12272, 12146), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12273, 12148), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12274, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12269, 12275), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12269, 652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12271, 12275), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12270, 12275), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11291, 12276), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12280, 12278), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12281, 12279), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12282, 12277), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6367, 12283), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 551), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12284, 12285), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12286, 12287), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12288, 12289), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12290, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 563), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12284, 12292), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 564), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12293, 12294), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 571), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12295, 12296), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12297, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12291, 12298), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12291, 556), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(676, 12298), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12302, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12299, 12303), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12299, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12301, 12303), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12300, 12303), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11325, 12304), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12308, 12306), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12309, 12307), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12310, 12305), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6377, 12311), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 574), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12312, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 741), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12314, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12313, 12315), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12313, 740), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(573, 12315), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 744), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12319, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12316, 12320), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12316, 743), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12318, 12320), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12317, 12320), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11364, 12321), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12325, 12323), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12326, 12324), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12327, 12322), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6378, 12328), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12329, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11804, 12330), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11804, 769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(760, 12330), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12334, 11584), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12335, 11586), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12336, 11588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12337, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12331, 12338), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12331, 771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12333, 12338), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12332, 12338), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11408, 12339), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12343, 12341), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12344, 12342), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12345, 12340), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6379, 12346), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 781), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12334, 12347), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 732), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12348, 12349), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12350, 12351), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12352, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 798), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12354, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12353, 12355), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12353, 764), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(762, 12355), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12356, 12207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12356, 807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12358, 12207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12357, 12207), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11436, 12359), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12363, 12361), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12364, 12362), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12365, 12360), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6380, 12366), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1154), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12367, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12220, 12368), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12222, 12368), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12221, 12368), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11464, 12369), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12372, 12370), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12373, 12371), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12374, 12224), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6381, 12375), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12376, 11836), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12377, 11838), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12378, 11840), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12379, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 823), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12376, 12381), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 826), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12382, 12383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 829), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12384, 12385), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12386, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12380, 12387), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12380, 820), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(802, 12387), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 835), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12391, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12388, 12392), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12388, 832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12390, 12392), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12389, 12392), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11481, 12393), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12397, 12395), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12398, 12396), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12399, 12394), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6382, 12400), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 841), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12401, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 850), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12403, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12402, 12404), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12402, 847), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(838, 12404), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11698, 12405), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12408, 12407), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12409, 12406), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6383, 12410), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11493, 11697), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6384, 12411), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndCond(6376, 440, 6385), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 1078), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12412, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 1084), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12414, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12413, 12415), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12413, 1081), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1075, 12415), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 1137), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 808), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12419, 12420), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 1143), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12421, 12422), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 809), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12423, 12424), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12425, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12416, 12426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12416, 807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12418, 12426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12417, 12426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11224, 12427), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12431, 12429), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12432, 12430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12433, 12428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(0, 12434), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 810), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12419, 12435), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 1154), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12436, 12437), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 811), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12438, 12439), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12440, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 1372), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 1373), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12442, 12443), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 1375), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12444, 12445), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 1382), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12446, 12447), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12448, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12441, 12449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12441, 1160), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1148, 12449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 1385), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12442, 12453), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 1391), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12454, 12455), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 1392), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12456, 12457), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12458, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12450, 12459), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12450, 1383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12452, 12459), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12451, 12459), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11263, 12460), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12464, 12462), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12465, 12463), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12466, 12461), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6387, 12467), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 1401), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 1402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12468, 12469), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 1404), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12470, 12471), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 1410), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12472, 12473), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12474, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 1424), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12468, 12476), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 1427), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12477, 12478), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 1426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12479, 12480), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12481, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12475, 12482), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12475, 1411), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1394, 12482), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 1829), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 1830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12486, 12487), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 1429), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12488, 12489), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 1430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12490, 12491), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12492, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12483, 12493), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12483, 1428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12485, 12493), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12484, 12493), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11291, 12494), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12498, 12496), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12499, 12497), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12500, 12495), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6388, 12501), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 1432), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12486, 12502), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 1439), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12503, 12504), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 1440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12505, 12506), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12507, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 538), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 2278), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12509, 12510), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12511, 12512), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 591), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12513, 12514), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12515, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12508, 12516), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12508, 1900), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1431, 12516), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 601), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12509, 12520), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 608), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12521, 12522), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 615), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12523, 12524), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12525, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12517, 12526), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12517, 594), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12519, 12526), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12518, 12526), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11325, 12527), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12531, 12529), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12532, 12530), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12533, 12528), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6389, 12534), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12133, 12535), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 639), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12536, 12537), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 646), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12538, 12539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12540, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12133, 12542), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 659), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12543, 12544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12545, 12546), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12547, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12541, 12548), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12541, 649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(622, 12548), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 676), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12552, 12553), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 551), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12554, 12555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12556, 12557), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12558, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12549, 12559), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12549, 673), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12551, 12559), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12550, 12559), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11364, 12560), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12564, 12562), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12565, 12563), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12566, 12561), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6390, 12567), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 556), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12552, 12568), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 563), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12569, 12570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 564), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12571, 12572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12573, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12575, 11304), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12576, 11306), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12577, 11308), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12578, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12574, 12579), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12574, 571), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(555, 12579), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12575, 11330), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12583, 11332), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12584, 11334), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12585, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12580, 12586), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12580, 575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12582, 12586), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12581, 12586), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11408, 12587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12591, 12589), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12592, 12590), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12593, 12588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6391, 12594), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11338, 11549), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11338, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(587, 11549), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 742), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12598, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12595, 12599), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12595, 741), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12597, 12599), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12596, 12599), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11436, 12600), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12604, 12602), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12605, 12603), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12606, 12601), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6392, 12607), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 744), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12608, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 746), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12610, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12609, 12611), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12609, 745), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(743, 12611), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12615, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12612, 12616), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12612, 747), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12614, 12616), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12613, 12616), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11464, 12617), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12621, 12619), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12622, 12620), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12623, 12618), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6393, 12624), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 767), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12625, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12627, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12626, 12628), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12626, 768), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(766, 12628), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12632, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12629, 12633), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12629, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12631, 12633), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12630, 12633), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11481, 12634), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12638, 12636), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12639, 12637), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12640, 12635), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6394, 12641), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 772), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12642, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12644, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12643, 12645), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12643, 756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(771, 12645), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 781), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12649, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12646, 12650), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12646, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12648, 12650), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12647, 12650), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11698, 12651), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12655, 12653), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12656, 12654), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12657, 12652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6395, 12658), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12659, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12660, 12255), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12660, 764), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(732, 12255), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 802), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12664, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12661, 12665), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12661, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12663, 12665), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12662, 12665), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11732, 12666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12670, 12668), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12671, 12669), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12672, 12667), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6396, 12673), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 814), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12674, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 820), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12676, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12675, 12677), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12675, 817), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(804, 12677), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 826), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12681, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12678, 12682), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12678, 823), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12680, 12682), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12679, 12682), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11765, 12683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12687, 12685), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12688, 12686), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12689, 12684), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6397, 12690), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12691, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 838), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12693, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12692, 12694), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12692, 835), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(829, 12694), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12698, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12695, 12699), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12695, 841), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12697, 12699), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12696, 12699), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11782, 12700), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12704, 12702), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12705, 12703), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12706, 12701), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6398, 12707), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 856), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12708, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12404, 12709), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12404, 853), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(847, 12709), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 893), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12713, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12710, 12714), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12710, 859), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12712, 12714), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12711, 12714), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12020, 12715), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12719, 12717), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12720, 12718), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12721, 12716), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6399, 12722), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 899), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12723, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 905), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12725, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12724, 12726), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12724, 902), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(896, 12726), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 911), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12730, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12727, 12731), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12727, 908), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12729, 12731), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12728, 12731), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12059, 12732), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12736, 12734), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12737, 12735), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12738, 12733), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6400, 12739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 917), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12740, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 923), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12742, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12741, 12743), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12741, 920), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(914, 12743), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12747, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12744, 12748), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12744, 926), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12746, 12748), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12745, 12748), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12081, 12749), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12753, 12751), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12754, 12752), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12755, 12750), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6401, 12756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 935), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12757, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 972), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12759, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12758, 12760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12758, 938), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(932, 12760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 978), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12764, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12761, 12765), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12761, 975), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12763, 12765), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12762, 12765), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(102), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(101), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12770, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12771, 12772), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(100), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12773, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12774, 12775), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(99), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12776, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12777, 12778), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12779, 12080), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12780, 12766), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12781, 12768), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12782, 12769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12783, 12767), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6402, 12784), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 984), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12785, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 990), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12787, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12786, 12788), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12786, 987), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(981, 12788), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 996), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12792, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12789, 12793), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12789, 993), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12791, 12793), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12790, 12793), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(106), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(105), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12798, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12799, 12800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(104), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12801, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12802, 12803), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(103), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12804, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12805, 12806), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12807, 12779), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12808, 12794), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12809, 12796), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12810, 12797), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12811, 12795), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6403, 12812), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1002), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12813, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1008), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12815, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12814, 12816), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12814, 1005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(999, 12816), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1014), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12820, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12817, 12821), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12817, 1011), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12819, 12821), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12818, 12821), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(110), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(109), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12826, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12827, 12828), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(108), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12829, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12830, 12831), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Get(107), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12832, 356), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12833, 12834), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :190:50 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12835, 12807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12836, 12822), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12837, 12824), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12838, 12825), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12839, 12823), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6404, 12840), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1051), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12841, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11493, 12835), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :177:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12843, 12842), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12844, 1017), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6405, 12845), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndCond(6386, 443, 6406), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12846, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12848, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12847, 12849), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12847, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(571, 12849), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 577), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12853, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12850, 12854), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12850, 576), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12852, 12854), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12851, 12854), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11224, 12855), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12859, 12857), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12860, 12858), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12861, 12856), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(0, 12862), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12863, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12864, 12426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12864, 807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(588, 12426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12865, 12441), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12865, 1148), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12867, 12441), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12866, 12441), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11263, 12868), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12872, 12870), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12873, 12871), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12874, 12869), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6408, 12875), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12449, 12459), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12449, 1383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1160, 12459), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12876, 12475), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12876, 1394), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12878, 12475), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12877, 12475), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11291, 12879), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12883, 12881), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12884, 12882), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12885, 12880), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6409, 12886), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12482, 12493), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12482, 1428), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1411, 12493), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12887, 12508), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12887, 1431), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12889, 12508), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12888, 12508), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11325, 12890), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12894, 12892), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12895, 12893), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12896, 12891), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6410, 12897), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11271, 11276), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11271, 2278), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1900, 11276), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12898, 11506), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12898, 591), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12900, 11506), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12899, 11506), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11364, 12901), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12905, 12903), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12906, 12904), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12907, 12902), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6411, 12908), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 608), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12909, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 622), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12911, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12910, 12912), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12910, 615), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(601, 12912), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12916, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12913, 12917), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12913, 629), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12915, 12917), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12914, 12917), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11408, 12918), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12922, 12920), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12923, 12921), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12924, 12919), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6412, 12925), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 646), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12926, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12928, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12927, 12929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12927, 649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(639, 12929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12930, 11998), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12930, 659), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12932, 11998), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12931, 11998), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11436, 12933), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12937, 12935), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12938, 12936), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12939, 12934), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6413, 12940), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12000, 12005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12000, 544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(673, 12005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12944, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12941, 12945), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12941, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12943, 12945), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12942, 12945), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11464, 12946), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12950, 12948), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12951, 12949), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12952, 12947), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6414, 12953), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12692, 12402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12692, 838), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(829, 12402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11481, 12954), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12957, 12956), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12958, 12955), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6415, 12959), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6416, 11494), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndCond(6407, 446, 6417), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 1090), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12960, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 1096), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12962, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12961, 12963), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12961, 1093), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1087, 12963), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 591), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12967, 12116), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12968, 12118), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12969, 12120), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12970, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12964, 12971), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12964, 539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12966, 12971), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12965, 12971), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11224, 12972), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12976, 12974), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12977, 12975), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(12978, 12973), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(0, 12979), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 622), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12967, 12980), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 629), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12981, 12982), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12983, 12984), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12985, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 646), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12987, 12988), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12989, 12990), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 659), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12991, 12992), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12993, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12986, 12994), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12986, 639), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(615, 12994), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 673), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12987, 12998), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 676), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(12999, 13000), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13001, 13002), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13003, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12995, 13004), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12995, 666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12997, 13004), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12996, 13004), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11263, 13005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13009, 13007), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13010, 13008), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13011, 13006), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6419, 13012), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13013, 13014), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 556), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13015, 13016), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 563), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13017, 13018), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13019, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 571), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13013, 13021), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13022, 13023), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13024, 13025), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13026, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13020, 13027), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13020, 564), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(551, 13027), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 574), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13031, 13032), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 576), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13033, 13034), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 577), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13035, 13036), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13037, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13028, 13038), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13028, 573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13030, 13038), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13029, 13038), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11291, 13039), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13043, 13041), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13044, 13042), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13045, 13040), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6420, 13046), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13031, 13047), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13048, 13049), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13050, 13051), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13052, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 741), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 742), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13054, 13055), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 743), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13056, 13057), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 744), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13058, 13059), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13060, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13053, 13061), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13053, 740), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(578, 13061), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 746), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13054, 13065), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 747), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13066, 13067), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13068, 13069), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13070, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13062, 13071), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13062, 745), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13064, 13071), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13063, 13071), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11325, 13072), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13076, 13074), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13077, 13075), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13078, 13073), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6421, 13079), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 768), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11805, 13080), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 769), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13081, 13082), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 761), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13083, 13084), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13085, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(11805, 13087), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 772), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13088, 13089), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13090, 13091), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13092, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13086, 13093), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13086, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(766, 13093), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13097, 12347), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13098, 12349), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13099, 12351), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13100, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13094, 13101), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13094, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13096, 13101), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13095, 13101), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11364, 13102), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13106, 13104), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13107, 13105), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13108, 13103), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6422, 13109), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 798), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13097, 13110), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13111, 13112), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 802), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13113, 13114), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13115, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 814), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 817), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13117, 13118), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 820), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13119, 13120), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 823), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13121, 13122), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13123, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13116, 13124), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13116, 804), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(764, 13124), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 829), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13117, 13128), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13129, 13130), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 835), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13131, 13132), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13133, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13125, 13134), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13125, 826), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13127, 13134), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13126, 13134), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11408, 13135), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13139, 13137), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13140, 13138), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13141, 13136), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6423, 13142), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 841), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13143, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 847), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13145, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13144, 13146), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13144, 844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(838, 13146), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 853), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13150, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13147, 13151), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13147, 850), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13149, 13151), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13148, 13151), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11436, 13152), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13156, 13154), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13157, 13155), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13158, 13153), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6424, 13159), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 859), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13160, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 896), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13162, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13161, 13163), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13161, 893), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(856, 13163), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 902), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13167, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13164, 13168), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13164, 899), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13166, 13168), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13165, 13168), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11464, 13169), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13173, 13171), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13174, 13172), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13175, 13170), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6425, 13176), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 908), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13177, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 914), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13179, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13178, 13180), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13178, 911), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(905, 13180), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 629), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13184, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13181, 13185), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13181, 917), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13183, 13185), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13182, 13185), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11481, 13186), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13190, 13188), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13191, 13189), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13192, 13187), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6426, 13193), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 926), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13194, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12917, 13195), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12917, 923), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(920, 13195), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 676), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13199, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13196, 13200), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13196, 929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13198, 13200), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13197, 13200), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11698, 13201), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13205, 13203), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13206, 13204), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13207, 13202), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6427, 13208), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13209, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 938), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13211, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13210, 13212), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13210, 935), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(932, 13212), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13213, 11521), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13213, 972), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13215, 11521), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13214, 11521), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11732, 13216), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13220, 13218), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13221, 13219), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13222, 13217), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6428, 13223), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13224, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 981), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13226, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13225, 13227), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13225, 978), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(975, 13227), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13231, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13228, 13232), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13228, 984), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13230, 13232), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13229, 13232), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11765, 13233), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13237, 13235), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13238, 13236), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13239, 13234), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6429, 13240), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12864, 11771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12864, 990), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(987, 11771), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 747), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13244, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13241, 13245), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13241, 996), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13243, 13245), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13242, 13245), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11782, 13246), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13250, 13248), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13251, 13249), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13252, 13247), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6430, 13253), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 760), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13254, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13256, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13255, 13257), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13255, 1002), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(999, 13257), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13258, 12643), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13258, 1008), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13260, 12643), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13259, 12643), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12020, 13261), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13265, 13263), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13266, 13264), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13267, 13262), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6431, 13268), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13269, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1017), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13271, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13270, 13272), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13270, 1014), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1011, 13272), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13276, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13273, 13277), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13273, 1051), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13275, 13277), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13274, 13277), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12059, 13278), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13282, 13280), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13283, 13281), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13284, 13279), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6432, 13285), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1060), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13286, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12665, 13287), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12665, 1057), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1054, 13287), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13288, 12692), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13288, 1063), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13290, 12692), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13289, 12692), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12081, 13291), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13295, 13293), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13296, 13294), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13297, 13292), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6433, 13298), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 835), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13299, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 1072), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13301, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13300, 13302), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13300, 1069), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1066, 13302), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1078), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13306, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13303, 13307), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13303, 1075), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13305, 13307), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13304, 13307), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12780, 13308), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13312, 13310), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13313, 13311), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13314, 13309), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6434, 13315), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 1084), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13316, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12808, 13317), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13318, 1081), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6435, 13319), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11493, 12807), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6436, 13320), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndCond(6418, 449, 6437), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 591), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13321, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 601), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13323, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13322, 13324), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13322, 594), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(539, 13324), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11224, 13325), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13328, 13327), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13329, 13326), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(0, 13330), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11493, 11223), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6439, 13331), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndCond(6438, 452, 6440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 1075), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13332, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 1081), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13334, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13333, 13335), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13333, 1078), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1072, 13335), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 817), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 820), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13339, 13340), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 823), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13341, 13342), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 826), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13343, 13344), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13345, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13336, 13346), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13336, 814), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13338, 13346), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13337, 13346), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11224, 13347), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13351, 13349), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13352, 13350), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13353, 13348), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(0, 13354), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13339, 13355), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 835), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13356, 13357), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 838), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13358, 13359), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13360, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 847), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13362, 13363), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 850), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13364, 13365), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 853), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13366, 13367), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13368, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13361, 13369), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13361, 841), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(829, 13369), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 859), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13362, 13373), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 893), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13374, 13375), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 896), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13376, 13377), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13378, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13370, 13379), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13370, 856), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13372, 13379), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13371, 13379), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11263, 13380), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13384, 13382), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13385, 13383), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13386, 13381), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6442, 13387), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 902), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 905), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13388, 13389), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 908), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13390, 13391), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 911), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13392, 13393), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13394, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 917), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13388, 13396), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 920), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13397, 13398), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 923), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13399, 13400), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13401, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13395, 13402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13395, 914), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(899, 13402), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 932), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13406, 13407), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 935), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13408, 13409), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 938), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13410, 13411), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13412, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13403, 13413), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13403, 926), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13405, 13413), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13404, 13413), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11291, 13414), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13418, 13416), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13419, 13417), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13420, 13415), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6443, 13421), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 975), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13406, 13422), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 978), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13423, 13424), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 981), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13425, 13426), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13427, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 987), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 990), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13429, 13430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 993), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13431, 13432), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 996), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13433, 13434), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13435, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13428, 13436), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13428, 984), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(972, 13436), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 1002), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13429, 13440), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 1005), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13441, 13442), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 1008), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13443, 13444), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13445, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13437, 13446), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13437, 999), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13439, 13446), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13438, 13446), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11325, 13447), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13451, 13449), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13452, 13450), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13453, 13448), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6444, 13454), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 1014), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13455, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 1051), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13457, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13456, 13458), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13456, 1017), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1011, 13458), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 1057), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13462, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13459, 13463), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13459, 1054), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13461, 13463), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13460, 13463), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11364, 13464), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13468, 13466), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13469, 13467), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13470, 13465), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6445, 13471), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 1063), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13472, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 1069), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13474, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13473, 13475), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13473, 1066), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1060, 13475), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11408, 13476), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13479, 13478), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13480, 13477), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6446, 13481), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11493, 11407), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6447, 13482), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndCond(6441, 455, 6448), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 935), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13483, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11180, 972), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13485, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13484, 13486), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13484, 938), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(932, 13486), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 1411), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13490, 12476), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13491, 12478), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13492, 12480), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13493, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13487, 13494), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13487, 1410), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13489, 13494), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13488, 13494), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11224, 13495), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13499, 13497), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13500, 13498), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13501, 13496), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(0, 13502), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 1829), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13490, 13503), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 1830), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13504, 13505), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 1429), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13506, 13507), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13508, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 1431), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13510, 12502), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13511, 12504), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13512, 12506), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13513, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13509, 13514), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13509, 1430), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(1428, 13514), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13510, 12106), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13518, 12108), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13519, 12110), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13520, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13515, 13521), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13515, 1900), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13517, 13521), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13516, 13521), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11263, 13522), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13526, 13524), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13527, 13525), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13528, 13523), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6450, 13529), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 594), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13530, 12520), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13531, 12522), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13532, 12524), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13533, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 629), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13530, 13535), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13536, 13537), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 639), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13538, 13539), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13540, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13534, 13541), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13534, 622), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(591, 13541), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13545, 12542), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13546, 12544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13547, 12546), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13548, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13542, 13549), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13542, 646), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13544, 13549), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13543, 13549), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11291, 13550), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13554, 13552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13555, 13553), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13556, 13551), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6451, 13557), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 676), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13545, 13558), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 544), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13559, 13560), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 551), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13561, 13562), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13563, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 555), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13565, 12568), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13566, 12570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13567, 12572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13568, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13564, 13569), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13564, 552), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(673, 13569), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 570), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13565, 13573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 572), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13574, 13575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 573), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13576, 13577), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13578, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13570, 13579), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13570, 571), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13572, 13579), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13571, 13579), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11325, 13580), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13584, 13582), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13585, 13583), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13586, 13581), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6452, 13587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11140, 575), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13588, 11330), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13589, 11332), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13590, 11334), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13591, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11150, 588), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13588, 13593), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11160, 739), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13594, 13595), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11170, 740), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13596, 13597), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :157:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13598, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13592, 13599), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13592, 587), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(574, 13599), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13600, 12599), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13600, 741), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13602, 12599), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13601, 12599), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11364, 13603), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13607, 13605), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13608, 13606), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13609, 13604), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6453, 13610), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11408, 12617), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13611, 12619), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13612, 12620), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13613, 12618), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6454, 13614), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 770), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13615, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12629, 13616), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12631, 13616), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12630, 13616), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11436, 13617), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13620, 13618), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13621, 13619), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13622, 12635), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6455, 13623), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 772), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13624, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 757), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13626, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13625, 13627), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13625, 756), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(771, 13627), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 781), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13631, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13628, 13632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13628, 762), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13630, 13632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13629, 13632), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11464, 13633), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13637, 13635), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13638, 13636), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13639, 13634), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6456, 13640), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 737), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13641, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 798), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13643, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13642, 13644), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13642, 764), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(732, 13644), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 802), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13648, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13645, 13649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13645, 800), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13647, 13649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13646, 13649), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11481, 13650), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13654, 13652), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13655, 13653), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13656, 13651), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6457, 13657), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 814), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13658, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 820), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13660, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13659, 13661), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13659, 817), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(804, 13661), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 826), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13665, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13662, 13666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13662, 823), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13664, 13666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13663, 13666), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11698, 13667), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13671, 13669), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13672, 13670), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13673, 13668), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6458, 13674), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 832), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13675, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 838), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13677, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13676, 13678), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13676, 835), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(829, 13678), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 844), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13682, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13679, 13683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13679, 841), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13681, 13683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13680, 13683), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11732, 13684), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13688, 13686), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13689, 13687), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13690, 13685), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6459, 13691), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 850), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13692, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 856), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13694, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13693, 13695), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13693, 853), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(847, 13695), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11504, 893), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13699, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13696, 13700), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13696, 859), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13698, 13700), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13697, 13700), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11765, 13701), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13705, 13703), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13706, 13704), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13707, 13702), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6460, 13708), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 911), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13709, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12727, 13710), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12729, 13710), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12728, 13710), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11782, 13711), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13714, 13712), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13715, 13713), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13716, 12733), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6461, 13717), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 917), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13718, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 923), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13720, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13719, 13721), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13719, 920), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(914, 13721), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(11130, 929), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :146:36 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Add(13725, 11190), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :238:47 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13722, 13726), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :217:45 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13722, 926), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :219:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13724, 13726), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(13723, 13726), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :223:37 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Mul(12020, 13727), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :178:46 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13731, 13729), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13732, 13730), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(13733, 13728), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :180:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6462, 13734), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :182:33 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::Sub(11493, 12019), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :124:42 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndEqz(6463, 13735), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :125:35 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +PolyExtStep::AndCond(6449, 458, 6464), // loc(callsite( zirgen/dsl/passes/GenerateAccum.cpp :589:9 at callsite( zirgen/dsl/passes/GenerateAccum.cpp :525:9 at All Constraints ))) +], + ret: 6465, +}; + +impl PolyExt for CircuitImpl { + fn poly_ext( + &self, + mix: &BabyBearExtElem, + u: &[BabyBearExtElem], + args: &[&[BabyBearElem]], + ) -> MixState { + DEF.step::(mix, u, args) + } +} diff --git a/src/circuit/v3_0/recursive/control_id.rs b/src/circuit/v3_0/recursive/control_id.rs new file mode 100644 index 0000000..0ca2f3e --- /dev/null +++ b/src/circuit/v3_0/recursive/control_id.rs @@ -0,0 +1,327 @@ +// Copyright Copyright 2024, Horizen Labs, Inc. +// Copyright Copyright 2025 RISC Zero, Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +use risc0_zkp_v3::core::digest::Digest; +use risc0_zkp_v3::digest; + +/// Smallest cycle limit, as a power of two (po2), supported as a lift program. +pub const MIN_LIFT_PO2: usize = 14; + +/// Control IDs allowed in the default set of recursion programs. Includes control IDs for the base +/// set of recursion programs, and each power-of-two of the rv32im circuit, using Poseidon2. +pub const ALLOWED_CONTROL_IDS: &[Digest] = &[ + digest!("0d79bc33b4760b4783cbb96fdc87724c7e0c463eb0ba1b2705d39f43c698bd2d"), // recursion identity.zkr + digest!("7a8f24092c34ed3eb81b3d0a0b796c588c615d3488ef9e61c21dbd1e4b83ea6e"), // recursion join.zkr + digest!("96cdf605f755f175a5661812810f2d491507c05f2ea4a83e4c3cad693d26651e"), // recursion join_povw.zkr + digest!("f74a894ff593584f65847630ead1a23af78c5f5fed2b61090866e01fa5767f12"), // recursion join_unwrap_povw.zkr + digest!("411fa636f2d364648f035174d3778d6340d9ae1dd648fc35657c173f01e27e5f"), // recursion lift_rv32im_v2_14.zkr + digest!("1ca3ca03030719064ba61b3125bdd326fc57f74e799ef860bdea6f3227381e16"), // recursion lift_rv32im_v2_15.zkr + digest!("c32b3627d2b3d60c64adf523a98bd16c0ff607471f3d6630d1f26d5e9406d841"), // recursion lift_rv32im_v2_16.zkr + digest!("c9b08054994f542a6310b00d9b6fc6528ed7bb6f4ca5476a686847127cdfdc5b"), // recursion lift_rv32im_v2_17.zkr + digest!("e7934a23ddce1423b425cf32aa23be29f48cd40e0b6ff9376dce6f3bf9d0bc35"), // recursion lift_rv32im_v2_18.zkr + digest!("8c2fdd36ede09a4b9d316a43c51f1160cbd8876659c5f35810c3a119c60d3843"), // recursion lift_rv32im_v2_19.zkr + digest!("34530b42028fb631c90e1226bb0e750d4b9b593840d45216f75dca449dac7734"), // recursion lift_rv32im_v2_20.zkr + digest!("fd84d83092a1e1244d423a26d89c892ab098b467c6d82229912deb26e37d2562"), // recursion lift_rv32im_v2_21.zkr + digest!("9d9dbf33535ab11f52a93839dfd23b352b7626009e81d9459fd04e488898ec6a"), // recursion lift_rv32im_v2_22.zkr + digest!("c6972402cc81bc6c1122e65aa7cf463f3ac3f477c7dd860582ca7420fc7b8b02"), // recursion lift_rv32im_v2_povw_14.zkr + digest!("2f6ea1104bdd5955faa135611e8f803e7b4461703b937e704da70955ec115467"), // recursion lift_rv32im_v2_povw_15.zkr + digest!("a7b55654228123448cd67c400d9bf80b4e54eb3997ee92103e900903b6578862"), // recursion lift_rv32im_v2_povw_16.zkr + digest!("2adab2445391035b21f255606a1ba060a7d5a64db5cdf13d9fda7f22a2853270"), // recursion lift_rv32im_v2_povw_17.zkr + digest!("58b27422240db834c08b8e6c12000c093efce8613263f05825c380009c41da48"), // recursion lift_rv32im_v2_povw_18.zkr + digest!("26c84437d3e26875b259880d0f29da47ed5ca869133637701d33fb15a83dce4b"), // recursion lift_rv32im_v2_povw_19.zkr + digest!("177fde1441dc735dbd6a58245d82b2036623ac41547dc345f1fd7c486ac51462"), // recursion lift_rv32im_v2_povw_20.zkr + digest!("eac3fb487080a62e6ff85d331dd72a4706e50e55c9cb842dea48d71e3e119a04"), // recursion lift_rv32im_v2_povw_21.zkr + digest!("0344cd54d62d2a1b6538b674d5aa141250ff4c5be08c6e3d16cb5e1de632252d"), // recursion lift_rv32im_v2_povw_22.zkr + digest!("53a7b23d07f99e5d5685e85874f5181e8486aa267a0ae607ffe9ba47c8bdda4a"), // recursion resolve.zkr + digest!("20ac6e29b1806a143b508414140e2e15e461f93e04e3830af39cca362b8f005d"), // recursion resolve_povw.zkr + digest!("ba1d7275d5840e4f998e2c5120810c0eb197e90219696e2a64dec7662aa3cb06"), // recursion resolve_unwrap_povw.zkr + digest!("7771415b778fea1923440e2eb22c4a1e1d7ada2d42cbe03d13402743c0988a31"), // recursion union.zkr + digest!("1688f04cca489638862dba455c1d5c561513f975c885a3491f0fe12df761c847"), // recursion unwrap_povw.zkr +]; + +/// Root of the Merkle tree constructed from [ALLOWED_CONTROL_IDS], using Poseidon2. +pub const ALLOWED_CONTROL_ROOT: Digest = + digest!("a54dc85ac99f851c92d7c96d7318af41dbe7c0194edfcc37eb4d422a998c1f56"); + +/// Control ID for the identity recursion programs (ZKR), using Poseidon over the BN254 scalar field. +pub const BN254_IDENTITY_CONTROL_ID: Digest = + digest!("c07a65145c3cb48b6101962ea607a4dd93c753bb26975cb47feb00d3666e4404"); + +/// Control IDs for included recursion programs (ZKRs), using Poseidon2 over BabyBear. +pub const POSEIDON2_CONTROL_IDS: [(&str, Digest); 32] = [ + ( + "identity.zkr", + digest!("0d79bc33b4760b4783cbb96fdc87724c7e0c463eb0ba1b2705d39f43c698bd2d"), + ), + ( + "join.zkr", + digest!("7a8f24092c34ed3eb81b3d0a0b796c588c615d3488ef9e61c21dbd1e4b83ea6e"), + ), + ( + "join_povw.zkr", + digest!("96cdf605f755f175a5661812810f2d491507c05f2ea4a83e4c3cad693d26651e"), + ), + ( + "join_unwrap_povw.zkr", + digest!("f74a894ff593584f65847630ead1a23af78c5f5fed2b61090866e01fa5767f12"), + ), + ( + "lift_rv32im_v2_14.zkr", + digest!("411fa636f2d364648f035174d3778d6340d9ae1dd648fc35657c173f01e27e5f"), + ), + ( + "lift_rv32im_v2_15.zkr", + digest!("1ca3ca03030719064ba61b3125bdd326fc57f74e799ef860bdea6f3227381e16"), + ), + ( + "lift_rv32im_v2_16.zkr", + digest!("c32b3627d2b3d60c64adf523a98bd16c0ff607471f3d6630d1f26d5e9406d841"), + ), + ( + "lift_rv32im_v2_17.zkr", + digest!("c9b08054994f542a6310b00d9b6fc6528ed7bb6f4ca5476a686847127cdfdc5b"), + ), + ( + "lift_rv32im_v2_18.zkr", + digest!("e7934a23ddce1423b425cf32aa23be29f48cd40e0b6ff9376dce6f3bf9d0bc35"), + ), + ( + "lift_rv32im_v2_19.zkr", + digest!("8c2fdd36ede09a4b9d316a43c51f1160cbd8876659c5f35810c3a119c60d3843"), + ), + ( + "lift_rv32im_v2_20.zkr", + digest!("34530b42028fb631c90e1226bb0e750d4b9b593840d45216f75dca449dac7734"), + ), + ( + "lift_rv32im_v2_21.zkr", + digest!("fd84d83092a1e1244d423a26d89c892ab098b467c6d82229912deb26e37d2562"), + ), + ( + "lift_rv32im_v2_22.zkr", + digest!("9d9dbf33535ab11f52a93839dfd23b352b7626009e81d9459fd04e488898ec6a"), + ), + ( + "lift_rv32im_v2_23.zkr", + digest!("817a4b13453eac5a4e67ea1bdcc0677681faa94e386bdd4b510429363685f067"), + ), + ( + "lift_rv32im_v2_24.zkr", + digest!("6c4f9e2ae5d3d5375956f608a54112418333ad2008052b059f3b500ba8df9d63"), + ), + ( + "lift_rv32im_v2_povw_14.zkr", + digest!("c6972402cc81bc6c1122e65aa7cf463f3ac3f477c7dd860582ca7420fc7b8b02"), + ), + ( + "lift_rv32im_v2_povw_15.zkr", + digest!("2f6ea1104bdd5955faa135611e8f803e7b4461703b937e704da70955ec115467"), + ), + ( + "lift_rv32im_v2_povw_16.zkr", + digest!("a7b55654228123448cd67c400d9bf80b4e54eb3997ee92103e900903b6578862"), + ), + ( + "lift_rv32im_v2_povw_17.zkr", + digest!("2adab2445391035b21f255606a1ba060a7d5a64db5cdf13d9fda7f22a2853270"), + ), + ( + "lift_rv32im_v2_povw_18.zkr", + digest!("58b27422240db834c08b8e6c12000c093efce8613263f05825c380009c41da48"), + ), + ( + "lift_rv32im_v2_povw_19.zkr", + digest!("26c84437d3e26875b259880d0f29da47ed5ca869133637701d33fb15a83dce4b"), + ), + ( + "lift_rv32im_v2_povw_20.zkr", + digest!("177fde1441dc735dbd6a58245d82b2036623ac41547dc345f1fd7c486ac51462"), + ), + ( + "lift_rv32im_v2_povw_21.zkr", + digest!("eac3fb487080a62e6ff85d331dd72a4706e50e55c9cb842dea48d71e3e119a04"), + ), + ( + "lift_rv32im_v2_povw_22.zkr", + digest!("0344cd54d62d2a1b6538b674d5aa141250ff4c5be08c6e3d16cb5e1de632252d"), + ), + ( + "lift_rv32im_v2_povw_23.zkr", + digest!("bd19f156d23811155241e10f7d03ab483949e5039a512d75b7e3da40fcb5490e"), + ), + ( + "lift_rv32im_v2_povw_24.zkr", + digest!("7898f8140d13c04781c2073b2b28541dfa40f23fa824c30228b80b2601d7114a"), + ), + ( + "resolve.zkr", + digest!("53a7b23d07f99e5d5685e85874f5181e8486aa267a0ae607ffe9ba47c8bdda4a"), + ), + ( + "resolve_povw.zkr", + digest!("20ac6e29b1806a143b508414140e2e15e461f93e04e3830af39cca362b8f005d"), + ), + ( + "resolve_unwrap_povw.zkr", + digest!("ba1d7275d5840e4f998e2c5120810c0eb197e90219696e2a64dec7662aa3cb06"), + ), + ( + "test_recursion_circuit.zkr", + digest!("6d55102aa73086602f7039412200124bdec91f0c497c606f9aa09040403e030b"), + ), + ( + "union.zkr", + digest!("7771415b778fea1923440e2eb22c4a1e1d7ada2d42cbe03d13402743c0988a31"), + ), + ( + "unwrap_povw.zkr", + digest!("1688f04cca489638862dba455c1d5c561513f975c885a3491f0fe12df761c847"), + ), +]; + +/// Control IDs for included recursion programs (ZKRs), using SHA-256. +pub const SHA256_CONTROL_IDS: [(&str, Digest); 32] = [ + ( + "identity.zkr", + digest!("d7ecd18c7d06fc468166147cf20869aa10f32e097a0c166146a5a62dd2d975ea"), + ), + ( + "join.zkr", + digest!("dc44002689aa7852410ad1c840388d66b8b9a2f6d0c4fb6b3ac6ec2ea17d9855"), + ), + ( + "join_povw.zkr", + digest!("9e97b7ba610dc00ec2628d53274c303eb0d78e6e5c33ef118cf60a5135efa97f"), + ), + ( + "join_unwrap_povw.zkr", + digest!("8cae4f60f8b44780351ec5740118fcc348d8fa0d029f07d2c77a3f9239165319"), + ), + ( + "lift_rv32im_v2_14.zkr", + digest!("52d814fea0ff156f2b8b34f7c47d7bfb5c09c527d7907a8664bd95f104633852"), + ), + ( + "lift_rv32im_v2_15.zkr", + digest!("ca0c7e2ffb7cc226f544dfbebd420a898ba1ec42cb6da27c1446f7dafc41c534"), + ), + ( + "lift_rv32im_v2_16.zkr", + digest!("b20d5da6ac0f4bface80e6f902cd0f77e3f5e3a8174379595ac74d6f052acae5"), + ), + ( + "lift_rv32im_v2_17.zkr", + digest!("7e81c18847d0693f69eaffe6a43e3883f81f57ecea2b740a682870d9d810faaf"), + ), + ( + "lift_rv32im_v2_18.zkr", + digest!("b8f1d3b165d1a9eab7c6c37d3e9583b9907af5ef847c90ca2e4d18c689897a95"), + ), + ( + "lift_rv32im_v2_19.zkr", + digest!("9385cfb4c04bb8a7afca8b2d1bf083cb5d7d975d8a47b92f02710a81cd49d2cb"), + ), + ( + "lift_rv32im_v2_20.zkr", + digest!("771619915ed607e737578315c855ba70c322ac02cfdd01da0e4d1bed4c51cb0d"), + ), + ( + "lift_rv32im_v2_21.zkr", + digest!("c662b29a03a3475a3dae43ef30b0e4234a9e00d99b49d1f61d8ae91c7957a148"), + ), + ( + "lift_rv32im_v2_22.zkr", + digest!("5d68f47ef1f5ab04588c370a79d1216eeec96c5d75fcf73af3a2a59b76bd2879"), + ), + ( + "lift_rv32im_v2_23.zkr", + digest!("bb5ced4a8480a2347cfa43125a9c5b165e2ff3bc99b42927d43f49d23d8b3208"), + ), + ( + "lift_rv32im_v2_24.zkr", + digest!("3e6ac6e4ca5d76858edae7a4f080a2a34649ea6ce0870d0d77ec18b7299b1dbd"), + ), + ( + "lift_rv32im_v2_povw_14.zkr", + digest!("e5e64a61ebe66ad5361417b2c5b879f555567b8b27f24263b285fd2a44e9d879"), + ), + ( + "lift_rv32im_v2_povw_15.zkr", + digest!("058a1436c07037e4b02856b51a09a4b8b81f0653dacde6efbead574d2ccc877c"), + ), + ( + "lift_rv32im_v2_povw_16.zkr", + digest!("39ac8603e8fdd8b1571546cf21afc4fecbd763abdc83c6f556f865f1639cf793"), + ), + ( + "lift_rv32im_v2_povw_17.zkr", + digest!("2f83f136dff007043e04c793946ec7b1d6fc85aa80fd56b3cddfd41e5b5e80cd"), + ), + ( + "lift_rv32im_v2_povw_18.zkr", + digest!("8fc29c56e18387c39b45a6ad5efe70c4b05f4755dafe79ceb503f00d99711171"), + ), + ( + "lift_rv32im_v2_povw_19.zkr", + digest!("a6e06036f3b4c84aac96b2c43b18fba7328a0f1c6d0a1a92f6601ceb7f136a23"), + ), + ( + "lift_rv32im_v2_povw_20.zkr", + digest!("97a1d6b0d9c7cbc754a24b76a068c43a3dd0a194708e88b5ba061617c3bff7b4"), + ), + ( + "lift_rv32im_v2_povw_21.zkr", + digest!("268d25ef3fa8fc664c1a9629870be677b66e537d8b56fceddf4e55cea3ec8167"), + ), + ( + "lift_rv32im_v2_povw_22.zkr", + digest!("e836234e551bf0404665c68a6489527e0f38d77e058a702911298912d4fdfee0"), + ), + ( + "lift_rv32im_v2_povw_23.zkr", + digest!("5544f519c4d65a1546475b23860e26ff7299059e24cacb3b10854cc2872e7736"), + ), + ( + "lift_rv32im_v2_povw_24.zkr", + digest!("ae43f6e6b2565ef910c9736eb616a1d045ff049571c37ac728ad70d8cca2d66d"), + ), + ( + "resolve.zkr", + digest!("ecc34946284eb02d1e119ef0878ae65ba5e855d6e0b5db4e462a694007b2a0f4"), + ), + ( + "resolve_povw.zkr", + digest!("51fe537675d705e759c0cb0862f0cb7c5d70ce3dc483efc3cb1646c2b6f0cba3"), + ), + ( + "resolve_unwrap_povw.zkr", + digest!("1332cc7a1cb90467d849db4ebc4fcc201f81fe0a2ab06d6a398d76b7dd8aa694"), + ), + ( + "test_recursion_circuit.zkr", + digest!("3c7b9195e051f01d9dc21d96a1dd26c7035bc225511a715cf8c7ba83f8df7687"), + ), + ( + "union.zkr", + digest!("44bfa51c5030508d7eddc1b1489145a6e519842f7283098a17f13fe9113497dc"), + ), + ( + "unwrap_povw.zkr", + digest!("3b5de70ddecc2fabcd3b9b9150ff64e7fc084ecb80f97cac2f9ee11e326087d1"), + ), +]; diff --git a/src/circuit/v3_0/recursive/poly_ext.rs b/src/circuit/v3_0/recursive/poly_ext.rs new file mode 100644 index 0000000..5cc4e7c --- /dev/null +++ b/src/circuit/v3_0/recursive/poly_ext.rs @@ -0,0 +1,12403 @@ +// Copyright Copyright 2024, Horizen Labs, Inc. +// Copyright Copyright 2024 RISC Zero, Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +// This code is automatically generated + +use risc0_zkp_v3::{ + adapter::{MixState, PolyExt, PolyExtStep, PolyExtStepDef}, + field::baby_bear::{BabyBear, BabyBearElem, BabyBearExtElem}, +}; + +use super::CircuitImpl; + +#[allow(missing_docs)] +#[rustfmt::skip] +pub const DEF: PolyExtStepDef = PolyExtStepDef { + block: &[PolyExtStep::Const(0), // loc(unknown) +PolyExtStep::Const(1), // loc(unknown) +PolyExtStep::Const(2), // loc(unknown) +PolyExtStep::Const(3), // loc(unknown) +PolyExtStep::Const(4), // loc(unknown) +PolyExtStep::Const(5), // loc(unknown) +PolyExtStep::Const(6), // loc(unknown) +PolyExtStep::Const(7), // loc(unknown) +PolyExtStep::Const(8), // loc(unknown) +PolyExtStep::Const(9), // loc(unknown) +PolyExtStep::Const(10), // loc(unknown) +PolyExtStep::Const(2013265910), // loc(unknown) +PolyExtStep::Const(65536), // loc(unknown) +PolyExtStep::Const(1509949441), // loc(unknown) +PolyExtStep::Const(16), // loc(unknown) +PolyExtStep::Const(32), // loc(unknown) +PolyExtStep::Const(64), // loc(unknown) +PolyExtStep::Const(128), // loc(unknown) +PolyExtStep::Const(2005401601), // loc(unknown) +PolyExtStep::Const(256), // loc(unknown) +PolyExtStep::Const(512), // loc(unknown) +PolyExtStep::Const(1024), // loc(unknown) +PolyExtStep::Const(2048), // loc(unknown) +PolyExtStep::Const(4096), // loc(unknown) +PolyExtStep::Const(8192), // loc(unknown) +PolyExtStep::Const(16384), // loc(unknown) +PolyExtStep::Const(32768), // loc(unknown) +PolyExtStep::Const(2013235201), // loc(unknown) +PolyExtStep::Const(131072), // loc(unknown) +PolyExtStep::Const(262144), // loc(unknown) +PolyExtStep::Const(524288), // loc(unknown) +PolyExtStep::Const(1048576), // loc(unknown) +PolyExtStep::Const(2097152), // loc(unknown) +PolyExtStep::Const(4194304), // loc(unknown) +PolyExtStep::Const(8388608), // loc(unknown) +PolyExtStep::Const(16777216), // loc(unknown) +PolyExtStep::Const(33554432), // loc(unknown) +PolyExtStep::Const(67108864), // loc(unknown) +PolyExtStep::Const(134217728), // loc(unknown) +PolyExtStep::Const(268435456), // loc(unknown) +PolyExtStep::Const(536870912), // loc(unknown) +PolyExtStep::Const(1073741824), // loc(unknown) +PolyExtStep::Const(268435454), // loc(unknown) +PolyExtStep::Const(943718400), // loc(unknown) +PolyExtStep::Const(262278199), // loc(unknown) +PolyExtStep::Const(127253399), // loc(unknown) +PolyExtStep::Const(314968988), // loc(unknown) +PolyExtStep::Const(246143118), // loc(unknown) +PolyExtStep::Const(157582794), // loc(unknown) +PolyExtStep::Const(118043943), // loc(unknown) +PolyExtStep::Const(454905424), // loc(unknown) +PolyExtStep::Const(815798990), // loc(unknown) +PolyExtStep::Const(1004040026), // loc(unknown) +PolyExtStep::Const(1773108264), // loc(unknown) +PolyExtStep::Const(1066694495), // loc(unknown) +PolyExtStep::Const(1930780904), // loc(unknown) +PolyExtStep::Const(1180307149), // loc(unknown) +PolyExtStep::Const(1464793095), // loc(unknown) +PolyExtStep::Const(1660766320), // loc(unknown) +PolyExtStep::Const(1389166148), // loc(unknown) +PolyExtStep::Const(343354132), // loc(unknown) +PolyExtStep::Const(1307439985), // loc(unknown) +PolyExtStep::Const(638242172), // loc(unknown) +PolyExtStep::Const(525458520), // loc(unknown) +PolyExtStep::Const(1964135730), // loc(unknown) +PolyExtStep::Const(1751797115), // loc(unknown) +PolyExtStep::Const(1421525369), // loc(unknown) +PolyExtStep::Const(831813382), // loc(unknown) +PolyExtStep::Const(1003792297), // loc(unknown) +PolyExtStep::Const(1006235079), // loc(unknown) +PolyExtStep::Const(1090783436), // loc(unknown) +PolyExtStep::Const(1111203133), // loc(unknown) +PolyExtStep::Const(1124078057), // loc(unknown) +PolyExtStep::Const(1150912935), // loc(unknown) +PolyExtStep::Const(1170029417), // loc(unknown) +PolyExtStep::Const(117294666), // loc(unknown) +PolyExtStep::Const(1201063290), // loc(unknown) +PolyExtStep::Const(1206940496), // loc(unknown) +PolyExtStep::Const(1209164052), // loc(unknown) +PolyExtStep::Const(1213686459), // loc(unknown) +PolyExtStep::Const(1221257987), // loc(unknown) +PolyExtStep::Const(1239734761), // loc(unknown) +PolyExtStep::Const(1262312258), // loc(unknown) +PolyExtStep::Const(1269493554), // loc(unknown) +PolyExtStep::Const(1282239129), // loc(unknown) +PolyExtStep::Const(128479034), // loc(unknown) +PolyExtStep::Const(1290028279), // loc(unknown) +PolyExtStep::Const(1291790245), // loc(unknown) +PolyExtStep::Const(1296144415), // loc(unknown) +PolyExtStep::Const(1303271640), // loc(unknown) +PolyExtStep::Const(1333667262), // loc(unknown) +PolyExtStep::Const(1338899225), // loc(unknown) +PolyExtStep::Const(1339793538), // loc(unknown) +PolyExtStep::Const(1380248020), // loc(unknown) +PolyExtStep::Const(1393671120), // loc(unknown) +PolyExtStep::Const(1401020792), // loc(unknown) +PolyExtStep::Const(140621810), // loc(unknown) +PolyExtStep::Const(1454563174), // loc(unknown) +PolyExtStep::Const(150307788), // loc(unknown) +PolyExtStep::Const(1507936940), // loc(unknown) +PolyExtStep::Const(1518763784), // loc(unknown) +PolyExtStep::Const(1545325389), // loc(unknown) +PolyExtStep::Const(1587822577), // loc(unknown) +PolyExtStep::Const(1608891156), // loc(unknown) +PolyExtStep::Const(162506101), // loc(unknown) +PolyExtStep::Const(1647665372), // loc(unknown) +PolyExtStep::Const(1647670797), // loc(unknown) +PolyExtStep::Const(1649953458), // loc(unknown) +PolyExtStep::Const(1672219447), // loc(unknown) +PolyExtStep::Const(1687379185), // loc(unknown) +PolyExtStep::Const(1715719711), // loc(unknown) +PolyExtStep::Const(1718628547), // loc(unknown) +PolyExtStep::Const(172614232), // loc(unknown) +PolyExtStep::Const(1737016378), // loc(unknown) +PolyExtStep::Const(1740472809), // loc(unknown) +PolyExtStep::Const(1781980094), // loc(unknown) +PolyExtStep::Const(1832911930), // loc(unknown) +PolyExtStep::Const(1845603984), // loc(unknown) +PolyExtStep::Const(1889603648), // loc(unknown) +PolyExtStep::Const(1889898), // loc(unknown) +PolyExtStep::Const(1896271507), // loc(unknown) +PolyExtStep::Const(1917549072), // loc(unknown) +PolyExtStep::Const(1917861751), // loc(unknown) +PolyExtStep::Const(1989924532), // loc(unknown) +PolyExtStep::Const(1997503974), // loc(unknown) +PolyExtStep::Const(202271745), // loc(unknown) +PolyExtStep::Const(204228775), // loc(unknown) +PolyExtStep::Const(228520958), // loc(unknown) +PolyExtStep::Const(238616145), // loc(unknown) +PolyExtStep::Const(241306552), // loc(unknown) +PolyExtStep::Const(273790406), // loc(unknown) +PolyExtStep::Const(306391314), // loc(unknown) +PolyExtStep::Const(342857858), // loc(unknown) +PolyExtStep::Const(390340387), // loc(unknown) +PolyExtStep::Const(395622276), // loc(unknown) +PolyExtStep::Const(427731030), // loc(unknown) +PolyExtStep::Const(459826664), // loc(unknown) +PolyExtStep::Const(51256176), // loc(unknown) +PolyExtStep::Const(53007114), // loc(unknown) +PolyExtStep::Const(540703332), // loc(unknown) +PolyExtStep::Const(588764636), // loc(unknown) +PolyExtStep::Const(608401422), // loc(unknown) +PolyExtStep::Const(622609176), // loc(unknown) +PolyExtStep::Const(641665156), // loc(unknown) +PolyExtStep::Const(686842369), // loc(unknown) +PolyExtStep::Const(695835963), // loc(unknown) +PolyExtStep::Const(708123747), // loc(unknown) +PolyExtStep::Const(714957516), // loc(unknown) +PolyExtStep::Const(716894289), // loc(unknown) +PolyExtStep::Const(738091882), // loc(unknown) +PolyExtStep::Const(755691969), // loc(unknown) +PolyExtStep::Const(781141772), // loc(unknown) +PolyExtStep::Const(78845751), // loc(unknown) +PolyExtStep::Const(790726260), // loc(unknown) +PolyExtStep::Const(809508074), // loc(unknown) +PolyExtStep::Const(813674331), // loc(unknown) +PolyExtStep::Const(825405577), // loc(unknown) +PolyExtStep::Const(897025192), // loc(unknown) +PolyExtStep::Const(925018226), // loc(unknown) +PolyExtStep::Const(930036496), // loc(unknown) +PolyExtStep::Const(942439428), // loc(unknown) +PolyExtStep::Const(989176635), // loc(unknown) +PolyExtStep::Const(989618631), // loc(unknown) +PolyExtStep::Const(993455846), // loc(unknown) +PolyExtStep::Const(1042892522), // loc(unknown) +PolyExtStep::Const(1065075039), // loc(unknown) +PolyExtStep::Const(1079030649), // loc(unknown) +PolyExtStep::Const(1080533265), // loc(unknown) +PolyExtStep::Const(1099252725), // loc(unknown) +PolyExtStep::Const(1147522062), // loc(unknown) +PolyExtStep::Const(1150410028), // loc(unknown) +PolyExtStep::Const(1198261138), // loc(unknown) +PolyExtStep::Const(1215259350), // loc(unknown) +PolyExtStep::Const(1257820264), // loc(unknown) +PolyExtStep::Const(1293938517), // loc(unknown) +PolyExtStep::Const(1402624179), // loc(unknown) +PolyExtStep::Const(142102402), // loc(unknown) +PolyExtStep::Const(1424297384), // loc(unknown) +PolyExtStep::Const(1463323727), // loc(unknown) +PolyExtStep::Const(1478577620), // loc(unknown) +PolyExtStep::Const(1507649755), // loc(unknown) +PolyExtStep::Const(1549062383), // loc(unknown) +PolyExtStep::Const(1567618575), // loc(unknown) +PolyExtStep::Const(1584033957), // loc(unknown) +PolyExtStep::Const(158646617), // loc(unknown) +PolyExtStep::Const(1608853840), // loc(unknown) +PolyExtStep::Const(1622328571), // loc(unknown) +PolyExtStep::Const(162510541), // loc(unknown) +PolyExtStep::Const(1663353317), // loc(unknown) +PolyExtStep::Const(1664590951), // loc(unknown) +PolyExtStep::Const(1748789933), // loc(unknown) +PolyExtStep::Const(1827572010), // loc(unknown) +PolyExtStep::Const(1841795381), // loc(unknown) +PolyExtStep::Const(1891637550), // loc(unknown) +PolyExtStep::Const(1908416316), // loc(unknown) +PolyExtStep::Const(1910423126), // loc(unknown) +PolyExtStep::Const(192082241), // loc(unknown) +PolyExtStep::Const(1950429111), // loc(unknown) +PolyExtStep::Const(217046702), // loc(unknown) +PolyExtStep::Const(27129487), // loc(unknown) +PolyExtStep::Const(447555988), // loc(unknown) +PolyExtStep::Const(457372011), // loc(unknown) +PolyExtStep::Const(538103555), // loc(unknown) +PolyExtStep::Const(552696906), // loc(unknown) +PolyExtStep::Const(59510015), // loc(unknown) +PolyExtStep::Const(623051854), // loc(unknown) +PolyExtStep::Const(760115692), // loc(unknown) +PolyExtStep::Const(76770019), // loc(unknown) +PolyExtStep::Const(855276054), // loc(unknown) +PolyExtStep::Const(862495875), // loc(unknown) +PolyExtStep::Const(890243564), // loc(unknown) +PolyExtStep::Const(946500736), // loc(unknown) +PolyExtStep::Const(497520322), // loc(unknown) +PolyExtStep::Const(1001081699), // loc(unknown) +PolyExtStep::Const(106789798), // loc(unknown) +PolyExtStep::Const(1083257840), // loc(unknown) +PolyExtStep::Const(111593398), // loc(unknown) +PolyExtStep::Const(1188752902), // loc(unknown) +PolyExtStep::Const(13683276), // loc(unknown) +PolyExtStep::Const(1389833583), // loc(unknown) +PolyExtStep::Const(1461037801), // loc(unknown) +PolyExtStep::Const(1558116381), // loc(unknown) +PolyExtStep::Const(1792686146), // loc(unknown) +PolyExtStep::Const(1867716110), // loc(unknown) +PolyExtStep::Const(1928969209), // loc(unknown) +PolyExtStep::Const(1942928017), // loc(unknown) +PolyExtStep::Const(1974912880), // loc(unknown) +PolyExtStep::Const(1997365680), // loc(unknown) +PolyExtStep::Const(20525701), // loc(unknown) +PolyExtStep::Const(375892129), // loc(unknown) +PolyExtStep::Const(51866717), // loc(unknown) +PolyExtStep::Const(606789471), // loc(unknown) +PolyExtStep::Const(658182609), // loc(unknown) +PolyExtStep::Const(65998480), // loc(unknown) +PolyExtStep::Const(801504236), // loc(unknown) +PolyExtStep::Const(918610824), // loc(unknown) +PolyExtStep::Const(98371040), // loc(unknown) +PolyExtStep::Const(1930103076), // loc(unknown) +PolyExtStep::Const(1052077299), // loc(unknown) +PolyExtStep::Const(1540960371), // loc(unknown) +PolyExtStep::Const(924863639), // loc(unknown) +PolyExtStep::Const(1365519753), // loc(unknown) +PolyExtStep::Const(1726563304), // loc(unknown) +PolyExtStep::Const(440300254), // loc(unknown) +PolyExtStep::Const(1891545577), // loc(unknown) +PolyExtStep::Const(822033215), // loc(unknown) +PolyExtStep::Const(1111544260), // loc(unknown) +PolyExtStep::Const(308575117), // loc(unknown) +PolyExtStep::Const(1708681573), // loc(unknown) +PolyExtStep::Const(1240419708), // loc(unknown) +PolyExtStep::Const(1199068823), // loc(unknown) +PolyExtStep::Const(1186174623), // loc(unknown) +PolyExtStep::Const(1551596046), // loc(unknown) +PolyExtStep::Const(1886977120), // loc(unknown) +PolyExtStep::Const(1327682690), // loc(unknown) +PolyExtStep::Const(1210751726), // loc(unknown) +PolyExtStep::Const(1810596765), // loc(unknown) +PolyExtStep::Const(53041581), // loc(unknown) +PolyExtStep::Const(723038058), // loc(unknown) +PolyExtStep::Const(1439947916), // loc(unknown) +PolyExtStep::Const(1136469704), // loc(unknown) +PolyExtStep::Const(205609311), // loc(unknown) +PolyExtStep::Const(1883820770), // loc(unknown) +PolyExtStep::Const(14387587), // loc(unknown) +PolyExtStep::Const(720724951), // loc(unknown) +PolyExtStep::Const(1854174607), // loc(unknown) +PolyExtStep::Const(1629316321), // loc(unknown) +PolyExtStep::Const(530151394), // loc(unknown) +PolyExtStep::Const(1679178250), // loc(unknown) +PolyExtStep::Const(1549779579), // loc(unknown) +PolyExtStep::Const(48375137), // loc(unknown) +PolyExtStep::Const(976057819), // loc(unknown) +PolyExtStep::Const(463976218), // loc(unknown) +PolyExtStep::Const(875839332), // loc(unknown) +PolyExtStep::Const(1946596189), // loc(unknown) +PolyExtStep::Const(434078361), // loc(unknown) +PolyExtStep::Const(1878280202), // loc(unknown) +PolyExtStep::Const(1363837384), // loc(unknown) +PolyExtStep::Const(1470845646), // loc(unknown) +PolyExtStep::Const(1792450386), // loc(unknown) +PolyExtStep::Const(1040977421), // loc(unknown) +PolyExtStep::Const(12), // loc(unknown) +PolyExtStep::Const(48), // loc(unknown) +PolyExtStep::Const(192), // loc(unknown) +PolyExtStep::True, // zirgen/circuit/recursion/recursion.cpp:33 +PolyExtStep::Get(17), // top(recursion::Top)/code(recursion::Code)/select(OneHot)/micro_ops(Reg)(components/mux.h:59) +PolyExtStep::Get(24), // top(recursion::Top)/code(recursion::Code)/inst(Mux)/micro_ops(recursion::MicroInsts)/inst[0](recursion::MicroInst)/opcode(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(16), // top(recursion::Top)/code(recursion::Code)/write_addr(Reg)(zirgen/circuit/recursion/top.cpp:33) +PolyExtStep::Get(496), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[0](recursion::MicroOp)/decode(OneHot)/extract(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(450), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[0](recursion::MicroOp)/decode(OneHot)/add(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(456), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[0](recursion::MicroOp)/decode(OneHot)/sub(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(458), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[0](recursion::MicroOp)/decode(OneHot)/mul(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(460), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[0](recursion::MicroOp)/decode(OneHot)/inv(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(466), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[0](recursion::MicroOp)/decode(OneHot)/eq(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(472), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[0](recursion::MicroOp)/decode(OneHot)/read_iop_header(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(478), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[0](recursion::MicroOp)/decode(OneHot)/read_iop_body(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(484), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[0](recursion::MicroOp)/decode(OneHot)/mix_rng(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(490), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[0](recursion::MicroOp)/decode(OneHot)/select(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Mul(287, 10), // components/onehot.h:56 +PolyExtStep::Mul(289, 2), // components/onehot.h:56 +PolyExtStep::Mul(290, 3), // components/onehot.h:56 +PolyExtStep::Mul(291, 4), // components/onehot.h:56 +PolyExtStep::Mul(292, 5), // components/onehot.h:56 +PolyExtStep::Mul(293, 6), // components/onehot.h:56 +PolyExtStep::Mul(294, 7), // components/onehot.h:56 +PolyExtStep::Mul(295, 8), // components/onehot.h:56 +PolyExtStep::Mul(296, 9), // components/onehot.h:56 +PolyExtStep::Add(288, 298), // components/onehot.h:56 +PolyExtStep::Add(306, 299), // components/onehot.h:56 +PolyExtStep::Add(307, 300), // components/onehot.h:56 +PolyExtStep::Add(308, 301), // components/onehot.h:56 +PolyExtStep::Add(309, 302), // components/onehot.h:56 +PolyExtStep::Add(310, 303), // components/onehot.h:56 +PolyExtStep::Add(311, 304), // components/onehot.h:56 +PolyExtStep::Add(312, 305), // components/onehot.h:56 +PolyExtStep::Add(313, 297), // components/onehot.h:56 +PolyExtStep::Sub(314, 285), // components/onehot.h:50 +PolyExtStep::AndEqz(0, 315), // components/onehot.h:50 +PolyExtStep::Get(444), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[0](recursion::MicroOp)/decode(OneHot)/constop(Reg)(zirgen/circuit/recursion/micro.cpp:29) +PolyExtStep::Get(25), // top(recursion::Top)/code(recursion::Code)/inst(Mux)/micro_ops(recursion::MicroInsts)/inst[0](recursion::MicroInst)/operand[0](Reg)(zirgen/circuit/recursion/micro.cpp:24) +PolyExtStep::Get(27), // top(recursion::Top)/code(recursion::Code)/inst(Mux)/micro_ops(recursion::MicroInsts)/inst[0](recursion::MicroInst)/operand[2](Reg)(zirgen/circuit/recursion/micro.cpp:26) +PolyExtStep::Get(26), // top(recursion::Top)/code(recursion::Code)/inst(Mux)/micro_ops(recursion::MicroInsts)/inst[0](recursion::MicroInst)/operand[1](Reg)(zirgen/circuit/recursion/micro.cpp:25) +PolyExtStep::Get(49), // zirgen/circuit/recursion/wom.cpp:22 +PolyExtStep::AndEqz(0, 320), // zirgen/circuit/recursion/wom.cpp:22 +PolyExtStep::Get(50), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(2, 321), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(51), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(3, 322), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(52), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(4, 323), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(53), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(5, 324), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(54), // zirgen/circuit/recursion/wom.cpp:22 +PolyExtStep::AndEqz(6, 325), // zirgen/circuit/recursion/wom.cpp:22 +PolyExtStep::Get(55), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(7, 326), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(56), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(8, 327), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(57), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(9, 328), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(58), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(10, 329), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(59), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(330, 286), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::AndEqz(11, 331), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Get(60), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(332, 317), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(12, 333), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(61), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(334, 319), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(13, 335), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(62), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(336, 318), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(14, 337), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(63), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(15, 338), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(1, 316, 16), // zirgen/circuit/recursion/micro.cpp:29 +PolyExtStep::Sub(320, 317), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(0, 339), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Sub(325, 319), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(18, 340), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Add(321, 326), // zirgen/circuit/recursion/micro.cpp:38 +PolyExtStep::Add(322, 327), // zirgen/circuit/recursion/micro.cpp:38 +PolyExtStep::Add(323, 328), // zirgen/circuit/recursion/micro.cpp:38 +PolyExtStep::Add(324, 329), // zirgen/circuit/recursion/micro.cpp:38 +PolyExtStep::AndEqz(19, 331), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(332, 341), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(20, 345), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(334, 342), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(21, 346), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(336, 343), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(22, 347), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(338, 344), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(23, 348), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(17, 288, 24), // zirgen/circuit/recursion/micro.cpp:35 +PolyExtStep::Sub(321, 326), // zirgen/circuit/recursion/micro.cpp:44 +PolyExtStep::Sub(322, 327), // zirgen/circuit/recursion/micro.cpp:44 +PolyExtStep::Sub(323, 328), // zirgen/circuit/recursion/micro.cpp:44 +PolyExtStep::Sub(324, 329), // zirgen/circuit/recursion/micro.cpp:44 +PolyExtStep::Sub(332, 349), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(20, 353), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(334, 350), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(26, 354), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(336, 351), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(27, 355), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(338, 352), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(28, 356), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(25, 289, 29), // zirgen/circuit/recursion/micro.cpp:41 +PolyExtStep::Mul(321, 326), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(321, 327), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(321, 328), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(321, 329), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(322, 329), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(323, 329), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(324, 329), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(322, 326), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(322, 327), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(322, 328), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(323, 326), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(323, 327), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(323, 328), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(324, 326), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(324, 327), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(324, 328), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(363, 11), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(358, 364), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(359, 365), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(360, 366), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(361, 369), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(362, 372), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(378, 11), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(375, 367), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(376, 368), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(377, 371), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(380, 373), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(381, 370), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(374, 379), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(382, 11), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(357, 386), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Sub(332, 387), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(20, 388), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(334, 385), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(31, 389), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(336, 383), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(32, 390), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(338, 384), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(33, 391), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(30, 290, 34), // zirgen/circuit/recursion/micro.cpp:47 +PolyExtStep::Mul(291, 319), // zirgen/circuit/recursion/micro.cpp:53 +PolyExtStep::AndEqz(18, 325), // zirgen/circuit/recursion/wom.cpp:22 +PolyExtStep::AndEqz(36, 326), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(37, 327), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(38, 328), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(39, 329), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Mul(321, 332), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(321, 334), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(321, 336), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(321, 338), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(322, 338), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(323, 338), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(324, 338), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(322, 332), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(322, 334), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(322, 336), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(323, 332), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(323, 334), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(323, 336), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(324, 332), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(324, 334), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(324, 336), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(399, 11), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(394, 400), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(395, 401), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(396, 402), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(397, 405), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(398, 408), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(414, 11), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(411, 403), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(412, 404), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(413, 407), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(416, 409), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(417, 406), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(410, 415), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(418, 11), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(393, 422), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Sub(1, 423), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::AndEqz(40, 424), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Sub(0, 421), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::AndEqz(41, 425), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Sub(0, 419), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::AndEqz(42, 426), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Sub(0, 420), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::AndEqz(43, 427), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::AndCond(35, 392, 44), // zirgen/circuit/recursion/micro.cpp:53 +PolyExtStep::Sub(1, 319), // zirgen/circuit/recursion/micro.cpp:60 +PolyExtStep::Mul(291, 428), // zirgen/circuit/recursion/micro.cpp:60 +PolyExtStep::Get(502), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[0](recursion::MicroOp)/extra(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Sub(1, 332), // zirgen/circuit/recursion/micro.cpp:71 +PolyExtStep::Mul(332, 431), // zirgen/circuit/recursion/micro.cpp:71 +PolyExtStep::AndEqz(40, 432), // zirgen/circuit/recursion/micro.cpp:71 +PolyExtStep::Mul(430, 321), // zirgen/circuit/recursion/micro.cpp:73 +PolyExtStep::Sub(433, 431), // zirgen/circuit/recursion/micro.cpp:73 +PolyExtStep::AndEqz(46, 434), // zirgen/circuit/recursion/micro.cpp:73 +PolyExtStep::AndEqz(47, 393), // zirgen/circuit/recursion/micro.cpp:75 +PolyExtStep::AndCond(45, 429, 48), // zirgen/circuit/recursion/micro.cpp:60 +PolyExtStep::Sub(0, 332), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::AndEqz(29, 435), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::Sub(0, 334), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::AndEqz(50, 436), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::Sub(0, 336), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::AndEqz(51, 437), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::Sub(0, 338), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::AndEqz(52, 438), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::AndCond(49, 292, 53), // zirgen/circuit/recursion/micro.cpp:78 +PolyExtStep::AndEqz(12, 332), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(55, 334), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(56, 336), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(57, 338), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(54, 293, 58), // zirgen/circuit/recursion/micro.cpp:85 +PolyExtStep::Mul(317, 334), // zirgen/circuit/recursion/micro.cpp:104 +PolyExtStep::AndEqz(11, 439), // zirgen/circuit/recursion/micro.cpp:104 +PolyExtStep::Mul(319, 336), // zirgen/circuit/recursion/micro.cpp:105 +PolyExtStep::AndEqz(60, 440), // zirgen/circuit/recursion/micro.cpp:105 +PolyExtStep::Mul(319, 338), // zirgen/circuit/recursion/micro.cpp:106 +PolyExtStep::AndEqz(61, 441), // zirgen/circuit/recursion/micro.cpp:106 +PolyExtStep::AndCond(59, 294, 62), // zirgen/circuit/recursion/micro.cpp:92 +PolyExtStep::Get(636), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[2](recursion::MicroOp)/extra(Reg)(zirgen/circuit/recursion/micro.cpp:117) +PolyExtStep::Mul(318, 442), // zirgen/circuit/recursion/micro.cpp:117 +PolyExtStep::Mul(443, 12), // zirgen/circuit/recursion/micro.cpp:119 +PolyExtStep::Add(444, 322), // zirgen/circuit/recursion/micro.cpp:119 +PolyExtStep::Mul(445, 12), // zirgen/circuit/recursion/micro.cpp:120 +PolyExtStep::Add(446, 321), // zirgen/circuit/recursion/micro.cpp:120 +PolyExtStep::Mul(447, 12), // zirgen/circuit/recursion/micro.cpp:121 +PolyExtStep::Add(448, 327), // zirgen/circuit/recursion/micro.cpp:121 +PolyExtStep::Mul(449, 12), // zirgen/circuit/recursion/micro.cpp:122 +PolyExtStep::Add(450, 326), // zirgen/circuit/recursion/micro.cpp:122 +PolyExtStep::Sub(430, 451), // zirgen/circuit/recursion/micro.cpp:124 +PolyExtStep::AndEqz(19, 452), // zirgen/circuit/recursion/micro.cpp:124 +PolyExtStep::AndEqz(64, 331), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(332, 451), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(65, 453), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(66, 334), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(67, 336), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(68, 338), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(63, 295, 69), // zirgen/circuit/recursion/micro.cpp:108 +PolyExtStep::Mul(318, 321), // zirgen/circuit/recursion/micro.cpp:129 +PolyExtStep::Add(319, 454), // zirgen/circuit/recursion/micro.cpp:129 +PolyExtStep::Sub(325, 455), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(18, 456), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(71, 331), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(332, 326), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(72, 457), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(334, 327), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(73, 458), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(336, 328), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(74, 459), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(338, 329), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(75, 460), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(70, 296, 76), // zirgen/circuit/recursion/micro.cpp:127 +PolyExtStep::Mul(319, 318), // zirgen/circuit/recursion/micro.cpp:144 +PolyExtStep::Sub(1, 318), // zirgen/circuit/recursion/micro.cpp:145 +PolyExtStep::Mul(319, 462), // zirgen/circuit/recursion/micro.cpp:145 +PolyExtStep::Mul(461, 324), // zirgen/circuit/recursion/micro.cpp:144 +PolyExtStep::Mul(428, 318), // zirgen/circuit/recursion/micro.cpp:146 +PolyExtStep::Mul(428, 462), // zirgen/circuit/recursion/micro.cpp:147 +PolyExtStep::Mul(463, 323), // zirgen/circuit/recursion/micro.cpp:145 +PolyExtStep::Mul(465, 322), // zirgen/circuit/recursion/micro.cpp:146 +PolyExtStep::Mul(466, 321), // zirgen/circuit/recursion/micro.cpp:147 +PolyExtStep::Add(464, 467), // zirgen/circuit/recursion/micro.cpp:144 +PolyExtStep::Add(470, 468), // zirgen/circuit/recursion/micro.cpp:144 +PolyExtStep::Add(471, 469), // zirgen/circuit/recursion/micro.cpp:144 +PolyExtStep::AndEqz(40, 331), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(332, 472), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(78, 473), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(79, 334), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(80, 336), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(81, 338), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(77, 287, 82), // zirgen/circuit/recursion/micro.cpp:140 +PolyExtStep::Add(286, 1), // zirgen/circuit/recursion/micro.cpp:163 +PolyExtStep::Get(28), // top(recursion::Top)/code(recursion::Code)/inst(Mux)/micro_ops(recursion::MicroInsts)/inst[1](recursion::MicroInst)/opcode(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(514), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[1](recursion::MicroOp)/decode(OneHot)/add(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(520), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[1](recursion::MicroOp)/decode(OneHot)/sub(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(526), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[1](recursion::MicroOp)/decode(OneHot)/mul(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(532), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[1](recursion::MicroOp)/decode(OneHot)/inv(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(538), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[1](recursion::MicroOp)/decode(OneHot)/eq(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(544), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[1](recursion::MicroOp)/decode(OneHot)/read_iop_header(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(550), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[1](recursion::MicroOp)/decode(OneHot)/read_iop_body(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(556), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[1](recursion::MicroOp)/decode(OneHot)/mix_rng(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(562), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[1](recursion::MicroOp)/decode(OneHot)/select(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(568), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[1](recursion::MicroOp)/decode(OneHot)/extract(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Mul(477, 2), // components/onehot.h:56 +PolyExtStep::Mul(478, 3), // components/onehot.h:56 +PolyExtStep::Mul(479, 4), // components/onehot.h:56 +PolyExtStep::Mul(480, 5), // components/onehot.h:56 +PolyExtStep::Mul(481, 6), // components/onehot.h:56 +PolyExtStep::Mul(482, 7), // components/onehot.h:56 +PolyExtStep::Mul(483, 8), // components/onehot.h:56 +PolyExtStep::Mul(484, 9), // components/onehot.h:56 +PolyExtStep::Mul(485, 10), // components/onehot.h:56 +PolyExtStep::Add(476, 486), // components/onehot.h:56 +PolyExtStep::Add(495, 487), // components/onehot.h:56 +PolyExtStep::Add(496, 488), // components/onehot.h:56 +PolyExtStep::Add(497, 489), // components/onehot.h:56 +PolyExtStep::Add(498, 490), // components/onehot.h:56 +PolyExtStep::Add(499, 491), // components/onehot.h:56 +PolyExtStep::Add(500, 492), // components/onehot.h:56 +PolyExtStep::Add(501, 493), // components/onehot.h:56 +PolyExtStep::Add(502, 494), // components/onehot.h:56 +PolyExtStep::Sub(503, 475), // components/onehot.h:50 +PolyExtStep::AndEqz(83, 504), // components/onehot.h:50 +PolyExtStep::Get(508), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[1](recursion::MicroOp)/decode(OneHot)/constop(Reg)(zirgen/circuit/recursion/micro.cpp:29) +PolyExtStep::Get(29), // top(recursion::Top)/code(recursion::Code)/inst(Mux)/micro_ops(recursion::MicroInsts)/inst[1](recursion::MicroInst)/operand[0](Reg)(zirgen/circuit/recursion/micro.cpp:24) +PolyExtStep::Get(31), // top(recursion::Top)/code(recursion::Code)/inst(Mux)/micro_ops(recursion::MicroInsts)/inst[1](recursion::MicroInst)/operand[2](Reg)(zirgen/circuit/recursion/micro.cpp:26) +PolyExtStep::Get(30), // top(recursion::Top)/code(recursion::Code)/inst(Mux)/micro_ops(recursion::MicroInsts)/inst[1](recursion::MicroInst)/operand[1](Reg)(zirgen/circuit/recursion/micro.cpp:25) +PolyExtStep::Get(64), // zirgen/circuit/recursion/wom.cpp:22 +PolyExtStep::AndEqz(0, 509), // zirgen/circuit/recursion/wom.cpp:22 +PolyExtStep::Get(65), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(85, 510), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(66), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(86, 511), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(67), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(87, 512), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(68), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(88, 513), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(69), // zirgen/circuit/recursion/wom.cpp:22 +PolyExtStep::AndEqz(89, 514), // zirgen/circuit/recursion/wom.cpp:22 +PolyExtStep::Get(70), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(90, 515), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(76), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(91, 516), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(82), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(92, 517), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(88), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(93, 518), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(94), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(519, 474), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::AndEqz(94, 520), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Get(100), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(521, 506), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(95, 522), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(106), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(523, 508), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(96, 524), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(112), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(525, 507), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(97, 526), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(118), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(98, 527), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(84, 505, 99), // zirgen/circuit/recursion/micro.cpp:29 +PolyExtStep::Sub(509, 506), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(0, 528), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Sub(514, 508), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(101, 529), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Add(510, 515), // zirgen/circuit/recursion/micro.cpp:38 +PolyExtStep::Add(511, 516), // zirgen/circuit/recursion/micro.cpp:38 +PolyExtStep::Add(512, 517), // zirgen/circuit/recursion/micro.cpp:38 +PolyExtStep::Add(513, 518), // zirgen/circuit/recursion/micro.cpp:38 +PolyExtStep::AndEqz(102, 520), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(521, 530), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(103, 534), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(523, 531), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(104, 535), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(525, 532), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(105, 536), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(527, 533), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(106, 537), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(100, 476, 107), // zirgen/circuit/recursion/micro.cpp:35 +PolyExtStep::Sub(510, 515), // zirgen/circuit/recursion/micro.cpp:44 +PolyExtStep::Sub(511, 516), // zirgen/circuit/recursion/micro.cpp:44 +PolyExtStep::Sub(512, 517), // zirgen/circuit/recursion/micro.cpp:44 +PolyExtStep::Sub(513, 518), // zirgen/circuit/recursion/micro.cpp:44 +PolyExtStep::Sub(521, 538), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(103, 542), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(523, 539), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(109, 543), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(525, 540), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(110, 544), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(527, 541), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(111, 545), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(108, 477, 112), // zirgen/circuit/recursion/micro.cpp:41 +PolyExtStep::Mul(510, 515), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(510, 516), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(510, 517), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(510, 518), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(511, 518), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(512, 518), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(513, 518), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(511, 515), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(511, 516), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(511, 517), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(512, 515), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(512, 516), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(512, 517), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(513, 515), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(513, 516), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(513, 517), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(552, 11), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(547, 553), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(548, 554), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(549, 555), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(550, 558), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(551, 561), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(567, 11), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(564, 556), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(565, 557), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(566, 560), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(569, 562), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(570, 559), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(563, 568), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(571, 11), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(546, 575), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Sub(521, 576), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(103, 577), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(523, 574), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(114, 578), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(525, 572), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(115, 579), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(527, 573), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(116, 580), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(113, 478, 117), // zirgen/circuit/recursion/micro.cpp:47 +PolyExtStep::Mul(479, 508), // zirgen/circuit/recursion/micro.cpp:53 +PolyExtStep::AndEqz(101, 514), // zirgen/circuit/recursion/wom.cpp:22 +PolyExtStep::AndEqz(119, 515), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(120, 516), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(121, 517), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(122, 518), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Mul(510, 521), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(510, 523), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(510, 525), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(510, 527), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(511, 527), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(512, 527), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(513, 527), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(511, 521), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(511, 523), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(511, 525), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(512, 521), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(512, 523), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(512, 525), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(513, 521), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(513, 523), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(513, 525), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(588, 11), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(583, 589), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(584, 590), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(585, 591), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(586, 594), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(587, 597), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(603, 11), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(600, 592), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(601, 593), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(602, 596), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(605, 598), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(606, 595), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(599, 604), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(607, 11), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(582, 611), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Sub(1, 612), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::AndEqz(123, 613), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Sub(0, 610), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::AndEqz(124, 614), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Sub(0, 608), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::AndEqz(125, 615), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Sub(0, 609), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::AndEqz(126, 616), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::AndCond(118, 581, 127), // zirgen/circuit/recursion/micro.cpp:53 +PolyExtStep::Sub(1, 508), // zirgen/circuit/recursion/micro.cpp:60 +PolyExtStep::Mul(479, 617), // zirgen/circuit/recursion/micro.cpp:60 +PolyExtStep::Get(574), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[1](recursion::MicroOp)/extra(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Sub(1, 521), // zirgen/circuit/recursion/micro.cpp:71 +PolyExtStep::Mul(521, 620), // zirgen/circuit/recursion/micro.cpp:71 +PolyExtStep::AndEqz(123, 621), // zirgen/circuit/recursion/micro.cpp:71 +PolyExtStep::Mul(619, 510), // zirgen/circuit/recursion/micro.cpp:73 +PolyExtStep::Sub(622, 620), // zirgen/circuit/recursion/micro.cpp:73 +PolyExtStep::AndEqz(129, 623), // zirgen/circuit/recursion/micro.cpp:73 +PolyExtStep::AndEqz(130, 582), // zirgen/circuit/recursion/micro.cpp:75 +PolyExtStep::AndCond(128, 618, 131), // zirgen/circuit/recursion/micro.cpp:60 +PolyExtStep::Sub(0, 521), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::AndEqz(112, 624), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::Sub(0, 523), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::AndEqz(133, 625), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::Sub(0, 525), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::AndEqz(134, 626), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::Sub(0, 527), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::AndEqz(135, 627), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::AndCond(132, 480, 136), // zirgen/circuit/recursion/micro.cpp:78 +PolyExtStep::AndEqz(95, 521), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(138, 523), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(139, 525), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(140, 527), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(137, 481, 141), // zirgen/circuit/recursion/micro.cpp:85 +PolyExtStep::Mul(506, 523), // zirgen/circuit/recursion/micro.cpp:104 +PolyExtStep::AndEqz(94, 628), // zirgen/circuit/recursion/micro.cpp:104 +PolyExtStep::Mul(508, 525), // zirgen/circuit/recursion/micro.cpp:105 +PolyExtStep::AndEqz(143, 629), // zirgen/circuit/recursion/micro.cpp:105 +PolyExtStep::Mul(508, 527), // zirgen/circuit/recursion/micro.cpp:106 +PolyExtStep::AndEqz(144, 630), // zirgen/circuit/recursion/micro.cpp:106 +PolyExtStep::AndCond(142, 482, 145), // zirgen/circuit/recursion/micro.cpp:92 +PolyExtStep::Get(502), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[0](recursion::MicroOp)/extra(Reg)(zirgen/circuit/recursion/micro.cpp:117) +PolyExtStep::Mul(507, 631), // zirgen/circuit/recursion/micro.cpp:117 +PolyExtStep::Mul(632, 12), // zirgen/circuit/recursion/micro.cpp:119 +PolyExtStep::Add(633, 511), // zirgen/circuit/recursion/micro.cpp:119 +PolyExtStep::Mul(634, 12), // zirgen/circuit/recursion/micro.cpp:120 +PolyExtStep::Add(635, 510), // zirgen/circuit/recursion/micro.cpp:120 +PolyExtStep::Mul(636, 12), // zirgen/circuit/recursion/micro.cpp:121 +PolyExtStep::Add(637, 516), // zirgen/circuit/recursion/micro.cpp:121 +PolyExtStep::Mul(638, 12), // zirgen/circuit/recursion/micro.cpp:122 +PolyExtStep::Add(639, 515), // zirgen/circuit/recursion/micro.cpp:122 +PolyExtStep::Sub(619, 640), // zirgen/circuit/recursion/micro.cpp:124 +PolyExtStep::AndEqz(102, 641), // zirgen/circuit/recursion/micro.cpp:124 +PolyExtStep::AndEqz(147, 520), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(521, 640), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(148, 642), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(149, 523), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(150, 525), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(151, 527), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(146, 483, 152), // zirgen/circuit/recursion/micro.cpp:108 +PolyExtStep::Mul(507, 510), // zirgen/circuit/recursion/micro.cpp:129 +PolyExtStep::Add(508, 643), // zirgen/circuit/recursion/micro.cpp:129 +PolyExtStep::Sub(514, 644), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(101, 645), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(154, 520), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(521, 515), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(155, 646), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(523, 516), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(156, 647), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(525, 517), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(157, 648), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(527, 518), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(158, 649), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(153, 484, 159), // zirgen/circuit/recursion/micro.cpp:127 +PolyExtStep::Mul(508, 507), // zirgen/circuit/recursion/micro.cpp:144 +PolyExtStep::Sub(1, 507), // zirgen/circuit/recursion/micro.cpp:145 +PolyExtStep::Mul(508, 651), // zirgen/circuit/recursion/micro.cpp:145 +PolyExtStep::Mul(650, 513), // zirgen/circuit/recursion/micro.cpp:144 +PolyExtStep::Mul(617, 507), // zirgen/circuit/recursion/micro.cpp:146 +PolyExtStep::Mul(617, 651), // zirgen/circuit/recursion/micro.cpp:147 +PolyExtStep::Mul(652, 512), // zirgen/circuit/recursion/micro.cpp:145 +PolyExtStep::Mul(654, 511), // zirgen/circuit/recursion/micro.cpp:146 +PolyExtStep::Mul(655, 510), // zirgen/circuit/recursion/micro.cpp:147 +PolyExtStep::Add(653, 656), // zirgen/circuit/recursion/micro.cpp:144 +PolyExtStep::Add(659, 657), // zirgen/circuit/recursion/micro.cpp:144 +PolyExtStep::Add(660, 658), // zirgen/circuit/recursion/micro.cpp:144 +PolyExtStep::AndEqz(123, 520), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(521, 661), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(161, 662), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(162, 523), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(163, 525), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(164, 527), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(160, 485, 165), // zirgen/circuit/recursion/micro.cpp:140 +PolyExtStep::Add(286, 2), // zirgen/circuit/recursion/micro.cpp:163 +PolyExtStep::Get(32), // top(recursion::Top)/code(recursion::Code)/inst(Mux)/micro_ops(recursion::MicroInsts)/inst[2](recursion::MicroInst)/opcode(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(585), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[2](recursion::MicroOp)/decode(OneHot)/add(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(590), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[2](recursion::MicroOp)/decode(OneHot)/sub(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(595), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[2](recursion::MicroOp)/decode(OneHot)/mul(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(600), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[2](recursion::MicroOp)/decode(OneHot)/inv(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(605), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[2](recursion::MicroOp)/decode(OneHot)/eq(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(610), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[2](recursion::MicroOp)/decode(OneHot)/read_iop_header(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(615), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[2](recursion::MicroOp)/decode(OneHot)/read_iop_body(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(620), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[2](recursion::MicroOp)/decode(OneHot)/mix_rng(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(625), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[2](recursion::MicroOp)/decode(OneHot)/select(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Get(630), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[2](recursion::MicroOp)/decode(OneHot)/extract(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Mul(666, 2), // components/onehot.h:56 +PolyExtStep::Mul(667, 3), // components/onehot.h:56 +PolyExtStep::Mul(668, 4), // components/onehot.h:56 +PolyExtStep::Mul(669, 5), // components/onehot.h:56 +PolyExtStep::Mul(670, 6), // components/onehot.h:56 +PolyExtStep::Mul(671, 7), // components/onehot.h:56 +PolyExtStep::Mul(672, 8), // components/onehot.h:56 +PolyExtStep::Mul(673, 9), // components/onehot.h:56 +PolyExtStep::Mul(674, 10), // components/onehot.h:56 +PolyExtStep::Add(665, 675), // components/onehot.h:56 +PolyExtStep::Add(684, 676), // components/onehot.h:56 +PolyExtStep::Add(685, 677), // components/onehot.h:56 +PolyExtStep::Add(686, 678), // components/onehot.h:56 +PolyExtStep::Add(687, 679), // components/onehot.h:56 +PolyExtStep::Add(688, 680), // components/onehot.h:56 +PolyExtStep::Add(689, 681), // components/onehot.h:56 +PolyExtStep::Add(690, 682), // components/onehot.h:56 +PolyExtStep::Add(691, 683), // components/onehot.h:56 +PolyExtStep::Sub(692, 664), // components/onehot.h:50 +PolyExtStep::AndEqz(166, 693), // components/onehot.h:50 +PolyExtStep::Get(580), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[2](recursion::MicroOp)/decode(OneHot)/constop(Reg)(zirgen/circuit/recursion/micro.cpp:29) +PolyExtStep::Get(33), // top(recursion::Top)/code(recursion::Code)/inst(Mux)/micro_ops(recursion::MicroInsts)/inst[2](recursion::MicroInst)/operand[0](Reg)(zirgen/circuit/recursion/micro.cpp:24) +PolyExtStep::Get(35), // top(recursion::Top)/code(recursion::Code)/inst(Mux)/micro_ops(recursion::MicroInsts)/inst[2](recursion::MicroInst)/operand[2](Reg)(zirgen/circuit/recursion/micro.cpp:26) +PolyExtStep::Get(34), // top(recursion::Top)/code(recursion::Code)/inst(Mux)/micro_ops(recursion::MicroInsts)/inst[2](recursion::MicroInst)/operand[1](Reg)(zirgen/circuit/recursion/micro.cpp:25) +PolyExtStep::Get(124), // zirgen/circuit/recursion/wom.cpp:22 +PolyExtStep::AndEqz(0, 698), // zirgen/circuit/recursion/wom.cpp:22 +PolyExtStep::Get(130), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(168, 699), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(136), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(169, 700), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(142), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(170, 701), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(148), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(171, 702), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(154), // zirgen/circuit/recursion/wom.cpp:22 +PolyExtStep::AndEqz(172, 703), // zirgen/circuit/recursion/wom.cpp:22 +PolyExtStep::Get(160), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(173, 704), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(166), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(174, 705), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(172), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(175, 706), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(178), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(176, 707), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(184), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(708, 663), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::AndEqz(177, 709), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Get(190), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(710, 695), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(178, 711), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(196), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(712, 697), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(179, 713), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(202), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(714, 696), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(180, 715), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Get(208), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(181, 716), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(167, 694, 182), // zirgen/circuit/recursion/micro.cpp:29 +PolyExtStep::Sub(698, 695), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(0, 717), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Sub(703, 697), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(184, 718), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Add(699, 704), // zirgen/circuit/recursion/micro.cpp:38 +PolyExtStep::Add(700, 705), // zirgen/circuit/recursion/micro.cpp:38 +PolyExtStep::Add(701, 706), // zirgen/circuit/recursion/micro.cpp:38 +PolyExtStep::Add(702, 707), // zirgen/circuit/recursion/micro.cpp:38 +PolyExtStep::AndEqz(185, 709), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(710, 719), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(186, 723), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(712, 720), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(187, 724), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(714, 721), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(188, 725), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(716, 722), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(189, 726), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(183, 665, 190), // zirgen/circuit/recursion/micro.cpp:35 +PolyExtStep::Sub(699, 704), // zirgen/circuit/recursion/micro.cpp:44 +PolyExtStep::Sub(700, 705), // zirgen/circuit/recursion/micro.cpp:44 +PolyExtStep::Sub(701, 706), // zirgen/circuit/recursion/micro.cpp:44 +PolyExtStep::Sub(702, 707), // zirgen/circuit/recursion/micro.cpp:44 +PolyExtStep::Sub(710, 727), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(186, 731), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(712, 728), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(192, 732), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(714, 729), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(193, 733), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(716, 730), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(194, 734), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(191, 666, 195), // zirgen/circuit/recursion/micro.cpp:41 +PolyExtStep::Mul(699, 704), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(699, 705), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(699, 706), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(699, 707), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(700, 707), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(701, 707), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(702, 707), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(700, 704), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(700, 705), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(700, 706), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(701, 704), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(701, 705), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(701, 706), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(702, 704), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(702, 705), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(702, 706), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(741, 11), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(736, 742), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(737, 743), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(738, 744), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(739, 747), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(740, 750), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(756, 11), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(753, 745), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(754, 746), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(755, 749), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(758, 751), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(759, 748), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(752, 757), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Mul(760, 11), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Add(735, 764), // zirgen/circuit/recursion/micro.cpp:50 +PolyExtStep::Sub(710, 765), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(186, 766), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(712, 763), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(197, 767), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(714, 761), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(198, 768), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(716, 762), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(199, 769), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(196, 667, 200), // zirgen/circuit/recursion/micro.cpp:47 +PolyExtStep::Mul(668, 697), // zirgen/circuit/recursion/micro.cpp:53 +PolyExtStep::AndEqz(184, 703), // zirgen/circuit/recursion/wom.cpp:22 +PolyExtStep::AndEqz(202, 704), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(203, 705), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(204, 706), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(205, 707), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Mul(699, 710), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(699, 712), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(699, 714), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(699, 716), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(700, 716), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(701, 716), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(702, 716), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(700, 710), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(700, 712), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(700, 714), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(701, 710), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(701, 712), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(701, 714), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(702, 710), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(702, 712), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(702, 714), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(777, 11), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(772, 778), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(773, 779), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(774, 780), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(775, 783), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(776, 786), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(792, 11), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(789, 781), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(790, 782), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(791, 785), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(794, 787), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(795, 784), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(788, 793), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Mul(796, 11), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Add(771, 800), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Sub(1, 801), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::AndEqz(206, 802), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Sub(0, 799), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::AndEqz(207, 803), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Sub(0, 797), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::AndEqz(208, 804), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::Sub(0, 798), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::AndEqz(209, 805), // zirgen/circuit/recursion/micro.cpp:58 +PolyExtStep::AndCond(201, 770, 210), // zirgen/circuit/recursion/micro.cpp:53 +PolyExtStep::Sub(1, 697), // zirgen/circuit/recursion/micro.cpp:60 +PolyExtStep::Mul(668, 806), // zirgen/circuit/recursion/micro.cpp:60 +PolyExtStep::Get(635), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[2](recursion::MicroOp)/extra(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Sub(1, 710), // zirgen/circuit/recursion/micro.cpp:71 +PolyExtStep::Mul(710, 809), // zirgen/circuit/recursion/micro.cpp:71 +PolyExtStep::AndEqz(206, 810), // zirgen/circuit/recursion/micro.cpp:71 +PolyExtStep::Mul(808, 699), // zirgen/circuit/recursion/micro.cpp:73 +PolyExtStep::Sub(811, 809), // zirgen/circuit/recursion/micro.cpp:73 +PolyExtStep::AndEqz(212, 812), // zirgen/circuit/recursion/micro.cpp:73 +PolyExtStep::AndEqz(213, 771), // zirgen/circuit/recursion/micro.cpp:75 +PolyExtStep::AndCond(211, 807, 214), // zirgen/circuit/recursion/micro.cpp:60 +PolyExtStep::Sub(0, 710), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::AndEqz(195, 813), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::Sub(0, 712), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::AndEqz(216, 814), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::Sub(0, 714), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::AndEqz(217, 815), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::Sub(0, 716), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::AndEqz(218, 816), // zirgen/circuit/recursion/micro.cpp:83 +PolyExtStep::AndCond(215, 669, 219), // zirgen/circuit/recursion/micro.cpp:78 +PolyExtStep::AndEqz(178, 710), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(221, 712), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(222, 714), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(223, 716), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(220, 670, 224), // zirgen/circuit/recursion/micro.cpp:85 +PolyExtStep::Mul(695, 712), // zirgen/circuit/recursion/micro.cpp:104 +PolyExtStep::AndEqz(177, 817), // zirgen/circuit/recursion/micro.cpp:104 +PolyExtStep::Mul(697, 714), // zirgen/circuit/recursion/micro.cpp:105 +PolyExtStep::AndEqz(226, 818), // zirgen/circuit/recursion/micro.cpp:105 +PolyExtStep::Mul(697, 716), // zirgen/circuit/recursion/micro.cpp:106 +PolyExtStep::AndEqz(227, 819), // zirgen/circuit/recursion/micro.cpp:106 +PolyExtStep::AndCond(225, 671, 228), // zirgen/circuit/recursion/micro.cpp:92 +PolyExtStep::Get(574), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/op[1](recursion::MicroOp)/extra(Reg)(zirgen/circuit/recursion/micro.cpp:117) +PolyExtStep::Mul(696, 820), // zirgen/circuit/recursion/micro.cpp:117 +PolyExtStep::Mul(821, 12), // zirgen/circuit/recursion/micro.cpp:119 +PolyExtStep::Add(822, 700), // zirgen/circuit/recursion/micro.cpp:119 +PolyExtStep::Mul(823, 12), // zirgen/circuit/recursion/micro.cpp:120 +PolyExtStep::Add(824, 699), // zirgen/circuit/recursion/micro.cpp:120 +PolyExtStep::Mul(825, 12), // zirgen/circuit/recursion/micro.cpp:121 +PolyExtStep::Add(826, 705), // zirgen/circuit/recursion/micro.cpp:121 +PolyExtStep::Mul(827, 12), // zirgen/circuit/recursion/micro.cpp:122 +PolyExtStep::Add(828, 704), // zirgen/circuit/recursion/micro.cpp:122 +PolyExtStep::Sub(808, 829), // zirgen/circuit/recursion/micro.cpp:124 +PolyExtStep::AndEqz(185, 830), // zirgen/circuit/recursion/micro.cpp:124 +PolyExtStep::AndEqz(230, 709), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(710, 829), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(231, 831), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(232, 712), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(233, 714), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(234, 716), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(229, 672, 235), // zirgen/circuit/recursion/micro.cpp:108 +PolyExtStep::Mul(696, 699), // zirgen/circuit/recursion/micro.cpp:129 +PolyExtStep::Add(697, 832), // zirgen/circuit/recursion/micro.cpp:129 +PolyExtStep::Sub(703, 833), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(184, 834), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(237, 709), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(710, 704), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(238, 835), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(712, 705), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(239, 836), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(714, 706), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(240, 837), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(716, 707), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(241, 838), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(236, 673, 242), // zirgen/circuit/recursion/micro.cpp:127 +PolyExtStep::Mul(697, 696), // zirgen/circuit/recursion/micro.cpp:144 +PolyExtStep::Sub(1, 696), // zirgen/circuit/recursion/micro.cpp:145 +PolyExtStep::Mul(697, 840), // zirgen/circuit/recursion/micro.cpp:145 +PolyExtStep::Mul(839, 702), // zirgen/circuit/recursion/micro.cpp:144 +PolyExtStep::Mul(806, 696), // zirgen/circuit/recursion/micro.cpp:146 +PolyExtStep::Mul(806, 840), // zirgen/circuit/recursion/micro.cpp:147 +PolyExtStep::Mul(841, 701), // zirgen/circuit/recursion/micro.cpp:145 +PolyExtStep::Mul(843, 700), // zirgen/circuit/recursion/micro.cpp:146 +PolyExtStep::Mul(844, 699), // zirgen/circuit/recursion/micro.cpp:147 +PolyExtStep::Add(842, 845), // zirgen/circuit/recursion/micro.cpp:144 +PolyExtStep::Add(848, 846), // zirgen/circuit/recursion/micro.cpp:144 +PolyExtStep::Add(849, 847), // zirgen/circuit/recursion/micro.cpp:144 +PolyExtStep::AndEqz(206, 709), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(710, 850), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(244, 851), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(245, 712), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(246, 714), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(247, 716), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(243, 674, 248), // zirgen/circuit/recursion/micro.cpp:140 +PolyExtStep::AndCond(0, 284, 249), // components/mux.h:59 +PolyExtStep::Get(18), // top(recursion::Top)/code(recursion::Code)/select(OneHot)/macro_ops(Reg)(components/mux.h:59) +PolyExtStep::AndCond(0, 317, 0), // components/mux.h:59 +PolyExtStep::Sub(326, 286), // zirgen/circuit/recursion/wom.cpp:27 +PolyExtStep::AndEqz(0, 853), // zirgen/circuit/recursion/wom.cpp:27 +PolyExtStep::AndEqz(252, 327), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(253, 328), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(254, 329), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(255, 330), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(251, 319, 256), // components/mux.h:59 +PolyExtStep::Sub(326, 697), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(0, 854), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Sub(332, 696), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(258, 855), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Mul(699, 700), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(701, 702), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(701, 2), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(702, 2), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(857, 2), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(699, 858), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(700, 859), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(856, 860), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(703, 704), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(703, 4), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(704, 4), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(864, 4), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(861, 865), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(862, 866), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(863, 867), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(705, 706), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(705, 8), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(706, 8), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(871, 8), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(868, 872), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(869, 873), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(870, 874), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(707, 708), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(707, 14), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(708, 14), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(878, 14), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(875, 879), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(876, 880), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(877, 881), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(710, 712), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(710, 15), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(712, 15), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(885, 15), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(882, 886), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(883, 887), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(884, 888), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(714, 716), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(714, 16), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(716, 16), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(892, 16), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(889, 893), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(890, 894), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(891, 895), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(214), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[7](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(220), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[7](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(899, 900), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(899, 17), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(900, 17), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(901, 17), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(896, 902), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(897, 903), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(898, 904), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(226), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[8](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(232), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[8](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(908, 909), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(908, 19), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(909, 19), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(910, 19), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(905, 911), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(906, 912), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(907, 913), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(238), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[9](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(244), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[9](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(917, 918), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(917, 20), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(918, 20), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(919, 20), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(914, 920), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(915, 921), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(916, 922), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(250), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[10](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(256), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[10](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(926, 927), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(926, 21), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(927, 21), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(928, 21), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(923, 929), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(924, 930), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(925, 931), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(262), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[11](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(263), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[11](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(935, 936), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(935, 22), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(936, 22), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(937, 22), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(932, 938), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(933, 939), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(934, 940), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(264), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[12](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(270), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[12](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(944, 945), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(944, 23), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(945, 23), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(946, 23), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(941, 947), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(942, 948), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(943, 949), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(276), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[13](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(282), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[13](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(953, 954), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(953, 24), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(954, 24), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(955, 24), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(950, 956), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(951, 957), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(952, 958), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(288), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[14](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(294), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[14](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(962, 963), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(962, 25), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(963, 25), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(964, 25), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(959, 965), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(960, 966), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(961, 967), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(300), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[15](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(306), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[15](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(971, 972), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(971, 26), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(972, 26), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(973, 26), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(968, 974), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(969, 975), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(970, 976), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(312), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[16](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(318), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[16](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(980, 981), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(980, 12), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(981, 12), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(982, 12), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(977, 983), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(978, 984), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(979, 985), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(324), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[17](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(330), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[17](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(989, 990), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(989, 28), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(990, 28), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(991, 28), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(986, 992), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(987, 993), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(988, 994), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(336), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[18](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(342), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[18](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(998, 999), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(998, 29), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(999, 29), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(1000, 29), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(995, 1001), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(996, 1002), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(997, 1003), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(348), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[19](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(354), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[19](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(1007, 1008), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(1007, 30), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(1008, 30), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(1009, 30), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(1004, 1010), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(1005, 1011), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(1006, 1012), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(360), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[20](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(366), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[20](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(1016, 1017), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(1016, 31), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(1017, 31), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(1018, 31), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(1013, 1019), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(1014, 1020), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(1015, 1021), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(372), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[21](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(378), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[21](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(1025, 1026), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(1025, 32), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(1026, 32), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(1027, 32), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(1022, 1028), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(1023, 1029), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(1024, 1030), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(384), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[22](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(390), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[22](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(1034, 1035), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(1034, 33), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(1035, 33), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(1036, 33), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(1031, 1037), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(1032, 1038), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(1033, 1039), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(396), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[23](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(402), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[23](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(1043, 1044), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(1043, 34), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(1044, 34), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(1045, 34), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(1040, 1046), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(1041, 1047), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(1042, 1048), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(408), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[24](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(414), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[24](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(1052, 1053), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(1052, 35), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(1053, 35), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(1054, 35), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(1049, 1055), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(1050, 1056), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(1051, 1057), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(420), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[25](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(426), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[25](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(1061, 1062), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(1061, 36), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(1062, 36), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(1063, 36), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(1058, 1064), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(1059, 1065), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(1060, 1066), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Get(432), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_a[26](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(438), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/bit_and_elem(recursion::BitAndElem)/bits_b[26](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(1070, 1071), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(1070, 37), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(1071, 37), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(1072, 37), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(1067, 1073), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(1068, 1074), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(1069, 1075), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(316, 288), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(316, 38), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(288, 38), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(1079, 38), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(1076, 1080), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(1077, 1081), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(1078, 1082), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(289, 290), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(289, 39), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(290, 39), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(1086, 39), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(1083, 1087), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(1084, 1088), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(1085, 1089), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(291, 292), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(291, 40), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(292, 40), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(1093, 40), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(1090, 1094), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(1091, 1095), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(1092, 1096), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(293, 294), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Mul(293, 41), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Mul(294, 41), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Mul(1100, 41), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Add(1097, 1101), // zirgen/circuit/recursion/bits.cpp:88 +PolyExtStep::Add(1098, 1102), // zirgen/circuit/recursion/bits.cpp:89 +PolyExtStep::Add(1099, 1103), // zirgen/circuit/recursion/bits.cpp:90 +PolyExtStep::Sub(1104, 327), // zirgen/circuit/recursion/bits.cpp:92 +PolyExtStep::AndEqz(259, 1107), // zirgen/circuit/recursion/bits.cpp:92 +PolyExtStep::Sub(1105, 334), // zirgen/circuit/recursion/bits.cpp:93 +PolyExtStep::AndEqz(260, 1108), // zirgen/circuit/recursion/bits.cpp:93 +PolyExtStep::Sub(510, 286), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::AndEqz(261, 1109), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(511, 1106), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(262, 1110), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(263, 512), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(264, 513), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(265, 514), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(257, 318, 266), // components/mux.h:59 +PolyExtStep::Get(36), // top(recursion::Top)/code(recursion::Code)/inst(Mux)/macro_ops(recursion::MacroInst)/operand[2](Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(699, 980), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(700, 981), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(700, 2), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(981, 2), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1113, 2), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(699, 1114), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(980, 1115), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1112, 1116), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(701, 989), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(701, 4), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(989, 4), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1120, 4), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1117, 1121), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1118, 1122), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1119, 1123), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(702, 990), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(702, 8), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(990, 8), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1127, 8), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1124, 1128), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1125, 1129), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1126, 1130), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(703, 998), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(703, 14), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(998, 14), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1134, 14), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1131, 1135), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1132, 1136), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1133, 1137), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(704, 999), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(704, 15), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(999, 15), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1141, 15), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1138, 1142), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1139, 1143), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1140, 1144), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(705, 1007), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(705, 16), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(1007, 16), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1148, 16), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1145, 1149), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1146, 1150), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1147, 1151), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(706, 1008), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(706, 17), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(1008, 17), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1155, 17), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1152, 1156), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1153, 1157), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1154, 1158), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(707, 1016), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(707, 19), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(1016, 19), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1162, 19), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1159, 1163), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1160, 1164), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1161, 1165), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(708, 1017), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(708, 20), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(1017, 20), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1169, 20), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1166, 1170), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1167, 1171), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1168, 1172), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(710, 1025), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(710, 21), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(1025, 21), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1176, 21), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1173, 1177), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1174, 1178), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1175, 1179), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(712, 1026), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(712, 22), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(1026, 22), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1183, 22), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1180, 1184), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1181, 1185), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1182, 1186), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(714, 1034), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(714, 23), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(1034, 23), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1190, 23), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1187, 1191), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1188, 1192), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1189, 1193), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(716, 1035), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(716, 24), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(1035, 24), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1197, 24), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1194, 1198), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1195, 1199), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1196, 1200), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(899, 1043), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(899, 25), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(1043, 25), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1204, 25), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1201, 1205), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1202, 1206), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1203, 1207), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(900, 1044), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(900, 26), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(1044, 26), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1211, 26), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1208, 1212), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1209, 1213), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1210, 1214), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Sub(1215, 327), // zirgen/circuit/recursion/bits.cpp:48 +PolyExtStep::AndEqz(259, 1218), // zirgen/circuit/recursion/bits.cpp:48 +PolyExtStep::Sub(1216, 334), // zirgen/circuit/recursion/bits.cpp:49 +PolyExtStep::AndEqz(268, 1219), // zirgen/circuit/recursion/bits.cpp:49 +PolyExtStep::Mul(908, 1052), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(909, 1053), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(909, 2), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(1053, 2), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1221, 2), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(908, 1222), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1052, 1223), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1220, 1224), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(917, 1061), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(917, 4), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(1061, 4), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1228, 4), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1225, 1229), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1226, 1230), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1227, 1231), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(918, 1062), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(918, 8), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(1062, 8), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1235, 8), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1232, 1236), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1233, 1237), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1234, 1238), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(926, 1070), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(926, 14), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(1070, 14), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1242, 14), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1239, 1243), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1240, 1244), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1241, 1245), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(927, 1071), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(927, 15), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(1071, 15), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1249, 15), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1246, 1250), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1247, 1251), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1248, 1252), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(935, 316), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(935, 16), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(316, 16), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1256, 16), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1253, 1257), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1254, 1258), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1255, 1259), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(936, 288), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(936, 17), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(288, 17), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1263, 17), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1260, 1264), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1261, 1265), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1262, 1266), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(944, 289), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(944, 19), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(289, 19), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1270, 19), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1267, 1271), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1268, 1272), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1269, 1273), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(945, 290), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(945, 20), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(290, 20), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1277, 20), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1274, 1278), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1275, 1279), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1276, 1280), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(953, 291), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(953, 21), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(291, 21), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1284, 21), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1281, 1285), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1282, 1286), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1283, 1287), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(954, 292), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(954, 22), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(292, 22), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1291, 22), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1288, 1292), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1289, 1293), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1290, 1294), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(962, 293), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(962, 23), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(293, 23), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1298, 23), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1295, 1299), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1296, 1300), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1297, 1301), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(963, 294), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(963, 24), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(294, 24), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1305, 24), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1302, 1306), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1303, 1307), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1304, 1308), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(971, 295), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(971, 25), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Mul(295, 25), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1312, 25), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1309, 1313), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1310, 1314), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1311, 1315), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(972, 296), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Mul(296, 26), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Mul(1319, 26), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Add(1316, 975), // zirgen/circuit/recursion/bits.cpp:44 +PolyExtStep::Add(1317, 1320), // zirgen/circuit/recursion/bits.cpp:45 +PolyExtStep::Add(1318, 1321), // zirgen/circuit/recursion/bits.cpp:46 +PolyExtStep::Sub(1322, 328), // zirgen/circuit/recursion/bits.cpp:48 +PolyExtStep::AndEqz(269, 1325), // zirgen/circuit/recursion/bits.cpp:48 +PolyExtStep::Sub(1323, 336), // zirgen/circuit/recursion/bits.cpp:49 +PolyExtStep::AndEqz(270, 1326), // zirgen/circuit/recursion/bits.cpp:49 +PolyExtStep::Mul(1324, 12), // zirgen/circuit/recursion/bits.cpp:54 +PolyExtStep::Add(1327, 1217), // zirgen/circuit/recursion/bits.cpp:54 +PolyExtStep::AndEqz(0, 1109), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(511, 1328), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(272, 1329), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(273, 512), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(274, 513), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(275, 514), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(271, 1111, 276), // zirgen/circuit/recursion/bits.cpp:52 +PolyExtStep::Sub(1, 1111), // zirgen/circuit/recursion/bits.cpp:57 +PolyExtStep::Mul(1324, 2), // zirgen/circuit/recursion/bits.cpp:61 +PolyExtStep::Mul(1217, 2), // zirgen/circuit/recursion/bits.cpp:60 +PolyExtStep::Add(327, 334), // zirgen/circuit/recursion/bits.cpp:60 +PolyExtStep::Add(328, 336), // zirgen/circuit/recursion/bits.cpp:61 +PolyExtStep::Sub(1333, 1332), // zirgen/circuit/recursion/bits.cpp:60 +PolyExtStep::Sub(1334, 1331), // zirgen/circuit/recursion/bits.cpp:61 +PolyExtStep::Sub(511, 1335), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(272, 1337), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(512, 1336), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(278, 1338), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(279, 513), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(280, 514), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(277, 1330, 281), // zirgen/circuit/recursion/bits.cpp:57 +PolyExtStep::AndCond(267, 475, 282), // components/mux.h:59 +PolyExtStep::Mul(287, 16), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(430, 17), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(505, 19), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(476, 20), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(477, 21), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(478, 22), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(479, 23), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(480, 24), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(481, 25), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(482, 26), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(292, 2), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(293, 4), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(294, 8), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(295, 14), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(296, 15), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(291, 1349), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1354, 1350), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1355, 1351), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1356, 1352), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1357, 1353), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1358, 1339), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1359, 1340), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1360, 1341), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1361, 1342), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1362, 1343), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1363, 1344), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1364, 1345), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1365, 1346), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1366, 1347), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1367, 1348), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Sub(0, 1368), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(1369, 27), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(1370, 324), // zirgen/circuit/recursion/sha.cpp:135 +PolyExtStep::Mul(1371, 13), // zirgen/circuit/recursion/sha.cpp:135 +PolyExtStep::Sub(1, 1372), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::Mul(1372, 1373), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::AndEqz(259, 1374), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::Mul(484, 2), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(485, 4), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(619, 8), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(694, 14), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(665, 15), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(666, 16), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(667, 17), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(668, 19), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(669, 20), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(670, 21), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(671, 22), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(672, 23), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(673, 24), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(674, 25), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(808, 26), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(483, 1375), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1390, 1376), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1391, 1377), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1392, 1378), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1393, 1379), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1394, 1380), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1395, 1381), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1396, 1382), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1397, 1383), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1398, 1384), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1399, 1385), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1400, 1386), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1401, 1387), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1402, 1388), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1403, 1389), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Sub(1370, 1404), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(1405, 27), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(1406, 325), // zirgen/circuit/recursion/sha.cpp:139 +PolyExtStep::Mul(1407, 13), // zirgen/circuit/recursion/sha.cpp:139 +PolyExtStep::Sub(1, 1408), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::Mul(1408, 1409), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::AndEqz(284, 1410), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::Mul(516, 2), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(517, 4), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(518, 8), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(519, 14), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(521, 15), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(523, 16), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(525, 17), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(527, 19), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(698, 20), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(699, 21), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(700, 22), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(701, 23), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(702, 24), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(703, 25), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(704, 26), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(515, 1411), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1426, 1412), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1427, 1413), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1428, 1414), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1429, 1415), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1430, 1416), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1431, 1417), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1432, 1418), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1433, 1419), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1434, 1420), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1435, 1421), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1436, 1422), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1437, 1423), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1438, 1424), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1439, 1425), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Sub(327, 1440), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(1441, 27), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(1442, 320), // zirgen/circuit/recursion/sha.cpp:135 +PolyExtStep::Mul(1443, 13), // zirgen/circuit/recursion/sha.cpp:135 +PolyExtStep::Sub(1, 1444), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::Mul(1444, 1445), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::AndEqz(285, 1446), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::Add(328, 1442), // zirgen/circuit/recursion/sha.cpp:137 +PolyExtStep::Mul(706, 2), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(707, 4), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(708, 8), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(710, 14), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(716, 17), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(899, 19), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(900, 20), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(908, 21), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(909, 22), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(917, 23), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(918, 24), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(926, 25), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(927, 26), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(705, 1448), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1461, 1449), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1462, 1450), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1463, 1451), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1464, 887), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1465, 893), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1466, 1452), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1467, 1453), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1468, 1454), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1469, 1455), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1470, 1456), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1471, 1457), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1472, 1458), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1473, 1459), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1474, 1460), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Sub(1447, 1475), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(1476, 27), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(1477, 321), // zirgen/circuit/recursion/sha.cpp:139 +PolyExtStep::Mul(1478, 13), // zirgen/circuit/recursion/sha.cpp:139 +PolyExtStep::Sub(1, 1479), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::Mul(1479, 1480), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::AndEqz(286, 1481), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::Mul(945, 2), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(953, 4), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(954, 8), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(962, 14), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(963, 15), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(971, 16), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(972, 17), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(980, 19), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(981, 20), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(989, 21), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(990, 22), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(998, 23), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(999, 24), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(1007, 25), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(1008, 26), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(944, 1482), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1497, 1483), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1498, 1484), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1499, 1485), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1500, 1486), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1501, 1487), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1502, 1488), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1503, 1489), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1504, 1490), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1505, 1491), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1506, 1492), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1507, 1493), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1508, 1494), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1509, 1495), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1510, 1496), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Sub(334, 1511), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(1512, 27), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(1513, 322), // zirgen/circuit/recursion/sha.cpp:135 +PolyExtStep::Mul(1514, 13), // zirgen/circuit/recursion/sha.cpp:135 +PolyExtStep::Sub(1, 1515), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::Mul(1515, 1516), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::AndEqz(287, 1517), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::Add(336, 1513), // zirgen/circuit/recursion/sha.cpp:137 +PolyExtStep::Mul(1017, 2), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(1025, 4), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(1026, 8), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(1034, 14), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(1035, 15), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(1043, 16), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(1044, 17), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(1052, 19), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(1053, 20), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(1061, 21), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(1062, 22), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(1070, 23), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(1071, 24), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(316, 25), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(288, 26), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1016, 1519), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1534, 1520), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1535, 1521), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1536, 1522), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1537, 1523), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1538, 1524), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1539, 1525), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1540, 1526), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1541, 1527), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1542, 1528), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1543, 1529), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1544, 1530), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1545, 1531), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1546, 1532), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(1547, 1533), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Sub(1518, 1548), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(1549, 27), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(1550, 323), // zirgen/circuit/recursion/sha.cpp:139 +PolyExtStep::Mul(1551, 13), // zirgen/circuit/recursion/sha.cpp:139 +PolyExtStep::Sub(1, 1552), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::Mul(1552, 1553), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::AndEqz(288, 1554), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::AndCond(283, 506, 289), // components/mux.h:59 +PolyExtStep::AndEqz(0, 1374), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::AndEqz(291, 1410), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::Get(74), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[0](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(80), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[1](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(86), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[2](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(92), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[3](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(98), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[4](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(104), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[5](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(110), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[6](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(116), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[7](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(122), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[8](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(128), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[9](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(134), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[10](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(140), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[11](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(146), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[12](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(152), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[13](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(158), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[14](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(164), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[15](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(170), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[16](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(176), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[17](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(182), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[18](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(188), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[19](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(194), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[20](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(200), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[21](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(206), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[22](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(212), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[23](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(218), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[24](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(224), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[25](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(230), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[26](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(236), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[27](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(242), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[28](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(248), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[29](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(254), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[30](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(260), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[31](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(75), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[0](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(81), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[1](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(87), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[2](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(93), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[3](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(99), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[4](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(105), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[5](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(111), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[6](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(117), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[7](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(123), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[8](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(129), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[9](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(135), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[10](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(141), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[11](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(147), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[12](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(153), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[13](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(159), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[14](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(165), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[15](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(171), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[16](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(177), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[17](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(183), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[18](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(189), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[19](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(195), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[20](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(201), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[21](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(207), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[22](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(213), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[23](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(219), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[24](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(225), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[25](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(231), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[26](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(237), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[27](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(243), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[28](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(249), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[29](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(255), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[30](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(261), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[31](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(1556, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1557, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1558, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1559, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1560, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1561, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1562, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1563, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1564, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1565, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1566, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1567, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1568, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1569, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1570, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1572, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1573, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1574, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1575, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1576, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1577, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1578, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1579, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1580, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1581, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1582, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1583, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1584, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1585, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1586, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1588, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1589, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1590, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1591, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1592, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1593, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1594, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1595, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1596, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1597, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1598, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1599, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1600, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1601, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1602, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1604, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1605, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1606, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1607, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1608, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1609, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1610, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1611, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1612, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1613, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1614, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1615, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1616, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1617, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1618, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1555, 1619), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1571, 1634), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1587, 1649), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1603, 1664), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1679, 1620), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1680, 1635), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1681, 1650), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1682, 1665), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1683, 1621), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1684, 1636), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1685, 1651), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1686, 1666), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1687, 1622), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1688, 1637), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1689, 1652), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1690, 1667), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1691, 1623), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1692, 1638), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1693, 1653), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1694, 1668), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1695, 1624), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1696, 1639), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1697, 1654), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1698, 1669), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1699, 1625), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1700, 1640), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1701, 1655), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1702, 1670), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1703, 1626), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1704, 1641), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1705, 1656), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1706, 1671), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1707, 1627), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1708, 1642), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1709, 1657), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1710, 1672), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1711, 1628), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1712, 1643), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1713, 1658), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1714, 1673), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1715, 1629), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1716, 1644), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1717, 1659), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1718, 1674), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1719, 1630), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1720, 1645), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1721, 1660), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1722, 1675), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1723, 1631), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1724, 1646), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1725, 1661), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1726, 1676), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1727, 1632), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1728, 1647), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1729, 1662), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1730, 1677), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1733, 1663), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1734, 1678), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1731, 1633), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1732, 1648), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1737, 1735), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(1738, 1736), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Sub(1739, 1440), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(1741, 27), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(1742, 320), // zirgen/circuit/recursion/sha.cpp:135 +PolyExtStep::Mul(1743, 13), // zirgen/circuit/recursion/sha.cpp:135 +PolyExtStep::Sub(1, 1744), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::Mul(1744, 1745), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::AndEqz(292, 1746), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::Add(1740, 1742), // zirgen/circuit/recursion/sha.cpp:137 +PolyExtStep::Sub(1747, 1475), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(1748, 27), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(1749, 321), // zirgen/circuit/recursion/sha.cpp:139 +PolyExtStep::Mul(1750, 13), // zirgen/circuit/recursion/sha.cpp:139 +PolyExtStep::Sub(1, 1751), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::Mul(1751, 1752), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::AndEqz(293, 1753), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::Get(268), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[0](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(274), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[1](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(280), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[2](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(286), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[3](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(292), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[4](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(298), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[5](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(304), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[6](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(310), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[7](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(316), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[8](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(322), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[9](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(328), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[10](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(334), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[11](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(340), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[12](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(346), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[13](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(352), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[14](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(358), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[15](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(364), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[16](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(370), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[17](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(376), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[18](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(382), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[19](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(388), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[20](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(394), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[21](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(400), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[22](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(406), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[23](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(412), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[24](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(418), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[25](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(424), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[26](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(430), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[27](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(436), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[28](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(442), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[29](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(448), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[30](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(454), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[31](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(269), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[0](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(275), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[1](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(281), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[2](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(287), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[3](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(293), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[4](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(299), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[5](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(305), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[6](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(311), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[7](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(317), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[8](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(323), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[9](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(329), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[10](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(335), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[11](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(341), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[12](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(347), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[13](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(353), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[14](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(359), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[15](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(365), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[16](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(371), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[17](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(377), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[18](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(383), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[19](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(389), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[20](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(395), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[21](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(401), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[22](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(407), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[23](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(413), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[24](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(419), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[25](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(425), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[26](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(431), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[27](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(437), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[28](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(443), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[29](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(449), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[30](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(455), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_fini(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[31](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(1755, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1756, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1757, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1758, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1759, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1760, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1761, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1762, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1763, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1764, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1765, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1766, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1767, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1768, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1769, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1771, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1772, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1773, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1774, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1775, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1776, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1777, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1778, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1779, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1780, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1781, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1782, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1783, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1784, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1785, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1787, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1788, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1789, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1790, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1791, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1792, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1793, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1794, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1795, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1796, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1797, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1798, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1799, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1800, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1801, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1803, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1804, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1805, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1806, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1807, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1808, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1809, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1810, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1811, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1812, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1813, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1814, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1815, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1816, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(1817, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1754, 1818), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1770, 1833), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1786, 1848), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1802, 1863), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1878, 1819), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1879, 1834), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1880, 1849), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1881, 1864), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1882, 1820), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1883, 1835), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1884, 1850), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1885, 1865), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1886, 1821), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1887, 1836), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1888, 1851), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1889, 1866), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1890, 1822), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1891, 1837), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1892, 1852), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1893, 1867), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1894, 1823), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1895, 1838), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1896, 1853), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1897, 1868), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1898, 1824), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1899, 1839), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1900, 1854), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1901, 1869), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1902, 1825), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1903, 1840), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1904, 1855), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1905, 1870), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1906, 1826), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1907, 1841), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1908, 1856), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1909, 1871), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1910, 1827), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1911, 1842), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1912, 1857), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1913, 1872), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1914, 1828), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1915, 1843), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1916, 1858), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1917, 1873), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1918, 1829), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1919, 1844), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1920, 1859), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1921, 1874), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1922, 1830), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1923, 1845), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1924, 1860), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1925, 1875), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1926, 1831), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1927, 1846), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1928, 1861), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1929, 1876), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1932, 1862), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1933, 1877), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1930, 1832), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1931, 1847), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(1936, 1934), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(1937, 1935), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Sub(1938, 1511), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(1940, 27), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(1941, 322), // zirgen/circuit/recursion/sha.cpp:135 +PolyExtStep::Mul(1942, 13), // zirgen/circuit/recursion/sha.cpp:135 +PolyExtStep::Sub(1, 1943), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::Mul(1943, 1944), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::AndEqz(294, 1945), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::Add(1939, 1941), // zirgen/circuit/recursion/sha.cpp:137 +PolyExtStep::Sub(1946, 1548), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(1947, 27), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(1948, 323), // zirgen/circuit/recursion/sha.cpp:139 +PolyExtStep::Mul(1949, 13), // zirgen/circuit/recursion/sha.cpp:139 +PolyExtStep::Sub(1, 1950), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::Mul(1950, 1951), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::AndEqz(295, 1952), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::Mul(698, 2), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Mul(699, 4), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Mul(700, 8), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Mul(701, 14), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Mul(702, 15), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Mul(703, 16), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Mul(704, 17), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Mul(900, 2), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Mul(908, 4), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Mul(909, 8), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Mul(917, 14), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Mul(918, 15), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Mul(926, 16), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Mul(927, 17), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Add(527, 1953), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Add(899, 1960), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Add(1967, 1954), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Add(1968, 1961), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Add(1969, 1955), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Add(1970, 1962), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Add(1971, 1956), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Add(1972, 1963), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Add(1973, 1957), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Add(1974, 1964), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Add(1975, 1958), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Add(1976, 1965), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Add(1977, 1959), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Add(1978, 1966), // zirgen/circuit/recursion/sha.cpp:125 +PolyExtStep::Mul(1432, 19), // zirgen/circuit/recursion/sha.cpp:258 +PolyExtStep::Mul(1467, 19), // zirgen/circuit/recursion/sha.cpp:258 +PolyExtStep::Add(1979, 1981), // zirgen/circuit/recursion/sha.cpp:258 +PolyExtStep::Add(1980, 1982), // zirgen/circuit/recursion/sha.cpp:258 +PolyExtStep::AndEqz(296, 854), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(327, 1984), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(297, 1985), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(328, 1983), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(298, 1986), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(299, 329), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(300, 330), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Mul(1503, 19), // zirgen/circuit/recursion/sha.cpp:259 +PolyExtStep::Mul(1540, 19), // zirgen/circuit/recursion/sha.cpp:259 +PolyExtStep::Add(1160, 1987), // zirgen/circuit/recursion/sha.cpp:259 +PolyExtStep::Add(1268, 1988), // zirgen/circuit/recursion/sha.cpp:259 +PolyExtStep::AndEqz(301, 855), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(334, 1990), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(302, 1991), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(336, 1989), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(303, 1992), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(304, 338), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(305, 509), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(290, 508, 306), // components/mux.h:59 +PolyExtStep::Mul(327, 42), // zirgen/circuit/recursion/sha.cpp:189 +PolyExtStep::Mul(669, 2), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(670, 4), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(671, 8), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(672, 14), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(673, 15), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(674, 16), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(808, 17), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(668, 1994), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(2001, 1995), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(2002, 1996), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(2003, 1997), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(2004, 1998), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(2005, 1999), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(2006, 2000), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Sub(1993, 2007), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(2008, 18), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(2009, 1396), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(2010, 18), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(476, 2), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(477, 4), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(478, 8), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(479, 14), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(480, 15), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(481, 16), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Mul(482, 17), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(505, 2012), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(2019, 2013), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(2020, 2014), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(2021, 2015), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(2022, 2016), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(2023, 2017), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Add(2024, 2018), // zirgen/circuit/recursion/sha.cpp:114 +PolyExtStep::Sub(2011, 2025), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(2026, 18), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(2027, 1360), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(2028, 18), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::AndEqz(0, 2029), // zirgen/circuit/recursion/sha.cpp:194 +PolyExtStep::Add(668, 669), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(294, 295), // zirgen/circuit/recursion/sha.cpp:203 +PolyExtStep::Add(2030, 670), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2031, 296), // zirgen/circuit/recursion/sha.cpp:203 +PolyExtStep::Add(2033, 287), // zirgen/circuit/recursion/sha.cpp:203 +PolyExtStep::Add(2032, 671), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2035, 672), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2036, 673), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2037, 674), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2038, 808), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2039, 483), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2040, 484), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2041, 485), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2042, 619), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2043, 694), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2044, 665), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2045, 666), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2046, 667), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2047, 505), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2048, 476), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2049, 477), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2050, 478), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2051, 479), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2052, 480), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2053, 481), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2054, 482), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2055, 291), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2056, 292), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Add(2057, 293), // zirgen/circuit/recursion/sha.cpp:207 +PolyExtStep::Sub(2034, 324), // zirgen/circuit/recursion/sha.cpp:224 +PolyExtStep::Mul(2059, 2058), // zirgen/circuit/recursion/sha.cpp:224 +PolyExtStep::AndEqz(308, 2060), // zirgen/circuit/recursion/sha.cpp:224 +PolyExtStep::AndEqz(309, 430), // zirgen/circuit/recursion/sha.cpp:226 +PolyExtStep::AndCond(259, 1330, 310), // zirgen/circuit/recursion/sha.cpp:187 +PolyExtStep::Sub(327, 2007), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(2061, 18), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(2062, 1396), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(2063, 18), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(0, 2064), // zirgen/circuit/recursion/sha.cpp:144 +PolyExtStep::AndEqz(0, 2065), // zirgen/circuit/recursion/sha.cpp:144 +PolyExtStep::Sub(328, 2025), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(2066, 18), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(2067, 1360), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(2068, 18), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(0, 2069), // zirgen/circuit/recursion/sha.cpp:145 +PolyExtStep::AndEqz(312, 2070), // zirgen/circuit/recursion/sha.cpp:145 +PolyExtStep::AndEqz(313, 324), // components/bits.h:78 +PolyExtStep::AndCond(311, 1111, 314), // zirgen/circuit/recursion/sha.cpp:228 +PolyExtStep::AndEqz(315, 325), // components/bits.h:78 +PolyExtStep::Get(71), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[0](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(77), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[1](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(83), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[2](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(89), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[3](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(95), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[4](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(101), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[5](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(107), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[6](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(113), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[7](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(119), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[8](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(125), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[9](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(131), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[10](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(137), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[11](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(143), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[12](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(149), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[13](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(155), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[14](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(161), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[15](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(167), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[16](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(173), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[17](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(179), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[18](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(185), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[19](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(191), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[20](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(197), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[21](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(203), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[22](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(209), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[23](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(215), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[24](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(221), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[25](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(227), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[26](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(233), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[27](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(239), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[28](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(245), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[29](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(251), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[30](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(257), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[31](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(265), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[0](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(271), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[1](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(277), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[2](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(283), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[3](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(289), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[4](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(295), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[5](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(301), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[6](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(307), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[7](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(313), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[8](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(319), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[9](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(325), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[10](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(331), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[11](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(337), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[12](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(343), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[13](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(349), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[14](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(355), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[15](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(361), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[16](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(367), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[17](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(373), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[18](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(379), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[19](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(385), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[20](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(391), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[21](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(397), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[22](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(403), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[23](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(409), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[24](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(415), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[25](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(421), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[26](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(427), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[27](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(433), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[28](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(439), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[29](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(445), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[30](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(451), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[31](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(266), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[0](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(272), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[1](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(278), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[2](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(284), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[3](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(290), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[4](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(296), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[5](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(302), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[6](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(308), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[7](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(314), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[8](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(320), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[9](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(326), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[10](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(332), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[11](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(338), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[12](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(344), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[13](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(350), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[14](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(356), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[15](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(362), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[16](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(368), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[17](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(374), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[18](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(380), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[19](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(386), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[20](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(392), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[21](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(398), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[22](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(404), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[23](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(410), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[24](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(416), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[25](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(422), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[26](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(428), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[27](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(434), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[28](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(440), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[29](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(446), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[30](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(452), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[31](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(72), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[0](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(78), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[1](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(84), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[2](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(90), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[3](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(96), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[4](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(102), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[5](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(108), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[6](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(114), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[7](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(120), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[8](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(126), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[9](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(132), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[10](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(138), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[11](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(144), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[12](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(150), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[13](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(156), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[14](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(162), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[15](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(168), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[16](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(174), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[17](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(180), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[18](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(186), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[19](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(192), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[20](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(198), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[21](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(204), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[22](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(210), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[23](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(216), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[24](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(222), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[25](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(228), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[26](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(234), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[27](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(240), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[28](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(246), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[29](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(252), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[30](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(258), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[31](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(267), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[0](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(273), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[1](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(279), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[2](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(285), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[3](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(291), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[4](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(297), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[5](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(303), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[6](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(309), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[7](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(315), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[8](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(321), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[9](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(327), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[10](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(333), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[11](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(339), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[12](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(345), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[13](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(351), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[14](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(357), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[15](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(363), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[16](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(369), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[17](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(375), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[18](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(381), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[19](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(387), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[20](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(393), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[21](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(399), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[22](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(405), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[23](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(411), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[24](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(417), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[25](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(423), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[26](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(429), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[27](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(435), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[28](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(441), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[29](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(447), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[30](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(453), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/e[31](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(73), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[0](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(79), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[1](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(85), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[2](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(91), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[3](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(97), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[4](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(103), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[5](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(109), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[6](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(115), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[7](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(121), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[8](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(127), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[9](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(133), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[10](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(139), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[11](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(145), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[12](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(151), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[13](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(157), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[14](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(163), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[15](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(169), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[16](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(175), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[17](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(181), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[18](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(187), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[19](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(193), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[20](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(199), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[21](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(205), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[22](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(211), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[23](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(217), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[24](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(223), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[25](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(229), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[26](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(235), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[27](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(241), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[28](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(247), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[29](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(253), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[30](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(259), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_load(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/a[31](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(2071, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2071, 2167), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2072, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2072, 2168), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2073, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2073, 2169), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2074, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2074, 2170), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2075, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2075, 2171), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2076, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2076, 2172), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2077, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2077, 2173), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2078, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2078, 2174), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2079, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2079, 2175), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2080, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2080, 2176), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2081, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2081, 2177), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2082, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2082, 2178), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2083, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2083, 2179), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2084, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2084, 2180), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2085, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2085, 2181), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2086, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2086, 2182), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2087, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2087, 2183), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2088, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2088, 2184), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2089, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2089, 2185), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2090, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2090, 2186), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2091, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2091, 2187), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2092, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2092, 2188), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2093, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2093, 2189), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2094, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2094, 2190), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2095, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2095, 2191), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2096, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2096, 2192), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2097, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2097, 2193), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2098, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2098, 2194), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2099, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2099, 2195), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2100, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2100, 2196), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2101, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2101, 2197), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2102, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2102, 2198), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2103, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2103, 2135), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2104, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2104, 2136), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2105, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2105, 2137), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2106, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2106, 2138), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2107, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2107, 2139), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2108, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2108, 2140), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2109, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2109, 2141), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2110, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2110, 2142), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2111, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2111, 2143), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2112, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2112, 2144), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2113, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2113, 2145), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2114, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2114, 2146), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2115, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2115, 2147), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2116, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2116, 2148), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2117, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2117, 2149), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2118, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2118, 2150), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2119, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2119, 2151), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2120, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2120, 2152), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2121, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2121, 2153), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2122, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2122, 2154), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2123, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2123, 2155), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2124, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2124, 2156), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2125, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2125, 2157), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2126, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2126, 2158), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2127, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2127, 2159), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2128, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2128, 2160), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2129, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2129, 2161), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2130, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2130, 2162), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2131, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2131, 2163), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2132, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2132, 2164), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2133, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2133, 2165), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2134, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2134, 2166), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2263, 2080), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2264, 2231), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2265, 2081), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2266, 2232), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2267, 2082), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2268, 2233), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2269, 2083), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2270, 2234), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2271, 2084), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2272, 2235), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2273, 2085), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2274, 2236), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2275, 2086), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2276, 2237), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2277, 2087), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2278, 2238), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2279, 2088), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2280, 2239), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2281, 2089), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2282, 2240), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2283, 2090), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2284, 2241), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2285, 2091), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2286, 2242), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2287, 2092), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2288, 2243), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2289, 2093), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2290, 2244), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2291, 2094), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2292, 2245), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2293, 2095), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2294, 2246), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2295, 2096), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2296, 2247), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2297, 2097), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2298, 2248), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2299, 2098), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2300, 2249), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2301, 2099), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2302, 2250), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2303, 2100), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2304, 2251), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2305, 2101), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2306, 2252), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2307, 2102), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2308, 2253), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2309, 2071), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2310, 2254), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2311, 2072), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2312, 2255), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2313, 2073), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2314, 2256), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2315, 2074), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2316, 2257), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2317, 2075), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2318, 2258), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2319, 2076), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2320, 2259), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2321, 2077), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2322, 2260), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2323, 2078), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2324, 2261), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2325, 2079), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2326, 2262), // zirgen/circuit/recursion/sha.cpp:66 +PolyExtStep::Mul(2327, 2117), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2329, 2118), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2331, 2119), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2333, 2120), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2335, 2121), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2337, 2122), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2339, 2123), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2341, 2124), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2343, 2125), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2345, 2126), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2347, 2127), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2349, 2128), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2351, 2129), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2353, 2130), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2355, 2131), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2357, 2132), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2359, 2133), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2361, 2134), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2363, 2103), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2365, 2104), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2367, 2105), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2369, 2106), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2371, 2107), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2373, 2108), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2375, 2109), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2377, 2110), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2379, 2111), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2381, 2112), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2383, 2113), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2385, 2114), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2387, 2115), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2389, 2116), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(1, 2071), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2072), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2073), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2074), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2075), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2076), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2077), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2078), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2079), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2080), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2081), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2082), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2083), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2084), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2085), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2086), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2087), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2088), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2089), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2090), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2091), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2092), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2093), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2094), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2095), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2096), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2097), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2098), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2099), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2100), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2101), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2102), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2103), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2104), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2105), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2106), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2107), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2108), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2109), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2110), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2111), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2112), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2113), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2114), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2115), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2116), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2117), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2118), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2119), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2120), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2121), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2122), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2123), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2124), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2125), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2126), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2127), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2128), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2129), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2130), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2131), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2132), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2133), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2134), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(1, 2167), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2168), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2169), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2170), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2171), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2172), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2173), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2174), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2175), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2176), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2177), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2178), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2179), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2180), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2181), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2182), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2183), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2184), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2185), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2186), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2187), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2188), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2189), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2190), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2191), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2192), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2193), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2194), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2195), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2196), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2197), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2198), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2231), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2232), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2233), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2234), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2235), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2236), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2237), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2238), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2239), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2240), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2241), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2242), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2243), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2244), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2245), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2246), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2247), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2248), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2249), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2250), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2251), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2252), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2253), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2254), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2255), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2256), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2257), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2258), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2259), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2260), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2261), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Sub(1, 2262), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2071, 2080), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2072, 2081), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2073, 2082), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2074, 2083), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2075, 2084), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2076, 2085), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2077, 2086), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2078, 2087), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2079, 2088), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2080, 2089), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2081, 2090), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2082, 2091), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2083, 2092), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2084, 2093), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2085, 2094), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2086, 2095), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2087, 2096), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2088, 2097), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2089, 2098), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2090, 2099), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2091, 2100), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2092, 2101), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2093, 2102), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2094, 2071), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2095, 2072), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2096, 2073), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2097, 2074), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2098, 2075), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2099, 2076), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2100, 2077), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2101, 2078), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2102, 2079), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2103, 2117), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2104, 2118), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2105, 2119), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2106, 2120), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2107, 2121), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2108, 2122), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2109, 2123), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2110, 2124), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2111, 2125), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2112, 2126), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2113, 2127), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2114, 2128), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2115, 2129), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2116, 2130), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2117, 2131), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2118, 2132), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2119, 2133), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2120, 2134), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2121, 2103), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2122, 2104), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2123, 2105), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2124, 2106), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2125, 2107), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2126, 2108), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2127, 2109), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2128, 2110), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2129, 2111), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2130, 2112), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2131, 2113), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2132, 2114), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2133, 2115), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2134, 2116), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2071, 2551), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2072, 2552), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2073, 2553), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2074, 2554), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2075, 2555), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2076, 2556), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2077, 2557), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2078, 2558), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2079, 2559), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2080, 2560), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2081, 2561), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2082, 2562), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2083, 2563), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2084, 2564), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2085, 2565), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2086, 2566), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2087, 2567), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2088, 2568), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2089, 2569), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2090, 2570), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2091, 2571), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2092, 2572), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2093, 2573), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2094, 2574), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2095, 2575), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2096, 2576), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2097, 2577), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2098, 2578), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2099, 2579), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2100, 2580), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2101, 2581), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2102, 2582), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2264, 2583), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2266, 2584), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2268, 2585), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2270, 2586), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2272, 2587), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2274, 2588), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2276, 2589), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2278, 2590), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2280, 2591), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2282, 2592), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2284, 2593), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2286, 2594), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2288, 2595), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2290, 2596), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2292, 2597), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2294, 2598), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2296, 2599), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2298, 2600), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2300, 2601), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2302, 2602), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2304, 2603), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2306, 2604), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2308, 2605), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2310, 2606), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2312, 2607), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2314, 2608), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2316, 2609), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2318, 2610), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2320, 2611), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2322, 2612), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2324, 2613), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2326, 2614), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2487, 2167), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2488, 2168), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2489, 2169), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2490, 2170), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2491, 2171), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2492, 2172), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2493, 2173), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2494, 2174), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2495, 2175), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2496, 2176), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2497, 2177), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2498, 2178), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2499, 2179), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2500, 2180), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2501, 2181), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2502, 2182), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2503, 2183), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2504, 2184), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2505, 2185), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2506, 2186), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2507, 2187), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2508, 2188), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2509, 2189), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2510, 2190), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2511, 2191), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2512, 2192), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2513, 2193), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2514, 2194), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2515, 2195), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2516, 2196), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2517, 2197), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2518, 2198), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2679, 2231), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2680, 2232), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2681, 2233), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2682, 2234), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2683, 2235), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2684, 2236), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2685, 2237), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2686, 2238), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2687, 2239), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2688, 2240), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2689, 2241), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2690, 2242), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2691, 2243), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2692, 2244), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2693, 2245), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2694, 2246), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2695, 2247), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2696, 2248), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2697, 2249), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2698, 2250), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2699, 2251), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2700, 2252), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2701, 2253), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2702, 2254), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2703, 2255), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2704, 2256), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2705, 2257), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2706, 2258), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2707, 2259), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2708, 2260), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2709, 2261), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2710, 2262), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2743, 2231), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2744, 2232), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2745, 2233), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2746, 2234), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2747, 2235), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2748, 2236), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2749, 2237), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2750, 2238), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2751, 2239), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2752, 2240), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2753, 2241), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2754, 2242), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2755, 2243), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2756, 2244), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2757, 2245), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2758, 2246), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2759, 2247), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2760, 2248), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2761, 2249), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2762, 2250), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2763, 2251), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2764, 2252), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2765, 2253), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2766, 2254), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2767, 2255), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2768, 2256), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2769, 2257), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2770, 2258), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2771, 2259), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2772, 2260), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2773, 2261), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2774, 2262), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(2519, 2199), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2520, 2200), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2521, 2201), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2522, 2202), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2523, 2203), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2524, 2204), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2525, 2205), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2526, 2206), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2527, 2207), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2528, 2208), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2529, 2209), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2530, 2210), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2531, 2211), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2532, 2212), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2533, 2213), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2534, 2214), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2535, 2215), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2536, 2216), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2537, 2217), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2538, 2218), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2539, 2219), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2540, 2220), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2541, 2221), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2542, 2222), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2543, 2223), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2544, 2224), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2545, 2225), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2546, 2226), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2547, 2227), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2548, 2228), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2549, 2229), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Mul(2550, 2230), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Sub(2615, 2391), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2616, 2393), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2617, 2395), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2618, 2397), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2619, 2399), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2620, 2401), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2621, 2403), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2622, 2405), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2623, 2407), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2624, 2409), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2625, 2411), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2626, 2413), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2627, 2415), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2628, 2417), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2629, 2419), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2630, 2421), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2631, 2423), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2632, 2425), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2633, 2427), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2634, 2429), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2635, 2431), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2636, 2433), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2637, 2435), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2638, 2437), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2639, 2439), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2640, 2441), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2641, 2443), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2642, 2445), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2643, 2447), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2644, 2449), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2645, 2451), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2646, 2453), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2647, 2455), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2648, 2456), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2649, 2457), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2650, 2458), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2651, 2459), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2652, 2460), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2653, 2461), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2654, 2462), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2655, 2463), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2656, 2464), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2657, 2465), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2658, 2466), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2659, 2467), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2660, 2468), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2661, 2469), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2662, 2470), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2663, 2471), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2664, 2472), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2665, 2473), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2666, 2474), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2667, 2475), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2668, 2476), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2669, 2477), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2670, 2478), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2671, 2479), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2672, 2480), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2673, 2481), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2674, 2482), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2675, 2483), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2676, 2484), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2677, 2485), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2678, 2486), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2071, 2882), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2072, 2883), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2073, 2884), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2074, 2885), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2075, 2886), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2076, 2887), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2077, 2888), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2078, 2889), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2079, 2890), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2080, 2891), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2081, 2892), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2082, 2893), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2083, 2894), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2084, 2895), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2085, 2896), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2086, 2897), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2087, 2898), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2088, 2899), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2089, 2900), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2090, 2901), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2091, 2902), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2092, 2871), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2093, 2872), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2094, 2873), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2095, 2874), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2096, 2875), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2097, 2876), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2098, 2877), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2099, 2878), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2100, 2879), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2101, 2880), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2102, 2881), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2103, 2908), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2104, 2909), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2105, 2910), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2106, 2911), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2107, 2912), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2108, 2913), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2109, 2914), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2110, 2915), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2111, 2916), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2112, 2917), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2113, 2918), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2114, 2919), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2115, 2920), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2116, 2921), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2117, 2922), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2118, 2923), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2119, 2924), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2120, 2925), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2121, 2926), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2122, 2927), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2123, 2928), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2124, 2929), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2125, 2930), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2126, 2931), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2127, 2932), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2128, 2933), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2129, 2934), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2130, 2903), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2131, 2904), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2132, 2905), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2133, 2906), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2134, 2907), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(2328, 2839), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2330, 2840), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2332, 2841), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2334, 2842), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2336, 2843), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2338, 2844), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2340, 2845), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2342, 2846), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2344, 2847), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2346, 2848), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2348, 2849), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2350, 2850), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2352, 2851), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2354, 2852), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2356, 2853), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2358, 2854), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2360, 2855), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2362, 2856), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2364, 2857), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2366, 2858), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2368, 2859), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2370, 2860), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2372, 2861), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2374, 2862), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2376, 2863), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2378, 2864), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2380, 2865), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2382, 2866), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2384, 2867), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2386, 2868), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2388, 2869), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2390, 2870), // zirgen/circuit/recursion/sha.cpp:74 +PolyExtStep::Add(2711, 2775), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2712, 2776), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2713, 2777), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2714, 2778), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2715, 2779), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2716, 2780), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2717, 2781), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2718, 2782), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2719, 2783), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2720, 2784), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2721, 2785), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2722, 2786), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2723, 2787), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2724, 2788), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2725, 2789), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2726, 2790), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2727, 2791), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2728, 2792), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2729, 2793), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2730, 2794), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2731, 2795), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2732, 2796), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2733, 2797), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2734, 2798), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2735, 2799), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2736, 2800), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2737, 2801), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2738, 2802), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2739, 2803), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2740, 2804), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2741, 2805), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2742, 2806), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(3000, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3001, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3002, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3003, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3004, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3005, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3006, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3007, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3008, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3009, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3010, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3011, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3012, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3013, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3014, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3016, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3017, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3018, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3019, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3020, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3021, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3022, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3023, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3024, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3025, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3026, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3027, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3028, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3029, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3030, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(2263, 2882), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2265, 2883), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2267, 2884), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2269, 2885), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2271, 2886), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2273, 2887), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2275, 2888), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2277, 2889), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2279, 2890), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2281, 2891), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2283, 2892), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2285, 2893), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2287, 2894), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2289, 2895), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2291, 2896), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2293, 2897), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2295, 2898), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2297, 2899), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2299, 2900), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2301, 2901), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2303, 2902), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2305, 2871), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2307, 2872), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2309, 2873), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2311, 2874), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2313, 2875), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2315, 2876), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2317, 2877), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2319, 2878), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2321, 2879), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2323, 2880), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2325, 2881), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2327, 2908), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2329, 2909), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2331, 2910), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2333, 2911), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2335, 2912), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2337, 2913), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2339, 2914), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2341, 2915), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2343, 2916), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2345, 2917), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2347, 2918), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2349, 2919), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2351, 2920), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2353, 2921), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2355, 2922), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2357, 2923), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2359, 2924), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2361, 2925), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2363, 2926), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2365, 2927), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2367, 2928), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2369, 2929), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2371, 2930), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2373, 2931), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2375, 2932), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2377, 2933), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2379, 2934), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2381, 2903), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2383, 2904), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2385, 2905), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2387, 2906), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(2389, 2907), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2935, 3093), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2936, 3094), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2937, 3095), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2938, 3096), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2939, 3097), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2940, 3098), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2941, 3099), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2942, 3100), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2943, 3101), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2944, 3102), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2945, 3103), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2946, 3104), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2947, 3105), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2948, 3106), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2949, 3107), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2950, 3108), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2951, 3109), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2952, 3110), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2953, 3111), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2954, 3112), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2955, 3113), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2956, 3114), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2957, 3115), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2958, 3116), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2959, 3117), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2960, 3118), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2961, 3119), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2962, 3120), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2963, 3121), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2964, 3122), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2965, 3123), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2966, 3124), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2967, 3125), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2968, 3126), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2969, 3127), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2970, 3128), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2971, 3129), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2972, 3130), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2973, 3131), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2974, 3132), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2975, 3133), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2976, 3134), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2977, 3135), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2978, 3136), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2979, 3137), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2980, 3138), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2981, 3139), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2982, 3140), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2983, 3141), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2984, 3142), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2985, 3143), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2986, 3144), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2987, 3145), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2988, 3146), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2989, 3147), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2990, 3148), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2991, 3149), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2992, 3150), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2993, 3151), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2994, 3152), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2995, 3153), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2996, 3154), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2997, 3155), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(2998, 3156), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3031, 2807), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3032, 2808), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3033, 2809), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3034, 2810), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3035, 2811), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3036, 2812), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3037, 2813), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3038, 2814), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3039, 2815), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3040, 2816), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3041, 2817), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3042, 2818), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3043, 2819), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3044, 2820), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3045, 2821), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3046, 2822), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3047, 2823), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3048, 2824), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3049, 2825), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3050, 2826), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3051, 2827), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3052, 2828), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3053, 2829), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3054, 2830), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3055, 2831), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3056, 2832), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3057, 2833), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3058, 2834), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3059, 2835), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3060, 2836), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3061, 2837), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3062, 2838), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Mul(3157, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3158, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3160, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3161, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3162, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3163, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3164, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3165, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3166, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3167, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3168, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3169, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3170, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3171, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3172, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3173, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3174, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3176, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3177, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3178, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3179, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3180, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3181, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3182, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3183, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3184, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3185, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3186, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3187, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3188, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3189, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3190, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3191, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3192, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3193, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3194, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3196, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3197, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3198, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3199, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3200, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3201, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3202, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3203, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3204, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3205, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3206, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3207, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3208, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3209, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3210, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3212, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3213, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3214, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3215, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3216, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3217, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3218, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3219, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3220, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3221, 2392), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3222, 2394), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3223, 2396), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3224, 2398), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3225, 2400), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3226, 2402), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3227, 2404), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3228, 2406), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3229, 2408), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3230, 2410), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3231, 2412), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3232, 2414), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3233, 2416), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3234, 2418), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3235, 2420), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3236, 2422), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3237, 2424), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3238, 2426), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3239, 2428), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3240, 2430), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3241, 2432), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3242, 2434), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3243, 2436), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3244, 2438), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3245, 2440), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3246, 2442), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3247, 2444), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3248, 2446), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3249, 2448), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3250, 2450), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3251, 2452), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(3252, 2454), // zirgen/circuit/recursion/sha.cpp:65 +PolyExtStep::Add(2999, 3063), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3015, 3078), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3314, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3315, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3316, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3317, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3318, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3319, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3320, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3321, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3322, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3323, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3324, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3325, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3326, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3327, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3328, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3330, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3331, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3332, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3333, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3334, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3335, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3336, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3337, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3338, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3339, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3340, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3341, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3342, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3343, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3344, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3345, 3064), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3346, 3079), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3159, 3255), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3175, 3270), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3195, 3289), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3211, 3304), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3377, 3065), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3378, 3080), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3379, 3256), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3380, 3271), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3381, 3290), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3382, 3305), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3313, 3347), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3329, 3362), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3383, 3066), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3384, 3081), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3385, 3257), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3386, 3272), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3387, 3291), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3388, 3306), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3389, 3348), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3390, 3363), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3391, 3067), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3392, 3082), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3393, 3258), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3394, 3273), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3395, 3292), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3396, 3307), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3397, 3349), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3398, 3364), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3399, 3068), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3400, 3083), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3401, 3259), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3402, 3274), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3403, 3293), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3404, 3308), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3405, 3350), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3406, 3365), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3407, 3069), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3408, 3084), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3409, 3260), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3410, 3275), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3411, 3294), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3412, 3309), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3413, 3351), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3414, 3366), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3415, 3070), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3416, 3085), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3417, 3261), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3418, 3276), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3419, 3295), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3420, 3310), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3421, 3352), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3422, 3367), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3423, 3071), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3424, 3086), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3425, 3262), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3426, 3277), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3427, 3296), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3428, 3311), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3429, 3353), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3430, 3368), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3431, 3072), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3432, 3087), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3433, 3263), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3434, 3278), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3435, 3297), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3436, 3312), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3437, 3354), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3438, 3369), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3439, 3073), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3440, 3088), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3441, 3264), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3442, 3279), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3443, 3298), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3444, 3283), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3445, 3355), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3446, 3370), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3447, 3074), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3448, 3089), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3449, 3265), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3450, 3280), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3451, 3299), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3452, 3284), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3453, 3356), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3454, 3371), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3455, 3075), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3456, 3090), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3457, 3266), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3458, 3281), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3459, 3300), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3460, 3285), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3461, 3357), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3462, 3372), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3463, 3076), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3464, 3091), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3465, 3267), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3466, 3282), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3467, 3301), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3468, 3286), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3469, 3358), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3470, 3373), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3471, 3077), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3472, 3092), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3473, 3268), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3474, 3253), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3475, 3302), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3476, 3287), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3477, 3359), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3478, 3374), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3481, 3269), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3482, 3254), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3483, 3303), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3484, 3288), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3485, 3360), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3486, 3375), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3479, 3489), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(3480, 3490), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(1936, 3493), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(1937, 3494), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(334, 3495), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(336, 3496), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(1404, 3498), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(1368, 3497), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(3491, 3361), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3492, 3376), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3499, 1738), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(3500, 1737), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(3501, 3487), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(3502, 3488), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(3499, 3506), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(3500, 3505), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Sub(935, 3508), // zirgen/circuit/recursion/sha.cpp:300 +PolyExtStep::AndEqz(316, 3509), // zirgen/circuit/recursion/sha.cpp:300 +PolyExtStep::Sub(289, 3504), // zirgen/circuit/recursion/sha.cpp:301 +PolyExtStep::AndEqz(317, 3510), // zirgen/circuit/recursion/sha.cpp:301 +PolyExtStep::Sub(936, 3507), // zirgen/circuit/recursion/sha.cpp:300 +PolyExtStep::AndEqz(318, 3511), // zirgen/circuit/recursion/sha.cpp:300 +PolyExtStep::Sub(290, 3503), // zirgen/circuit/recursion/sha.cpp:301 +PolyExtStep::AndEqz(319, 3512), // zirgen/circuit/recursion/sha.cpp:301 +PolyExtStep::Sub(935, 1440), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(3513, 27), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(3514, 320), // zirgen/circuit/recursion/sha.cpp:135 +PolyExtStep::Mul(3515, 13), // zirgen/circuit/recursion/sha.cpp:135 +PolyExtStep::Sub(1, 3516), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::Mul(3516, 3517), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::AndEqz(320, 3518), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::Add(936, 3514), // zirgen/circuit/recursion/sha.cpp:137 +PolyExtStep::Sub(3519, 1475), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(3520, 27), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(3521, 321), // zirgen/circuit/recursion/sha.cpp:139 +PolyExtStep::Mul(3522, 13), // zirgen/circuit/recursion/sha.cpp:139 +PolyExtStep::Sub(1, 3523), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::Mul(3523, 3524), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::AndEqz(321, 3525), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::Sub(289, 1511), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(3526, 27), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(3527, 322), // zirgen/circuit/recursion/sha.cpp:135 +PolyExtStep::Mul(3528, 13), // zirgen/circuit/recursion/sha.cpp:135 +PolyExtStep::Sub(1, 3529), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::Mul(3529, 3530), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::AndEqz(322, 3531), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::Add(290, 3527), // zirgen/circuit/recursion/sha.cpp:137 +PolyExtStep::Sub(3532, 1548), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(3533, 27), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(3534, 323), // zirgen/circuit/recursion/sha.cpp:139 +PolyExtStep::Mul(3535, 13), // zirgen/circuit/recursion/sha.cpp:139 +PolyExtStep::Sub(1, 3536), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::Mul(3536, 3537), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::AndEqz(323, 3538), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::AndCond(307, 507, 324), // components/mux.h:59 +PolyExtStep::AndEqz(0, 326), // zirgen/circuit/recursion/wom.cpp:22 +PolyExtStep::AndEqz(326, 327), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(327, 328), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(328, 329), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(329, 330), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(330, 855), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Get(464), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[0](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(470), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[1](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(476), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[2](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(500), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[6](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(506), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[7](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(512), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[8](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(518), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[9](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(524), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[10](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(530), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[11](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(536), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[12](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(542), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[13](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(548), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[14](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(572), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[18](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(578), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[19](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(583), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[20](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(588), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[21](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(593), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[22](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(598), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[23](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(603), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[24](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(608), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[25](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(613), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[26](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(618), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[27](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(623), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[28](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(628), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[29](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(633), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[30](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(639), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[31](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(482), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[3](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(488), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[4](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(494), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[5](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(554), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[15](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(560), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[16](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(566), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[17](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(501), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[6](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(507), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[7](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(513), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[8](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(519), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[9](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(525), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[10](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(531), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[11](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(537), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[12](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(543), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[13](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(549), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[14](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(555), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[15](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(561), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[16](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(567), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[17](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(573), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[18](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(579), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[19](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(584), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[20](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(589), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[21](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(594), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[22](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(599), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[23](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(604), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[24](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(609), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[25](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(614), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[26](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(619), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[27](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(624), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[28](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(629), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[29](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(634), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[30](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(640), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[31](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(465), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[0](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(471), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[1](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(477), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[2](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(483), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[3](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(489), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[4](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(495), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[5](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(498), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[6](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(504), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[7](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(510), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[8](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(462), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[0](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(468), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[1](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(474), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[2](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(480), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[3](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(486), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[4](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(492), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[5](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(516), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[9](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(576), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[19](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(581), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[20](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(586), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[21](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(591), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[22](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(596), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[23](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(601), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[24](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(606), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[25](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(611), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[26](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(616), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[27](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(621), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[28](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(626), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[29](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(631), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[30](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(637), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[31](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(522), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[10](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(528), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[11](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(534), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[12](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(540), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[13](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(546), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[14](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(552), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[15](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(558), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[16](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(564), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[17](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(570), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[18](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(499), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[6](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(505), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[7](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(511), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[8](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(517), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[9](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(523), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[10](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(529), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[11](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(535), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[12](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(541), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[13](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(547), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[14](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(553), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[15](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(559), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[16](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(565), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[17](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(571), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[18](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(577), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[19](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(582), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[20](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(587), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[21](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(592), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[22](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(597), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[23](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(602), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[24](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(607), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[25](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(612), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[26](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(617), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[27](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(622), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[28](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(627), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[29](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(632), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[30](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(638), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[31](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(463), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[0](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(469), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[1](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(475), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[2](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(481), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[3](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(487), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[4](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Get(493), // top(recursion::Top)/mux(Mux)/macro_ops(recursion::MacroOp)/mux(Mux)/sha_mix(recursion::ShaWrap)/sha_cycle(recursion::ShaCycle)/w[5](Bit)/bit(Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(3539, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3540, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3541, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3542, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3543, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3544, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3545, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3546, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3547, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3548, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3549, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3550, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3551, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3552, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3553, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3554, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3555, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3556, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3557, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3558, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3559, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3560, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3561, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3562, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3563, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3564, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3565, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3566, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3567, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3568, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3569, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3570, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3603, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3604, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3605, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3606, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3607, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3608, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3609, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3610, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3611, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3612, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3613, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3614, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3615, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3616, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3617, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3618, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3619, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3620, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3621, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3622, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3623, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3624, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3625, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3626, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3627, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3628, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3629, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3630, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3631, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3632, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3633, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3634, 2), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3571, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3572, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3573, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3574, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3575, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3576, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3577, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3578, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3579, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3580, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3582, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3583, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3584, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3585, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3586, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3587, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3588, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3589, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3590, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3591, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3592, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3593, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3594, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3595, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3596, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3598, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3599, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3600, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3601, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3602, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3635, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3636, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3637, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3638, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3639, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3640, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3641, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3642, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3643, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3644, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3646, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3647, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3648, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3649, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3650, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3651, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3652, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3653, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3654, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3655, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3656, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3657, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3658, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3659, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3660, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3662, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3663, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3664, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3665, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3666, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3667, 3570), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3668, 3551), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3669, 3552), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3670, 3556), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3670, 3570), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3671, 3557), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3672, 3558), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3673, 3559), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3674, 3560), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3675, 3561), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3676, 3562), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3677, 3563), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3678, 3564), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3679, 3565), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3680, 3566), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3681, 3567), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3682, 3542), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3683, 3543), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3684, 3544), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3685, 3545), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3686, 3546), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3687, 3547), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3688, 3548), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3689, 3549), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3690, 3550), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3691, 3568), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3692, 3569), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3693, 3553), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3694, 3554), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3694, 3568), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3695, 3555), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3695, 3569), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3699, 3623), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3700, 3612), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3700, 3624), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3701, 3625), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3701, 3626), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3702, 3617), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3703, 3618), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3704, 3619), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3705, 3620), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3706, 3621), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3707, 3622), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3708, 3627), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3709, 3626), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3710, 3627), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3711, 3628), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3712, 3629), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3713, 3630), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3714, 3631), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3715, 3632), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3716, 3633), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3717, 3634), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3718, 3613), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3719, 3614), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3720, 3615), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3721, 3616), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3722, 3628), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3723, 3629), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3724, 3630), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3725, 3631), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3726, 3632), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3727, 3633), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3728, 3634), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3539, 3570), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3540, 3551), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3541, 3552), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3542, 3556), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3542, 3570), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3543, 3557), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3544, 3558), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3545, 3559), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3546, 3560), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3547, 3561), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3548, 3562), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3549, 3563), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3550, 3564), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3551, 3565), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3552, 3566), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3553, 3567), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3554, 3542), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3555, 3543), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3556, 3544), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3557, 3545), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3558, 3546), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3559, 3547), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3560, 3548), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3561, 3549), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3562, 3550), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3563, 3568), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3564, 3569), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3565, 3553), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3566, 3554), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3566, 3568), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3567, 3555), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3567, 3569), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3603, 3623), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3604, 3612), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3604, 3624), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3605, 3625), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3605, 3626), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3606, 3617), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3607, 3618), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3608, 3619), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3609, 3620), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3610, 3621), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3611, 3622), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3612, 3627), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3613, 3626), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3614, 3627), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3615, 3628), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3616, 3629), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3617, 3630), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3618, 3631), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3619, 3632), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3620, 3633), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3621, 3634), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3622, 3613), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3623, 3614), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3624, 3615), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3625, 3616), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3626, 3628), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3627, 3629), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3628, 3630), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3629, 3631), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3630, 3632), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3631, 3633), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3632, 3634), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3859, 3795), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3884, 3820), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3886, 3822), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3888, 3824), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3891, 3827), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3898, 3834), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3912, 3848), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3913, 3849), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3914, 3850), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3915, 3851), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3916, 3852), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3917, 3853), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3918, 3854), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3855, 3791), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3856, 3792), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3857, 3793), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3858, 3794), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3860, 3796), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3861, 3797), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3862, 3798), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3863, 3799), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3864, 3800), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3865, 3801), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3866, 3802), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3867, 3803), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3868, 3804), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3869, 3805), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3870, 3806), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3871, 3807), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3872, 3808), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3873, 3809), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3874, 3810), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3875, 3811), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3876, 3812), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3877, 3813), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3878, 3814), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3879, 3815), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3880, 3816), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3881, 3817), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3882, 3818), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3883, 3819), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3885, 3821), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3887, 3823), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3889, 3825), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3890, 3826), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3892, 3828), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3893, 3829), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3894, 3830), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3895, 3831), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3896, 3832), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3897, 3833), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3899, 3835), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3900, 3836), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3901, 3837), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3902, 3838), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3903, 3839), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3904, 3840), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3905, 3841), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3906, 3842), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3907, 3843), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3908, 3844), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3909, 3845), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3910, 3846), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3911, 3847), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3581, 3741), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3597, 3756), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3645, 3771), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3661, 3786), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3539, 3940), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3540, 3941), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3541, 3942), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3543, 3944), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3544, 3945), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3545, 3946), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3546, 3947), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3547, 3948), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3548, 3949), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3549, 3950), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3550, 3951), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3551, 3955), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3552, 3956), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3553, 3957), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3554, 3932), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3555, 3933), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3556, 3934), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3557, 3958), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3558, 3959), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3559, 3960), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3560, 3935), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3561, 3936), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3562, 3937), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3563, 3938), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3564, 3939), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3565, 3943), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3568, 3952), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3569, 3953), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3570, 3954), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3603, 3963), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3606, 3966), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3607, 3967), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3608, 3968), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3609, 3969), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3610, 3961), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3611, 3962), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3613, 3972), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3614, 3973), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3615, 3974), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3616, 3975), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3617, 3976), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3618, 3977), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3619, 3978), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3620, 3979), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3621, 3980), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3622, 3981), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3623, 3982), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3624, 3964), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3625, 3965), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3633, 3970), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3634, 3971), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3667, 3940), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3668, 3941), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3669, 3942), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3671, 3944), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3672, 3945), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3673, 3946), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3674, 3947), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3675, 3948), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3676, 3949), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3677, 3950), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3678, 3951), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3679, 3955), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3680, 3956), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3681, 3957), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3682, 3932), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3683, 3933), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3684, 3934), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3685, 3958), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3686, 3959), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3687, 3960), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3688, 3935), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3689, 3936), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3690, 3937), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3691, 3938), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3692, 3939), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3693, 3943), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3696, 3952), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3697, 3953), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3698, 3954), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3699, 3963), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3702, 3966), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3703, 3967), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3704, 3968), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3705, 3969), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3706, 3961), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3707, 3962), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3709, 3972), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3710, 3973), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3711, 3974), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3712, 3975), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3713, 3976), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3714, 3977), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3715, 3978), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3716, 3979), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3717, 3980), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3718, 3981), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3719, 3982), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3720, 3964), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3721, 3965), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3729, 3970), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3730, 3971), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Mul(3919, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3920, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3921, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3922, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3923, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3924, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3925, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3926, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3927, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3928, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3929, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3930, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(3931, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Sub(3987, 4038), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3988, 4039), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3989, 4040), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3990, 4041), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3991, 4042), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3992, 4043), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3993, 4044), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3994, 4045), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3995, 4046), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3996, 4047), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3997, 4048), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3998, 4049), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(3999, 4050), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4000, 4051), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4001, 4052), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4002, 4053), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4003, 4054), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4004, 4055), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4005, 4056), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4006, 4057), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4007, 4058), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4008, 4059), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4009, 4060), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4010, 4061), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4011, 4062), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4012, 4063), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4013, 4064), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4014, 4065), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4015, 4066), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4016, 4067), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4017, 4068), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4018, 4069), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4019, 4070), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4020, 4071), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4021, 4072), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4022, 4073), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4023, 4074), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4024, 4075), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4025, 4076), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4026, 4077), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4027, 4078), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4028, 4079), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4029, 4080), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4030, 4081), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4031, 4082), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4032, 4083), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4033, 4084), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4034, 4085), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4035, 4086), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4036, 4087), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Sub(4037, 4088), // zirgen/circuit/recursion/sha.cpp:57 +PolyExtStep::Add(3983, 3742), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3984, 3757), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3985, 3772), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(3986, 3787), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4102, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4103, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4104, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4106, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4107, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4108, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4109, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4110, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4111, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4112, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4113, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4114, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4115, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4116, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4117, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4119, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4120, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4121, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4122, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4123, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4124, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4125, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4126, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4127, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4128, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4129, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4130, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4131, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4132, 26), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4134, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4135, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4136, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4137, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4138, 4), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4139, 8), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4140, 14), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4141, 15), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4142, 16), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4143, 17), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4144, 19), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4145, 20), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4146, 21), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4147, 22), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4148, 23), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4149, 24), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4150, 25), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Mul(4152, 2), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4153, 3743), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4154, 3758), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4155, 3773), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4156, 3788), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4204, 3744), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4205, 3759), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4206, 3774), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4207, 3789), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4105, 4160), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4118, 4172), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4133, 4186), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4151, 4203), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4208, 3745), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4209, 3760), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4210, 3775), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4211, 3790), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4212, 4161), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4213, 4173), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4214, 4187), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4215, 4190), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4216, 3746), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4217, 3731), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4218, 3776), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4219, 3761), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4220, 4162), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4221, 4174), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4222, 4188), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4223, 4191), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4224, 3747), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4225, 3732), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4226, 3777), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4227, 3762), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4228, 4163), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4229, 4175), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4230, 4189), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4231, 4192), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4232, 3748), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4233, 3733), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4234, 3778), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4235, 3763), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4236, 4164), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4237, 4176), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4238, 4184), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4239, 4193), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4240, 3749), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4241, 3734), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4242, 3779), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4243, 3764), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4244, 4165), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4245, 4177), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4246, 4092), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4247, 4194), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4248, 3750), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4249, 3735), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4250, 3780), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4251, 3765), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4252, 4166), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4253, 4178), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4254, 4093), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4255, 4195), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4256, 3751), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4257, 3736), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4258, 3781), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4259, 3766), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4260, 4181), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4261, 4179), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4262, 4094), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4263, 4196), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4264, 3752), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4265, 3737), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4266, 3782), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4267, 3767), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4268, 4182), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4269, 4157), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4270, 4095), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4271, 4197), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4272, 3753), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4273, 3738), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4274, 3783), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4275, 3768), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4276, 4183), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4277, 4158), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4278, 4096), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4279, 4198), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4280, 3754), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4281, 3739), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4282, 3784), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4283, 3769), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4284, 4167), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4285, 4159), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4286, 4097), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4287, 4199), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4288, 3755), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4289, 3740), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4290, 3785), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4291, 3770), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4292, 4168), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4293, 4180), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4294, 4098), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4295, 4200), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4300, 4169), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4301, 4090), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4302, 4099), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4303, 4201), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4304, 4170), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4305, 4091), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4306, 4100), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4307, 4202), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4310, 4101), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4311, 4185), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4308, 4171), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4309, 4089), // zirgen/circuit/recursion/sha.cpp:84 +PolyExtStep::Add(4298, 4312), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(4299, 4313), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(4314, 4317), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(4315, 4316), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(4296, 4319), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Add(4297, 4318), // zirgen/circuit/recursion/sha.cpp:93 +PolyExtStep::Get(641), // zirgen/circuit/recursion/sha.cpp:271 +PolyExtStep::Sub(4322, 4321), // zirgen/circuit/recursion/sha.cpp:271 +PolyExtStep::AndEqz(331, 4323), // zirgen/circuit/recursion/sha.cpp:271 +PolyExtStep::Get(642), // zirgen/circuit/recursion/sha.cpp:271 +PolyExtStep::Sub(4324, 4320), // zirgen/circuit/recursion/sha.cpp:271 +PolyExtStep::AndEqz(332, 4325), // zirgen/circuit/recursion/sha.cpp:271 +PolyExtStep::Sub(4322, 1368), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(4326, 27), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(4327, 324), // zirgen/circuit/recursion/sha.cpp:135 +PolyExtStep::Mul(4328, 13), // zirgen/circuit/recursion/sha.cpp:135 +PolyExtStep::Sub(1, 4329), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::Mul(4329, 4330), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::AndEqz(333, 4331), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::Add(4324, 4327), // zirgen/circuit/recursion/sha.cpp:137 +PolyExtStep::Sub(4332, 1404), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Mul(4333, 27), // zirgen/circuit/recursion/sha.cpp:116 +PolyExtStep::Sub(4334, 325), // zirgen/circuit/recursion/sha.cpp:139 +PolyExtStep::Mul(4335, 13), // zirgen/circuit/recursion/sha.cpp:139 +PolyExtStep::Sub(1, 4336), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::Mul(4336, 4337), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::AndEqz(334, 4338), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::AndEqz(335, 3509), // zirgen/circuit/recursion/sha.cpp:300 +PolyExtStep::AndEqz(336, 3510), // zirgen/circuit/recursion/sha.cpp:301 +PolyExtStep::AndEqz(337, 3511), // zirgen/circuit/recursion/sha.cpp:300 +PolyExtStep::AndEqz(338, 3512), // zirgen/circuit/recursion/sha.cpp:301 +PolyExtStep::AndEqz(339, 3518), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::AndEqz(340, 3525), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::AndEqz(341, 3531), // zirgen/circuit/recursion/sha.cpp:136 +PolyExtStep::AndEqz(342, 3538), // zirgen/circuit/recursion/sha.cpp:140 +PolyExtStep::AndCond(325, 664, 343), // components/mux.h:59 +PolyExtStep::Mul(328, 2), // components/onehot.h:56 +PolyExtStep::Mul(329, 3), // components/onehot.h:56 +PolyExtStep::Add(327, 4339), // components/onehot.h:56 +PolyExtStep::Add(4341, 4340), // components/onehot.h:56 +PolyExtStep::Sub(4342, 696), // components/onehot.h:50 +PolyExtStep::AndEqz(0, 4343), // components/onehot.h:50 +PolyExtStep::Sub(330, 697), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(0, 4344), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::GetGlobal(0, 0), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4345, 332), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(346, 4346), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::GetGlobal(0, 1), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4347, 334), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(347, 4348), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Add(697, 1), // zirgen/circuit/recursion/macro.cpp:47 +PolyExtStep::Sub(509, 4349), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(348, 4350), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::GetGlobal(0, 2), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4351, 510), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(349, 4352), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::GetGlobal(0, 3), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4353, 511), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(350, 4354), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Add(697, 2), // zirgen/circuit/recursion/macro.cpp:47 +PolyExtStep::Sub(514, 4355), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(351, 4356), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::GetGlobal(0, 4), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4357, 515), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(352, 4358), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::GetGlobal(0, 5), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4359, 516), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(353, 4360), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Add(697, 3), // zirgen/circuit/recursion/macro.cpp:47 +PolyExtStep::Sub(519, 4361), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(354, 4362), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::GetGlobal(0, 6), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4363, 521), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(355, 4364), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::GetGlobal(0, 7), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4365, 523), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(356, 4366), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndCond(345, 326, 357), // zirgen/circuit/recursion/macro.cpp:45 +PolyExtStep::GetGlobal(0, 8), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4367, 332), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(346, 4368), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::GetGlobal(0, 9), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4369, 334), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(359, 4370), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(360, 4350), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::GetGlobal(0, 10), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4371, 510), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(361, 4372), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::GetGlobal(0, 11), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4373, 511), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(362, 4374), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(363, 4356), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::GetGlobal(0, 12), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4375, 515), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(364, 4376), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::GetGlobal(0, 13), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4377, 516), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(365, 4378), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(366, 4362), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::GetGlobal(0, 14), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4379, 521), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(367, 4380), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::GetGlobal(0, 15), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4381, 523), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(368, 4382), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndCond(358, 327, 369), // zirgen/circuit/recursion/macro.cpp:45 +PolyExtStep::GetGlobal(0, 16), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4383, 332), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(346, 4384), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::GetGlobal(0, 17), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4385, 334), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(371, 4386), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(372, 4350), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::GetGlobal(0, 18), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4387, 510), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(373, 4388), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::GetGlobal(0, 19), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4389, 511), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(374, 4390), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(375, 4356), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::GetGlobal(0, 20), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4391, 515), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(376, 4392), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::GetGlobal(0, 21), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4393, 516), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(377, 4394), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(378, 4362), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::GetGlobal(0, 22), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4395, 521), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(379, 4396), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::GetGlobal(0, 23), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4397, 523), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(380, 4398), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndCond(370, 328, 381), // zirgen/circuit/recursion/macro.cpp:45 +PolyExtStep::GetGlobal(0, 24), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4399, 332), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(346, 4400), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::GetGlobal(0, 25), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4401, 334), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(383, 4402), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(384, 4350), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::GetGlobal(0, 26), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4403, 510), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(385, 4404), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::GetGlobal(0, 27), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4405, 511), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(386, 4406), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(387, 4356), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::GetGlobal(0, 28), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4407, 515), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(388, 4408), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::GetGlobal(0, 29), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4409, 516), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(389, 4410), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(390, 4362), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::GetGlobal(0, 30), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4411, 521), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(391, 4412), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::GetGlobal(0, 31), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::Sub(4413, 523), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndEqz(392, 4414), // zirgen/circuit/recursion/macro.cpp:50 +PolyExtStep::AndCond(382, 329, 393), // zirgen/circuit/recursion/macro.cpp:45 +PolyExtStep::AndCond(344, 695, 394), // components/mux.h:59 +PolyExtStep::AndCond(250, 852, 395), // components/mux.h:59 +PolyExtStep::Get(19), // top(recursion::Top)/code(recursion::Code)/select(OneHot)/poseidon2_load(Reg)(components/mux.h:59) +PolyExtStep::Mul(285, 43), // zirgen/circuit/recursion/poseidon2.cpp:65 +PolyExtStep::Sub(1, 285), // zirgen/circuit/recursion/poseidon2.cpp:65 +PolyExtStep::Add(4416, 4417), // zirgen/circuit/recursion/poseidon2.cpp:65 +PolyExtStep::Sub(320, 507), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(0, 4419), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Mul(321, 4418), // zirgen/circuit/recursion/poseidon2.cpp:67 +PolyExtStep::Sub(325, 664), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(397, 4421), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Mul(326, 4418), // zirgen/circuit/recursion/poseidon2.cpp:67 +PolyExtStep::Sub(330, 695), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(398, 4423), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Mul(332, 4418), // zirgen/circuit/recursion/poseidon2.cpp:67 +PolyExtStep::Sub(509, 697), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(399, 4425), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Mul(510, 4418), // zirgen/circuit/recursion/poseidon2.cpp:67 +PolyExtStep::Sub(514, 696), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(400, 4427), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Mul(515, 4418), // zirgen/circuit/recursion/poseidon2.cpp:67 +PolyExtStep::Sub(519, 1111), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(401, 4429), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Get(37), // top(recursion::Top)/code(recursion::Code)/inst(Mux)/poseidon2_load(recursion::Poseidon2MemInst)/inputs[6](Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(521, 4418), // zirgen/circuit/recursion/poseidon2.cpp:67 +PolyExtStep::Sub(698, 4430), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(402, 4432), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Get(38), // top(recursion::Top)/code(recursion::Code)/inst(Mux)/poseidon2_load(recursion::Poseidon2MemInst)/inputs[7](Reg)(compiler/edsl/component.h:164) +PolyExtStep::Mul(699, 4418), // zirgen/circuit/recursion/poseidon2.cpp:67 +PolyExtStep::Sub(703, 4433), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(403, 4435), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Get(497), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(503), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(509), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(515), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(521), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(527), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(533), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(539), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(545), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(551), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(557), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(563), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(569), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(575), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(445), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(451), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(457), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(459), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(461), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(467), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(473), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(479), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(485), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Get(491), // top(recursion::Top)/mux(Mux)/poseidon2_load(recursion::Poseidon2Load)/Reg(zirgen/circuit/recursion/poseidon2.cpp:79) +PolyExtStep::Mul(317, 4436), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(317, 4437), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(317, 4438), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(317, 4439), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(317, 4440), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(317, 4441), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(317, 4450), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(317, 4451), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(317, 4452), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(317, 4453), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(317, 4454), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(317, 4455), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(317, 4456), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(317, 4457), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(317, 4458), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(317, 4459), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(318, 44), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(475, 4422), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(475, 4424), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(475, 4426), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(475, 4428), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(475, 4431), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(475, 4434), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(475, 4420), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(506, 4422), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(506, 4424), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(506, 4426), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(506, 4428), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(506, 4431), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(506, 4434), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(506, 4420), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(508, 4422), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(508, 4424), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(508, 4426), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(508, 4428), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(508, 4431), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(508, 4434), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(508, 4420), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(317, 319), // zirgen/circuit/recursion/poseidon2.cpp:78 +PolyExtStep::Mul(704, 4418), // zirgen/circuit/recursion/poseidon2.cpp:67 +PolyExtStep::Add(317, 319), // zirgen/circuit/recursion/poseidon2.cpp:78 +PolyExtStep::Add(4460, 4485), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4462, 4487), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4464, 4489), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4466, 4483), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4468, 4478), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4470, 4480), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4472, 4482), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4474, 4490), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4461, 4486), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4463, 4488), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4467, 4477), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4469, 4479), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4471, 4481), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4475, 4484), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(4509, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(4510, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(4511, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(4512, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(4513, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(4514, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(475, 4499), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(506, 4499), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(508, 4499), // zirgen/circuit/recursion/poseidon2.cpp:80 +PolyExtStep::Mul(462, 4504), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Sub(4500, 4498), // zirgen/circuit/recursion/poseidon2.cpp:78 +PolyExtStep::Add(4501, 4509), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(4502, 4510), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(4504, 4511), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(4505, 4512), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(4506, 4513), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(4508, 4514), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(4515, 4531), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(4517, 4529), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(4518, 4528), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(4520, 4526), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(4465, 4522), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4473, 4521), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(4526, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(4527, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(4528, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(4529, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(4530, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(4531, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(4536, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(4537, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(4525, 4442), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(4525, 4443), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(4525, 4444), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(4525, 4445), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(4525, 4446), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(4525, 4447), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(4525, 4448), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(4525, 4449), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4503, 4536), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(4507, 4537), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(4540, 4533), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(4541, 4534), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(4516, 4554), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(4544, 4527), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(4519, 4555), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(4545, 4530), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(4546, 4497), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4548, 4492), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4550, 4494), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4552, 4496), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4538, 4532), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(4539, 4558), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(4542, 4560), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(4543, 4535), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(4547, 4491), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4549, 4493), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4551, 4495), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Add(4553, 4523), // zirgen/circuit/recursion/poseidon2.cpp:79 +PolyExtStep::Mul(4554, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(4555, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(4570, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(4571, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(4572, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(4573, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(4533, 4557), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(4534, 4556), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(4532, 4569), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(4559, 4567), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(4561, 4568), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(4535, 4566), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(4562, 4570), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(4563, 4571), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(4564, 4572), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(4565, 4573), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(4576, 4587), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(4577, 4586), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(4578, 4589), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(4579, 4588), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(4574, 4559), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(4575, 4561), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(4586, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(4587, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(4588, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(4589, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(4556, 4568), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4557, 4595), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4558, 4594), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(4560, 4595), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(4596, 4590), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(4597, 4591), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(4598, 4592), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(4599, 4593), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(4600, 4569), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4601, 4566), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4580, 4603), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4581, 4584), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4590, 4605), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(4591, 4604), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(4592, 4607), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(4593, 4606), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(4608, 4567), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4609, 4594), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4610, 4585), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4611, 4582), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4616, 4604), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4617, 4605), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4618, 4602), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4619, 4583), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4620, 4606), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4621, 4607), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4622, 4612), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4623, 4613), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4556, 4624), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4557, 4625), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4566, 4625), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4567, 4624), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4594, 4625), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4568, 4624), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4595, 4625), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4569, 4624), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4604, 4624), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4605, 4625), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4606, 4624), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4607, 4625), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4626, 4614), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4627, 4615), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(4580, 4640), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4581, 4641), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4582, 4641), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4602, 4640), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4583, 4641), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4603, 4640), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4584, 4641), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4585, 4640), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4612, 4640), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4613, 4641), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4614, 4640), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4615, 4641), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Mul(318, 4643), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4654, 4524), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4655, 4476), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(316, 4656), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(404, 4657), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4628), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 45), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4511), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4658, 4660), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4661, 4659), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(288, 4662), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(405, 4663), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4642), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 46), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4505), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4664, 4666), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4667, 4665), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(289, 4668), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(406, 4669), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4629), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 47), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4512), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4670, 4672), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4673, 4671), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(290, 4674), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(407, 4675), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4648), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 48), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4506), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4676, 4678), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4679, 4677), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(291, 4680), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(408, 4681), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4633), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 49), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4513), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4682, 4684), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4685, 4683), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(292, 4686), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(409, 4687), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4647), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 50), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4507), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4688, 4690), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4691, 4689), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(293, 4692), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(410, 4693), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4634), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 51), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4537), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4694, 4696), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4697, 4695), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(294, 4698), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(411, 4699), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4644), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 52), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4508), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4700, 4702), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4703, 4701), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(295, 4704), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(412, 4705), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4635), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 53), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4514), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4706, 4708), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4709, 4707), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(296, 4710), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(413, 4711), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4649), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 54), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4501), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4712, 4714), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4715, 4713), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(287, 4716), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(414, 4717), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4630), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 55), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4509), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4718, 4720), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4721, 4719), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(430, 4722), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(415, 4723), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4646), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 56), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4502), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4724, 4726), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4727, 4725), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(505, 4728), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(416, 4729), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4631), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 57), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4510), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4730, 4732), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4733, 4731), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(476, 4734), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(417, 4735), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4645), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 58), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4503), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4736, 4738), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4739, 4737), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(477, 4740), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(418, 4741), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4632), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 59), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4536), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4742, 4744), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4745, 4743), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(478, 4746), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(419, 4747), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4651), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 60), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4562), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4748, 4750), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4751, 4749), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(479, 4752), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(420, 4753), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4636), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 61), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4570), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4754, 4756), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4757, 4755), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(480, 4758), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(421, 4759), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4650), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 62), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4563), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4760, 4762), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4763, 4761), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(481, 4764), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(422, 4765), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4637), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 63), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4571), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4766, 4768), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4769, 4767), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(482, 4770), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(423, 4771), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4653), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 64), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4564), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4772, 4774), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4775, 4773), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(483, 4776), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(424, 4777), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4638), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 65), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4572), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4778, 4780), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4781, 4779), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(484, 4782), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(425, 4783), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4652), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 66), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4565), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4784, 4786), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4787, 4785), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(485, 4788), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(426, 4789), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::Mul(318, 4639), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Mul(318, 67), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Mul(462, 4573), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4790, 4792), // zirgen/circuit/recursion/poseidon2.cpp:86 +PolyExtStep::Add(4793, 4791), // zirgen/circuit/recursion/poseidon2.cpp:87 +PolyExtStep::Sub(619, 4794), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndEqz(427, 4795), // zirgen/circuit/recursion/poseidon2.cpp:88 +PolyExtStep::AndCond(396, 4415, 428), // components/mux.h:59 +PolyExtStep::Get(20), // top(recursion::Top)/code(recursion::Code)/select(OneHot)/poseidon2_full(Reg)(components/mux.h:59) +PolyExtStep::Get(497), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(503), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(509), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(515), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(521), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(527), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(533), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(539), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(545), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(551), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(557), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(563), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(569), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(575), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(457), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(459), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(461), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(467), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(473), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(479), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(485), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Get(491), // top(recursion::Top)/mux(Mux)/poseidon2_full(recursion::Poseidon2Full)/Reg(zirgen/circuit/recursion/poseidon2.cpp:211) +PolyExtStep::Mul(2133, 2133), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(4819, 4819), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(320, 4820), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(0, 4821), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(2134, 2134), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(320, 4819), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4823, 2133), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4822, 4822), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(321, 4825), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(430, 4826), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4811, 4811), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(321, 4822), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4828, 2134), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4827, 4827), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(322, 4830), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(431, 4831), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4812, 4812), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(322, 4827), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4833, 4811), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4832, 4832), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(323, 4835), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(432, 4836), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4813, 4813), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(323, 4832), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4838, 4812), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4837, 4837), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(324, 4840), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(433, 4841), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4814, 4814), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(324, 4837), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4843, 4813), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4842, 4842), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(325, 4845), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(434, 4846), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4815, 4815), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(325, 4842), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4848, 4814), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4847, 4847), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(326, 4850), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(435, 4851), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4816, 4816), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(326, 4847), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4853, 4815), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4852, 4852), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(327, 4855), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(436, 4856), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4817, 4817), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(327, 4852), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4858, 4816), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4857, 4857), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(328, 4860), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(437, 4861), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4818, 4818), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(328, 4857), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4863, 4817), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4862, 4862), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(329, 4865), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(438, 4866), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4797, 4797), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(329, 4862), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4868, 4818), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4867, 4867), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(330, 4870), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(439, 4871), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4798, 4798), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(330, 4867), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4873, 4797), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4872, 4872), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(332, 4875), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(440, 4876), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4799, 4799), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(332, 4872), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4878, 4798), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4877, 4877), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(334, 4880), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(441, 4881), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4800, 4800), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(334, 4877), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4883, 4799), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4882, 4882), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(336, 4885), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(442, 4886), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4801, 4801), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(336, 4882), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4888, 4800), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4887, 4887), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(338, 4890), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(443, 4891), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4802, 4802), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(338, 4887), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4893, 4801), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4892, 4892), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(509, 4895), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(444, 4896), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4803, 4803), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(509, 4892), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4898, 4802), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4897, 4897), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(510, 4900), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(445, 4901), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4804, 4804), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(510, 4897), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4903, 4803), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4902, 4902), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(511, 4905), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(446, 4906), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4805, 4805), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(511, 4902), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4908, 4804), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4907, 4907), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(512, 4910), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(447, 4911), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4806, 4806), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(512, 4907), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4913, 4805), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4912, 4912), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(513, 4915), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(448, 4916), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4807, 4807), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(513, 4912), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4918, 4806), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4917, 4917), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(514, 4920), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(449, 4921), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4808, 4808), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(514, 4917), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4923, 4807), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4922, 4922), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(515, 4925), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(450, 4926), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4809, 4809), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(515, 4922), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4928, 4808), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4927, 4927), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(516, 4930), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(451, 4931), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4810, 4810), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(516, 4927), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4933, 4809), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(4932, 4932), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(517, 4935), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(452, 4936), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(4854, 4859), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(4864, 4869), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(4874, 4879), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(4884, 4889), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(4894, 4899), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(4904, 4909), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(4914, 4919), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(4924, 4929), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(4824, 4829), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(4834, 4839), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(4844, 4849), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Mul(4937, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(4938, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(4939, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(4940, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(4941, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(4942, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(4943, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(4944, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(4945, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(4946, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(4947, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(4849, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(4859, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(4869, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(4879, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(4889, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(4899, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(4909, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(4919, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(4929, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(4829, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(4839, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(4959, 4937), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(4960, 4947), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(4961, 4939), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(4962, 4938), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(4963, 4941), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(4964, 4940), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(4965, 4943), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(4966, 4942), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(4968, 4946), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(4969, 4945), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(4948, 4971), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(4949, 4972), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(4950, 4973), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(4951, 4974), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(4952, 4975), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(4953, 4976), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(4954, 4977), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(4958, 4970), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(517, 4932), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(285, 73), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 74), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 76), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 84), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 90), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 92), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 99), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 100), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 109), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 113), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 117), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 121), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 122), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 123), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 124), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 129), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 134), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 139), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 142), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 144), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 145), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 148), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 157), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 161), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 69), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 75), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 78), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 79), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 95), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 96), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 98), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 101), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 105), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 107), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 110), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 118), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 128), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 133), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 146), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 147), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 150), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 152), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 153), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 158), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 159), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 160), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 162), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 163), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 68), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 70), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 71), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 72), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 77), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 82), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 88), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 89), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 93), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 94), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 103), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 104), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 108), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 116), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 119), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 120), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 125), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 127), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 136), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 143), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 149), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 151), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 154), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(318, 155), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 80), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 81), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 83), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 85), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 86), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 87), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 91), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 97), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 102), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 106), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 111), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 112), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 114), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 115), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 126), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 130), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 131), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 132), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 135), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 137), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 138), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 140), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 141), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(317, 156), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(4988, 4810), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Add(4970, 4980), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(4971, 4987), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(4972, 4982), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(4973, 4981), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(4974, 4984), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(4975, 4983), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(4976, 4986), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(4977, 4985), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(4956, 4978), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(4957, 4979), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(4934, 5085), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(4967, 5096), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(4955, 5097), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(5096, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(5085, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(4989, 5061), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(4990, 5084), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(4991, 5072), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(4992, 5067), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(4993, 5065), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(4994, 5082), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(4995, 5076), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(4996, 5071), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(4997, 5062), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(4998, 5073), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(4999, 5069), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5000, 5080), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5001, 5078), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5002, 5079), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5003, 5070), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5004, 5074), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5005, 5077), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5006, 5083), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5007, 5075), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5008, 5068), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5009, 5064), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5010, 5081), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5011, 5063), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5012, 5066), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(4978, 5095), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(4979, 5094), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(5100, 4944), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(5099, 5127), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(5101, 5035), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5102, 5014), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5103, 5033), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5104, 5021), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5105, 5016), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5106, 5024), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5107, 5023), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5108, 5036), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5109, 5020), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5110, 5027), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5111, 5028), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5112, 5017), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5113, 5031), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5114, 5018), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5115, 5013), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5116, 5029), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5117, 5025), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5118, 5026), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5119, 5030), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5120, 5032), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5121, 5015), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5122, 5034), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5123, 5022), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5124, 5019), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5094, 4987), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5095, 4980), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5129, 5048), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5130, 5051), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5131, 5044), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5132, 5043), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5133, 5057), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5134, 5050), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5135, 5049), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5136, 5054), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5137, 5042), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5138, 5053), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5139, 5052), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5140, 5059), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5141, 5040), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5142, 5060), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5143, 5056), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5144, 5047), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5145, 5046), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5146, 5037), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5147, 5058), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5148, 5055), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5149, 5041), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5150, 5038), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5151, 5039), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5152, 5045), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5097, 5128), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(5127, 5098), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(5153, 4981), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5154, 4982), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5125, 5086), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5126, 5087), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5181, 4983), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5182, 4984), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5183, 5088), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5184, 5089), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5185, 4985), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5186, 4986), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5187, 5090), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5188, 5091), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5189, 5098), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5190, 5128), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5191, 5092), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5192, 5093), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5094, 5193), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5095, 5194), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4980, 5194), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4981, 5193), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4982, 5194), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4983, 5193), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4984, 5194), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4985, 5193), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4986, 5194), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5098, 5193), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5128, 5194), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(4987, 5193), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5195, 5179), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5196, 5180), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5125, 5209), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5126, 5210), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5086, 5209), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5087, 5210), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5088, 5209), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5089, 5210), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5090, 5209), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5091, 5210), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5092, 5209), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5093, 5210), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5179, 5209), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5180, 5210), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5212, 5175), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Sub(518, 5223), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(453, 5224), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(518, 518), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5225, 5225), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(909, 5226), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(454, 5227), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5197, 5165), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(909, 5225), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5229, 518), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(519, 5228), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(455, 5231), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(519, 519), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5232, 5232), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(917, 5233), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(456, 5234), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5211, 5172), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(917, 5232), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5236, 519), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(521, 5235), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(457, 5238), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(521, 521), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5239, 5239), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(918, 5240), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(458, 5241), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5198, 5159), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(918, 5239), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5243, 521), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(523, 5242), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(459, 5245), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(523, 523), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5246, 5246), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(926, 5247), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(460, 5248), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5214, 5167), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(926, 5246), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5250, 523), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(525, 5249), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(461, 5252), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(525, 525), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5253, 5253), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(927, 5254), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(462, 5255), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5208, 5156), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(927, 5253), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5257, 525), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(527, 5256), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(463, 5259), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(527, 527), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5260, 5260), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(935, 5261), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(464, 5262), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5213, 5168), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(935, 5260), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5264, 527), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(698, 5263), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(465, 5266), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(698, 698), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5267, 5267), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(936, 5268), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(466, 5269), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5199, 5162), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(936, 5267), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5271, 698), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(699, 5270), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(467, 5273), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(699, 699), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5274, 5274), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(944, 5275), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(468, 5276), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5216, 5160), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(944, 5274), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5278, 699), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(700, 5277), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(469, 5280), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(700, 700), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5281, 5281), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(945, 5282), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(470, 5283), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5200, 5173), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(945, 5281), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5285, 700), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(701, 5284), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(471, 5287), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(701, 701), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5288, 5288), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(953, 5289), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(472, 5290), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5215, 5174), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(953, 5288), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5292, 701), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(702, 5291), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(473, 5294), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(702, 702), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5295, 5295), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(954, 5296), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(474, 5297), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5201, 5164), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(954, 5295), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5299, 702), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(703, 5298), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(475, 5301), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(703, 703), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5302, 5302), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(962, 5303), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(476, 5304), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5218, 5158), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(962, 5302), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5306, 703), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(704, 5305), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(477, 5308), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(704, 704), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5309, 5309), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(963, 5310), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(478, 5311), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5202, 5177), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(963, 5309), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5313, 704), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(705, 5312), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(479, 5315), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(705, 705), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5316, 5316), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(971, 5317), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(480, 5318), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5217, 5176), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(971, 5316), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5320, 705), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(706, 5319), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(481, 5322), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(706, 706), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5323, 5323), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(972, 5324), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(482, 5325), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5203, 5169), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(972, 5323), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5327, 706), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(707, 5326), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(483, 5329), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(707, 707), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5330, 5330), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(980, 5331), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(484, 5332), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5220, 5171), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(980, 5330), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5334, 707), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(708, 5333), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(485, 5336), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(708, 708), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5337, 5337), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(981, 5338), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(486, 5339), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5204, 5157), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(981, 5337), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5341, 708), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(710, 5340), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(487, 5343), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(710, 710), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5344, 5344), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(989, 5345), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(488, 5346), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5219, 5166), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(989, 5344), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5348, 710), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(712, 5347), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(489, 5350), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(712, 712), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5351, 5351), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(990, 5352), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(490, 5353), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5205, 5155), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(990, 5351), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5355, 712), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(714, 5354), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(491, 5357), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(714, 714), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5358, 5358), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(998, 5359), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(492, 5360), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5222, 5163), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(998, 5358), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5362, 714), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(716, 5361), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(493, 5364), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(716, 716), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5365, 5365), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(999, 5366), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(494, 5367), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5206, 5161), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(999, 5365), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5369, 716), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(899, 5368), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(495, 5371), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(899, 899), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5372, 5372), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(1007, 5373), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(496, 5374), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5221, 5170), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(1007, 5372), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5376, 899), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(900, 5375), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(497, 5378), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(900, 900), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5379, 5379), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(1008, 5380), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(498, 5381), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5207, 5178), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(1008, 5379), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5383, 900), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Sub(908, 5382), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::AndEqz(499, 5385), // zirgen/circuit/recursion/poseidon2.cpp:248 +PolyExtStep::Mul(908, 908), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5386, 5386), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(1016, 5387), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(500, 5388), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Add(5230, 5237), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(5244, 5251), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(5258, 5265), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(5272, 5279), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(5286, 5293), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(5300, 5307), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(5314, 5321), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(5328, 5335), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(5342, 5349), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(5356, 5363), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(5370, 5377), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Mul(5389, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(5390, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(5391, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(5392, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(5393, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(5394, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(5395, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(5396, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(5397, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(5398, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(5399, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(5237, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(5251, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(5265, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(5279, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(5293, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(5307, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(5321, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(5335, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(5349, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(5363, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(5377, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(5411, 5390), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(5412, 5389), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(5413, 5392), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(5414, 5391), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(5415, 5394), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(5416, 5393), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(5417, 5396), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(5418, 5395), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(5419, 5398), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(5420, 5397), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(5402, 5424), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(5403, 5425), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(5404, 5426), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(5405, 5427), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(5406, 5428), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(5407, 5429), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(5408, 5430), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(5409, 5431), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(1016, 5386), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(285, 166), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 168), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 169), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 172), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 173), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 176), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 177), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 181), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 183), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 185), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 186), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 187), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 189), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 194), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 195), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 198), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 199), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 200), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 202), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 203), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 205), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 208), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 209), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(285, 211), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 164), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 165), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 167), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 170), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 171), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 174), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 175), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 178), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 179), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 180), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 182), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 184), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 188), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 190), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 191), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 192), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 193), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 196), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 197), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 201), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 204), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 206), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 207), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(319, 210), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Mul(5440, 908), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Add(5441, 5484), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5442, 5486), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5443, 5475), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5444, 5488), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5445, 5483), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5446, 5481), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5447, 5485), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5448, 5487), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5449, 5480), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5450, 5466), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5451, 5478), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5452, 5468), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5453, 5467), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5454, 5473), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5455, 5465), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5456, 5482), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5457, 5477), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5458, 5474), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5459, 5469), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5460, 5471), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5461, 5470), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5462, 5472), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5463, 5479), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5464, 5476), // zirgen/circuit/recursion/poseidon2.cpp:198 +PolyExtStep::Add(5424, 5433), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(5425, 5432), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(5426, 5435), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(5427, 5434), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(5428, 5437), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(5429, 5436), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(5430, 5439), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(5431, 5438), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(5400, 5422), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(5401, 5423), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(5384, 5489), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(5421, 5524), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(5410, 5525), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(5524, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(5489, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(5422, 5523), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(5423, 5522), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(5528, 5399), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(5527, 5531), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(5522, 5432), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5523, 5433), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5525, 5532), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(5531, 5526), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(5533, 5434), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5534, 5435), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5529, 5514), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5530, 5515), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5537, 5436), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5538, 5437), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5539, 5516), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5540, 5517), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5541, 5438), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5542, 5439), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5543, 5518), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5544, 5519), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5545, 5526), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5546, 5532), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5547, 5520), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5548, 5521), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5522, 5549), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5523, 5550), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5432, 5549), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5433, 5550), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5434, 5549), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5435, 5550), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5436, 5549), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5437, 5550), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5438, 5549), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5439, 5550), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5526, 5549), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5532, 5550), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5551, 5535), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5552, 5536), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(5529, 5565), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5530, 5566), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5514, 5565), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5515, 5566), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5516, 5565), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5517, 5566), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5518, 5565), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5519, 5566), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5520, 5565), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5521, 5566), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5535, 5565), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5536, 5566), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(5568, 5492), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(316, 5579), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(501, 5580), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5553, 5506), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(288, 5581), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(502, 5582), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5567, 5494), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(289, 5583), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(503, 5584), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5554, 5495), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(290, 5585), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(504, 5586), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5570, 5505), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(291, 5587), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(505, 5588), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5555, 5502), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(292, 5589), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(506, 5590), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5569, 5511), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(293, 5591), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(507, 5592), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5556, 5493), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(294, 5593), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(508, 5594), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5572, 5513), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(295, 5595), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(509, 5596), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5557, 5509), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(296, 5597), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(510, 5598), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5571, 5496), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(287, 5599), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(511, 5600), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5558, 5508), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(430, 5601), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(512, 5602), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5574, 5499), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(505, 5603), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(513, 5604), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5559, 5501), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(476, 5605), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(514, 5606), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5573, 5510), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(477, 5607), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(515, 5608), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5560, 5497), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(478, 5609), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(516, 5610), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5576, 5503), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(479, 5611), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(517, 5612), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5561, 5500), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(480, 5613), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(518, 5614), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5575, 5490), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(481, 5615), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(519, 5616), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5562, 5498), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(482, 5617), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(520, 5618), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5578, 5491), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(483, 5619), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(521, 5620), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5563, 5504), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(484, 5621), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(522, 5622), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5577, 5507), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(485, 5623), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(523, 5624), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Add(5564, 5512), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::Sub(619, 5625), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndEqz(524, 5626), // zirgen/circuit/recursion/poseidon2.cpp:283 +PolyExtStep::AndCond(429, 4796, 525), // components/mux.h:59 +PolyExtStep::Get(21), // top(recursion::Top)/code(recursion::Code)/select(OneHot)/poseidon2_partial(Reg)(components/mux.h:59) +PolyExtStep::Sub(320, 2133), // zirgen/circuit/recursion/poseidon2.cpp:301 +PolyExtStep::AndEqz(0, 5628), // zirgen/circuit/recursion/poseidon2.cpp:301 +PolyExtStep::Add(320, 212), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(5629, 5629), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5630, 5630), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(518, 5631), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(527, 5632), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(4797, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4798, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4799, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4800, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4801, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4802, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4803, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4804, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4805, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4806, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4807, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4808, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4809, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4810, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(2134, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4811, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4812, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4813, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4814, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4815, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4816, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4817, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(4818, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(518, 5630), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5656, 5629), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5657, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5657, 2134), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5659, 4811), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5660, 4812), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5661, 4813), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5662, 4814), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5663, 4815), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5664, 4816), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5665, 4817), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5666, 4818), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5667, 4797), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5668, 4798), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5669, 4799), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5670, 4800), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5671, 4801), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5672, 4802), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5673, 4803), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5674, 4804), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5675, 4805), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5676, 4806), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5677, 4807), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5678, 4808), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5679, 4809), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5680, 4810), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5681, 5633), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5634), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5635), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5636), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5637), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5638), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5639), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5640), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5641), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5642), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5643), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5644), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5645), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5646), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5647), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5648), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5649), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5650), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5651), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5652), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5653), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5654), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5655), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5681, 5658), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(321, 5705), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(528, 5706), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(321, 237), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(5707, 5707), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5708, 5708), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(519, 5709), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(529, 5710), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(5682, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5683, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5684, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5685, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5686, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5687, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5688, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5689, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5690, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5691, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5692, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5693, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5694, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5695, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5696, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5697, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5698, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5699, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5700, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5701, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5702, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5703, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5704, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(519, 5708), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5734, 5707), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5735, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5735, 5696), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5737, 5697), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5738, 5698), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5739, 5699), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5740, 5700), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5741, 5701), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5742, 5702), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5743, 5703), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5744, 5704), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5745, 5682), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5746, 5683), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5747, 5684), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5748, 5685), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5749, 5686), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5750, 5687), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5751, 5688), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5752, 5689), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5753, 5690), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5754, 5691), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5755, 5692), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5756, 5693), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5757, 5694), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5758, 5695), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5759, 5711), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5712), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5713), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5714), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5715), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5716), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5717), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5718), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5719), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5720), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5721), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5722), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5723), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5724), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5725), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5726), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5727), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5728), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5729), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5730), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5731), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5732), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5733), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5759, 5736), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(322, 5783), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(530, 5784), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(322, 238), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(5785, 5785), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5786, 5786), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(521, 5787), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(531, 5788), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(5760, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5761, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5762, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5763, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5764, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5765, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5766, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5767, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5768, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5769, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5770, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5771, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5772, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5773, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5774, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5775, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5776, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5777, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5778, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5779, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5780, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5781, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5782, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(521, 5786), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5812, 5785), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5813, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5813, 5774), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5815, 5775), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5816, 5776), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5817, 5777), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5818, 5778), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5819, 5779), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5820, 5780), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5821, 5781), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5822, 5782), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5823, 5760), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5824, 5761), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5825, 5762), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5826, 5763), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5827, 5764), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5828, 5765), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5829, 5766), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5830, 5767), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5831, 5768), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5832, 5769), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5833, 5770), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5834, 5771), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5835, 5772), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5836, 5773), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5837, 5789), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5790), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5791), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5792), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5793), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5794), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5795), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5796), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5797), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5798), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5799), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5800), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5801), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5802), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5803), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5804), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5805), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5806), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5807), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5808), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5809), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5810), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5811), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5837, 5814), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(323, 5861), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(532, 5862), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(323, 239), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(5863, 5863), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5864, 5864), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(523, 5865), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(533, 5866), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(5838, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5839, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5840, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5841, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5842, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5843, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5844, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5845, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5846, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5847, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5848, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5849, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5850, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5851, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5852, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5853, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5854, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5855, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5856, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5857, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5858, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5859, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5860, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(523, 5864), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5890, 5863), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5891, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5891, 5852), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5893, 5853), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5894, 5854), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5895, 5855), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5896, 5856), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5897, 5857), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5898, 5858), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5899, 5859), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5900, 5860), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5901, 5838), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5902, 5839), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5903, 5840), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5904, 5841), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5905, 5842), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5906, 5843), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5907, 5844), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5908, 5845), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5909, 5846), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5910, 5847), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5911, 5848), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5912, 5849), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5913, 5850), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5914, 5851), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5915, 5867), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5868), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5869), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5870), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5871), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5872), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5873), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5874), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5875), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5876), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5877), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5878), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5879), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5880), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5881), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5882), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5883), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5884), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5885), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5886), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5887), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5888), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5889), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5915, 5892), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(324, 5939), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(534, 5940), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(324, 240), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(5941, 5941), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(5942, 5942), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(525, 5943), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(535, 5944), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(5916, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5917, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5918, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5919, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5920, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5921, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5922, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5923, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5924, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5925, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5926, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5927, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5928, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5929, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5930, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5931, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5932, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5933, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5934, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5935, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5936, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5937, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5938, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(525, 5942), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5968, 5941), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(5969, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5969, 5930), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5971, 5931), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5972, 5932), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5973, 5933), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5974, 5934), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5975, 5935), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5976, 5936), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5977, 5937), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5978, 5938), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5979, 5916), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5980, 5917), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5981, 5918), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5982, 5919), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5983, 5920), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5984, 5921), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5985, 5922), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5986, 5923), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5987, 5924), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5988, 5925), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5989, 5926), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5990, 5927), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5991, 5928), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5992, 5929), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(5993, 5945), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5946), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5947), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5948), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5949), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5950), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5951), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5952), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5953), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5954), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5955), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5956), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5957), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5958), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5959), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5960), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5961), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5962), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5963), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5964), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5965), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5966), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5967), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(5993, 5970), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(325, 6017), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(536, 6018), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(325, 241), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(6019, 6019), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(6020, 6020), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(527, 6021), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(537, 6022), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(5994, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5995, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5996, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5997, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5998, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(5999, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6000, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6001, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6002, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6003, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6004, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6005, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6006, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6007, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6008, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6009, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6010, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6011, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6012, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6013, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6014, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6015, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6016, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(527, 6020), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6046, 6019), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6047, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6047, 6008), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6049, 6009), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6050, 6010), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6051, 6011), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6052, 6012), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6053, 6013), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6054, 6014), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6055, 6015), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6056, 6016), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6057, 5994), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6058, 5995), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6059, 5996), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6060, 5997), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6061, 5998), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6062, 5999), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6063, 6000), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6064, 6001), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6065, 6002), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6066, 6003), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6067, 6004), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6068, 6005), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6069, 6006), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6070, 6007), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6071, 6023), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6024), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6025), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6026), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6027), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6028), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6029), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6030), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6031), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6032), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6033), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6034), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6035), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6036), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6037), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6038), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6039), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6040), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6041), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6042), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6043), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6044), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6045), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6071, 6048), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(326, 6095), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(538, 6096), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(326, 242), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(6097, 6097), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(6098, 6098), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(698, 6099), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(539, 6100), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(6072, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6073, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6074, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6075, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6076, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6077, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6078, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6079, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6080, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6081, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6082, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6083, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6084, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6085, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6086, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6087, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6088, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6089, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6090, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6091, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6092, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6093, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6094, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(698, 6098), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6124, 6097), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6125, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6125, 6086), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6127, 6087), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6128, 6088), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6129, 6089), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6130, 6090), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6131, 6091), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6132, 6092), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6133, 6093), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6134, 6094), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6135, 6072), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6136, 6073), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6137, 6074), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6138, 6075), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6139, 6076), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6140, 6077), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6141, 6078), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6142, 6079), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6143, 6080), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6144, 6081), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6145, 6082), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6146, 6083), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6147, 6084), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6148, 6085), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6149, 6101), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6102), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6103), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6104), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6105), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6106), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6107), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6108), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6109), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6110), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6111), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6112), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6113), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6114), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6115), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6116), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6117), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6118), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6119), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6120), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6121), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6122), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6123), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6149, 6126), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(327, 6173), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(540, 6174), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(327, 243), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(6175, 6175), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(6176, 6176), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(699, 6177), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(541, 6178), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(6150, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6151, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6152, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6153, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6154, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6155, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6156, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6157, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6158, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6159, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6160, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6161, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6162, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6163, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6164, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6165, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6166, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6167, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6168, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6169, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6170, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6171, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6172, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(699, 6176), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6202, 6175), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6203, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6203, 6164), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6205, 6165), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6206, 6166), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6207, 6167), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6208, 6168), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6209, 6169), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6210, 6170), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6211, 6171), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6212, 6172), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6213, 6150), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6214, 6151), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6215, 6152), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6216, 6153), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6217, 6154), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6218, 6155), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6219, 6156), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6220, 6157), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6221, 6158), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6222, 6159), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6223, 6160), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6224, 6161), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6225, 6162), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6226, 6163), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6227, 6179), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6180), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6181), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6182), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6183), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6184), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6185), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6186), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6187), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6188), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6189), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6190), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6191), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6192), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6193), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6194), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6195), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6196), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6197), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6198), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6199), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6200), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6201), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6227, 6204), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(328, 6251), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(542, 6252), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(328, 244), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(6253, 6253), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(6254, 6254), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(700, 6255), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(543, 6256), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(6228, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6229, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6230, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6231, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6232, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6233, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6234, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6235, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6236, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6237, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6238, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6239, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6240, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6241, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6242, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6243, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6244, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6245, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6246, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6247, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6248, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6249, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6250, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(700, 6254), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6280, 6253), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6281, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6281, 6242), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6283, 6243), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6284, 6244), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6285, 6245), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6286, 6246), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6287, 6247), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6288, 6248), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6289, 6249), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6290, 6250), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6291, 6228), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6292, 6229), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6293, 6230), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6294, 6231), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6295, 6232), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6296, 6233), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6297, 6234), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6298, 6235), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6299, 6236), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6300, 6237), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6301, 6238), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6302, 6239), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6303, 6240), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6304, 6241), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6305, 6257), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6258), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6259), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6260), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6261), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6262), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6263), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6264), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6265), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6266), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6267), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6268), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6269), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6270), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6271), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6272), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6273), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6274), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6275), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6276), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6277), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6278), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6279), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6305, 6282), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(329, 6329), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(544, 6330), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(329, 245), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(6331, 6331), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(6332, 6332), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(701, 6333), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(545, 6334), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(6306, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6307, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6308, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6309, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6310, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6311, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6312, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6313, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6314, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6315, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6316, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6317, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6318, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6319, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6320, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6321, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6322, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6323, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6324, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6325, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6326, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6327, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6328, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(701, 6332), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6358, 6331), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6359, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6359, 6320), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6361, 6321), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6362, 6322), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6363, 6323), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6364, 6324), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6365, 6325), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6366, 6326), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6367, 6327), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6368, 6328), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6369, 6306), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6370, 6307), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6371, 6308), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6372, 6309), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6373, 6310), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6374, 6311), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6375, 6312), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6376, 6313), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6377, 6314), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6378, 6315), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6379, 6316), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6380, 6317), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6381, 6318), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6382, 6319), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6383, 6335), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6336), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6337), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6338), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6339), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6340), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6341), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6342), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6343), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6344), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6345), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6346), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6347), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6348), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6349), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6350), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6351), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6352), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6353), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6354), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6355), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6356), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6357), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6383, 6360), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(330, 6407), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(546, 6408), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(330, 246), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(6409, 6409), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(6410, 6410), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(702, 6411), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(547, 6412), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(6384, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6385, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6386, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6387, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6388, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6389, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6390, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6391, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6392, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6393, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6394, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6395, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6396, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6397, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6398, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6399, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6400, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6401, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6402, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6403, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6404, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6405, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6406, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(702, 6410), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6436, 6409), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6437, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6437, 6398), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6439, 6399), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6440, 6400), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6441, 6401), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6442, 6402), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6443, 6403), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6444, 6404), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6445, 6405), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6446, 6406), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6447, 6384), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6448, 6385), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6449, 6386), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6450, 6387), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6451, 6388), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6452, 6389), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6453, 6390), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6454, 6391), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6455, 6392), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6456, 6393), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6457, 6394), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6458, 6395), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6459, 6396), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6460, 6397), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6461, 6413), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6414), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6415), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6416), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6417), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6418), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6419), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6420), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6421), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6422), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6423), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6424), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6425), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6426), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6427), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6428), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6429), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6430), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6431), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6432), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6433), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6434), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6435), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6461, 6438), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(332, 6485), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(548, 6486), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(332, 247), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(6487, 6487), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(6488, 6488), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(703, 6489), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(549, 6490), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(6462, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6463, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6464, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6465, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6466, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6467, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6468, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6469, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6470, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6471, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6472, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6473, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6474, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6475, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6476, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6477, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6478, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6479, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6480, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6481, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6482, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6483, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6484, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(703, 6488), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6514, 6487), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6515, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6515, 6476), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6517, 6477), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6518, 6478), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6519, 6479), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6520, 6480), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6521, 6481), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6522, 6482), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6523, 6483), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6524, 6484), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6525, 6462), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6526, 6463), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6527, 6464), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6528, 6465), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6529, 6466), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6530, 6467), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6531, 6468), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6532, 6469), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6533, 6470), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6534, 6471), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6535, 6472), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6536, 6473), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6537, 6474), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6538, 6475), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6539, 6491), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6492), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6493), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6494), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6495), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6496), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6497), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6498), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6499), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6500), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6501), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6502), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6503), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6504), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6505), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6506), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6507), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6508), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6509), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6510), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6511), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6512), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6513), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6539, 6516), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(334, 6563), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(550, 6564), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(334, 248), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(6565, 6565), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(6566, 6566), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(704, 6567), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(551, 6568), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(6540, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6541, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6542, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6543, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6544, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6545, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6546, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6547, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6548, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6549, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6550, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6551, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6552, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6553, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6554, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6555, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6556, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6557, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6558, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6559, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6560, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6561, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6562, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(704, 6566), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6592, 6565), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6593, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6593, 6554), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6595, 6555), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6596, 6556), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6597, 6557), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6598, 6558), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6599, 6559), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6600, 6560), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6601, 6561), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6602, 6562), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6603, 6540), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6604, 6541), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6605, 6542), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6606, 6543), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6607, 6544), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6608, 6545), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6609, 6546), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6610, 6547), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6611, 6548), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6612, 6549), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6613, 6550), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6614, 6551), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6615, 6552), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6616, 6553), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6617, 6569), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6570), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6571), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6572), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6573), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6574), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6575), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6576), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6577), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6578), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6579), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6580), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6581), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6582), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6583), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6584), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6585), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6586), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6587), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6588), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6589), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6590), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6591), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6617, 6594), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(336, 6641), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(552, 6642), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(336, 249), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(6643, 6643), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(6644, 6644), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(705, 6645), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(553, 6646), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(6618, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6619, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6620, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6621, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6622, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6623, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6624, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6625, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6626, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6627, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6628, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6629, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6630, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6631, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6632, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6633, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6634, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6635, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6636, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6637, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6638, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6639, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6640, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(705, 6644), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6670, 6643), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6671, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6671, 6632), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6673, 6633), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6674, 6634), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6675, 6635), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6676, 6636), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6677, 6637), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6678, 6638), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6679, 6639), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6680, 6640), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6681, 6618), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6682, 6619), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6683, 6620), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6684, 6621), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6685, 6622), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6686, 6623), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6687, 6624), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6688, 6625), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6689, 6626), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6690, 6627), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6691, 6628), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6692, 6629), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6693, 6630), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6694, 6631), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6695, 6647), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6648), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6649), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6650), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6651), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6652), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6653), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6654), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6655), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6656), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6657), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6658), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6659), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6660), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6661), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6662), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6663), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6664), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6665), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6666), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6667), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6668), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6669), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6695, 6672), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(338, 6719), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(554, 6720), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(338, 250), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(6721, 6721), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(6722, 6722), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(706, 6723), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(555, 6724), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(6696, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6697, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6698, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6699, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6700, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6701, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6702, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6703, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6704, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6705, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6706, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6707, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6708, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6709, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6710, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6711, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6712, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6713, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6714, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6715, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6716, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6717, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6718, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(706, 6722), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6748, 6721), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6749, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6749, 6710), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6751, 6711), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6752, 6712), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6753, 6713), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6754, 6714), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6755, 6715), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6756, 6716), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6757, 6717), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6758, 6718), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6759, 6696), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6760, 6697), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6761, 6698), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6762, 6699), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6763, 6700), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6764, 6701), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6765, 6702), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6766, 6703), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6767, 6704), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6768, 6705), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6769, 6706), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6770, 6707), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6771, 6708), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6772, 6709), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6773, 6725), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6726), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6727), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6728), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6729), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6730), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6731), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6732), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6733), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6734), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6735), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6736), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6737), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6738), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6739), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6740), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6741), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6742), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6743), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6744), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6745), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6746), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6747), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6773, 6750), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(509, 6797), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(556, 6798), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(509, 251), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(6799, 6799), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(6800, 6800), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(707, 6801), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(557, 6802), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(6774, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6775, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6776, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6777, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6778, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6779, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6780, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6781, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6782, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6783, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6784, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6785, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6786, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6787, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6788, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6789, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6790, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6791, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6792, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6793, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6794, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6795, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6796, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(707, 6800), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6826, 6799), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6827, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6827, 6788), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6829, 6789), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6830, 6790), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6831, 6791), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6832, 6792), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6833, 6793), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6834, 6794), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6835, 6795), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6836, 6796), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6837, 6774), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6838, 6775), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6839, 6776), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6840, 6777), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6841, 6778), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6842, 6779), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6843, 6780), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6844, 6781), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6845, 6782), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6846, 6783), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6847, 6784), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6848, 6785), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6849, 6786), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6850, 6787), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6851, 6803), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6804), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6805), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6806), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6807), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6808), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6809), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6810), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6811), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6812), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6813), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6814), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6815), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6816), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6817), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6818), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6819), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6820), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6821), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6822), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6823), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6824), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6825), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6851, 6828), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(510, 6875), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(558, 6876), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(510, 252), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(6877, 6877), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(6878, 6878), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(708, 6879), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(559, 6880), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(6852, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6853, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6854, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6855, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6856, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6857, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6858, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6859, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6860, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6861, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6862, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6863, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6864, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6865, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6866, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6867, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6868, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6869, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6870, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6871, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6872, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6873, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6874, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(708, 6878), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6904, 6877), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6905, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6905, 6866), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6907, 6867), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6908, 6868), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6909, 6869), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6910, 6870), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6911, 6871), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6912, 6872), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6913, 6873), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6914, 6874), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6915, 6852), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6916, 6853), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6917, 6854), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6918, 6855), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6919, 6856), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6920, 6857), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6921, 6858), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6922, 6859), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6923, 6860), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6924, 6861), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6925, 6862), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6926, 6863), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6927, 6864), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6928, 6865), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6929, 6881), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6882), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6883), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6884), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6885), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6886), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6887), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6888), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6889), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6890), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6891), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6892), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6893), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6894), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6895), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6896), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6897), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6898), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6899), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6900), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6901), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6902), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6903), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6929, 6906), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(511, 6953), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(560, 6954), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(511, 253), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(6955, 6955), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(6956, 6956), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(710, 6957), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(561, 6958), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(6930, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6931, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6932, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6933, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6934, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6935, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6936, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6937, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6938, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6939, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6940, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6941, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6942, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6943, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6944, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6945, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6946, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6947, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6948, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6949, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6950, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6951, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(6952, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(710, 6956), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6982, 6955), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(6983, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(6983, 6944), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6985, 6945), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6986, 6946), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6987, 6947), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6988, 6948), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6989, 6949), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6990, 6950), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6991, 6951), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6992, 6952), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6993, 6930), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6994, 6931), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6995, 6932), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6996, 6933), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6997, 6934), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6998, 6935), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(6999, 6936), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7000, 6937), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7001, 6938), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7002, 6939), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7003, 6940), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7004, 6941), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7005, 6942), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7006, 6943), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7007, 6959), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6960), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6961), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6962), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6963), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6964), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6965), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6966), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6967), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6968), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6969), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6970), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6971), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6972), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6973), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6974), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6975), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6976), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6977), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6978), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6979), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6980), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6981), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7007, 6984), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(512, 7031), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(562, 7032), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(512, 254), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(7033, 7033), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(7034, 7034), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(712, 7035), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(563, 7036), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(7008, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7009, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7010, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7011, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7012, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7013, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7014, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7015, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7016, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7017, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7018, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7019, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7020, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7021, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7022, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7023, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7024, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7025, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7026, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7027, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7028, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7029, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7030, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(712, 7034), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(7060, 7033), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(7061, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7061, 7022), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7063, 7023), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7064, 7024), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7065, 7025), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7066, 7026), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7067, 7027), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7068, 7028), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7069, 7029), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7070, 7030), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7071, 7008), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7072, 7009), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7073, 7010), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7074, 7011), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7075, 7012), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7076, 7013), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7077, 7014), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7078, 7015), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7079, 7016), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7080, 7017), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7081, 7018), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7082, 7019), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7083, 7020), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7084, 7021), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7085, 7037), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7038), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7039), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7040), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7041), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7042), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7043), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7044), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7045), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7046), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7047), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7048), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7049), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7050), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7051), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7052), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7053), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7054), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7055), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7056), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7057), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7058), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7059), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7085, 7062), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(513, 7109), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(564, 7110), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(513, 255), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(7111, 7111), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(7112, 7112), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(714, 7113), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(565, 7114), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(7086, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7087, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7088, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7089, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7090, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7091, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7092, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7093, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7094, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7095, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7096, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7097, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7098, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7099, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7100, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7101, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7102, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7103, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7104, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7105, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7106, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7107, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7108, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(714, 7112), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(7138, 7111), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(7139, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7139, 7100), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7141, 7101), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7142, 7102), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7143, 7103), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7144, 7104), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7145, 7105), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7146, 7106), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7147, 7107), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7148, 7108), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7149, 7086), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7150, 7087), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7151, 7088), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7152, 7089), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7153, 7090), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7154, 7091), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7155, 7092), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7156, 7093), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7157, 7094), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7158, 7095), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7159, 7096), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7160, 7097), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7161, 7098), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7162, 7099), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7163, 7115), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7116), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7117), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7118), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7119), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7120), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7121), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7122), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7123), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7124), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7125), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7126), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7127), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7128), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7129), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7130), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7131), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7132), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7133), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7134), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7135), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7136), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7137), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7163, 7140), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(514, 7187), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(566, 7188), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(514, 256), // zirgen/circuit/recursion/poseidon2.cpp:306 +PolyExtStep::Mul(7189, 7189), // zirgen/circuit/recursion/poseidon2.cpp:169 +PolyExtStep::Mul(7190, 7190), // zirgen/circuit/recursion/poseidon2.cpp:170 +PolyExtStep::Sub(716, 7191), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::AndEqz(567, 7192), // zirgen/circuit/recursion/poseidon2.cpp:171 +PolyExtStep::Mul(7164, 217), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7165, 214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7166, 219), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7167, 236), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7168, 213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7169, 222), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7170, 234), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7171, 227), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7172, 220), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7173, 233), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7174, 226), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7175, 231), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7176, 218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7177, 235), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7178, 229), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7179, 216), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7180, 223), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7181, 232), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7182, 230), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7183, 224), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7184, 225), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7185, 221), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(7186, 228), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Mul(716, 7190), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(7216, 7189), // zirgen/circuit/recursion/poseidon2.cpp:173 +PolyExtStep::Mul(7217, 215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7217, 7178), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7219, 7179), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7220, 7180), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7221, 7181), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7222, 7182), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7223, 7183), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7224, 7184), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7225, 7185), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7226, 7186), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7227, 7164), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7228, 7165), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7229, 7166), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7230, 7167), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7231, 7168), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7232, 7169), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7233, 7170), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7234, 7171), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7235, 7172), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7236, 7173), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7237, 7174), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7238, 7175), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7239, 7176), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7240, 7177), // zirgen/circuit/recursion/poseidon2.cpp:160 +PolyExtStep::Add(7241, 7218), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7193), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7194), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7195), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7196), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7197), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7198), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7199), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7200), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7201), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7202), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7203), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7204), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7205), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7206), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7207), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7208), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7209), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7210), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7211), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7212), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7213), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7214), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Add(7241, 7215), // zirgen/circuit/recursion/poseidon2.cpp:163 +PolyExtStep::Sub(515, 7242), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::AndEqz(568, 7266), // zirgen/circuit/recursion/poseidon2.cpp:311 +PolyExtStep::Add(7242, 257), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(316, 7267), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(569, 7268), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7257, 258), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(288, 7269), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(570, 7270), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7258, 259), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(289, 7271), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(571, 7272), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7259, 260), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(290, 7273), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(572, 7274), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7260, 261), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(291, 7275), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(573, 7276), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7261, 262), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(292, 7277), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(574, 7278), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7262, 263), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(293, 7279), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(575, 7280), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7263, 264), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(294, 7281), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(576, 7282), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7264, 265), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(295, 7283), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(577, 7284), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7265, 266), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(296, 7285), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(578, 7286), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7243, 267), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(287, 7287), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(579, 7288), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7244, 268), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(430, 7289), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(580, 7290), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7245, 269), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(505, 7291), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(581, 7292), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7246, 270), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(476, 7293), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(582, 7294), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7247, 271), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(477, 7295), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(583, 7296), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7248, 272), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(478, 7297), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(584, 7298), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7249, 273), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(479, 7299), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(585, 7300), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7250, 274), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(480, 7301), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(586, 7302), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7251, 275), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(481, 7303), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(587, 7304), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7252, 276), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(482, 7305), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(588, 7306), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7253, 277), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(483, 7307), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(589, 7308), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7254, 278), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(484, 7309), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(590, 7310), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7255, 279), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(485, 7311), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(591, 7312), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::Add(7256, 280), // zirgen/circuit/recursion/poseidon2.cpp:343 +PolyExtStep::Sub(619, 7313), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndEqz(592, 7314), // zirgen/circuit/recursion/poseidon2.cpp:344 +PolyExtStep::AndCond(526, 5627, 593), // components/mux.h:59 +PolyExtStep::Get(22), // top(recursion::Top)/code(recursion::Code)/select(OneHot)/poseidon2_store(Reg)(components/mux.h:59) +PolyExtStep::Mul(475, 2133), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(475, 2134), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(475, 4811), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(475, 4812), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(475, 4813), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(475, 4814), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(475, 4815), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(475, 4816), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(285, 42), // zirgen/circuit/recursion/poseidon2.cpp:366 +PolyExtStep::Mul(506, 4797), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(506, 4798), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(506, 4799), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(506, 4800), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(506, 4801), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(506, 4802), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(506, 4817), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(506, 4818), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(508, 4803), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(508, 4804), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(508, 4805), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(508, 4806), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(508, 4807), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(508, 4808), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(508, 4809), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(508, 4810), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Add(7324, 4417), // zirgen/circuit/recursion/poseidon2.cpp:366 +PolyExtStep::Add(7316, 7331), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Add(7317, 7332), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Add(7318, 7325), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Add(7319, 7326), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Add(7320, 7327), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Add(7321, 7328), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Add(7322, 7329), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Add(7323, 7330), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Add(7342, 7333), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Add(7343, 7334), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Add(7344, 7335), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Add(7345, 7336), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Add(7346, 7337), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Add(7347, 7338), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Add(7348, 7339), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Add(7349, 7340), // zirgen/circuit/recursion/poseidon2.cpp:364 +PolyExtStep::Mul(7350, 7341), // zirgen/circuit/recursion/poseidon2.cpp:368 +PolyExtStep::Sub(320, 286), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::AndEqz(0, 7359), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(321, 7358), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(595, 7360), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(596, 322), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(597, 323), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(598, 324), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Mul(7351, 7341), // zirgen/circuit/recursion/poseidon2.cpp:368 +PolyExtStep::Sub(325, 474), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::AndEqz(599, 7362), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(326, 7361), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(600, 7363), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(601, 327), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(602, 328), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(603, 329), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Mul(7352, 7341), // zirgen/circuit/recursion/poseidon2.cpp:368 +PolyExtStep::Sub(330, 663), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::AndEqz(604, 7365), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(332, 7364), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(605, 7366), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(606, 334), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(607, 336), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(608, 338), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Mul(7353, 7341), // zirgen/circuit/recursion/poseidon2.cpp:368 +PolyExtStep::Add(286, 3), // zirgen/circuit/recursion/poseidon2.cpp:368 +PolyExtStep::Sub(509, 7368), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::AndEqz(609, 7369), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(510, 7367), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(610, 7370), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(611, 511), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(612, 512), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(613, 513), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Mul(7354, 7341), // zirgen/circuit/recursion/poseidon2.cpp:368 +PolyExtStep::Add(286, 4), // zirgen/circuit/recursion/poseidon2.cpp:368 +PolyExtStep::Sub(514, 7372), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::AndEqz(614, 7373), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(515, 7371), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(615, 7374), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(616, 516), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(617, 517), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(618, 518), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Mul(7355, 7341), // zirgen/circuit/recursion/poseidon2.cpp:368 +PolyExtStep::Add(286, 5), // zirgen/circuit/recursion/poseidon2.cpp:368 +PolyExtStep::Sub(519, 7376), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::AndEqz(619, 7377), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(521, 7375), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(620, 7378), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(621, 523), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(622, 525), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(623, 527), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Mul(7356, 7341), // zirgen/circuit/recursion/poseidon2.cpp:368 +PolyExtStep::Add(286, 6), // zirgen/circuit/recursion/poseidon2.cpp:368 +PolyExtStep::Sub(698, 7380), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::AndEqz(624, 7381), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(699, 7379), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(625, 7382), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(626, 700), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(627, 701), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(628, 702), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Mul(7357, 7341), // zirgen/circuit/recursion/poseidon2.cpp:368 +PolyExtStep::Add(286, 7), // zirgen/circuit/recursion/poseidon2.cpp:368 +PolyExtStep::Sub(703, 7384), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::AndEqz(629, 7385), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(704, 7383), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(630, 7386), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(631, 705), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(632, 706), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(633, 707), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(316, 2133), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(634, 7387), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(288, 2134), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(635, 7388), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(289, 4811), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(636, 7389), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(290, 4812), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(637, 7390), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(291, 4813), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(638, 7391), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(292, 4814), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(639, 7392), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(293, 4815), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(640, 7393), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(294, 4816), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(641, 7394), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(295, 4817), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(642, 7395), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(296, 4818), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(643, 7396), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(287, 4797), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(644, 7397), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(430, 4798), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(645, 7398), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(505, 4799), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(646, 7399), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(476, 4800), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(647, 7400), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(477, 4801), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(648, 7401), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(478, 4802), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(649, 7402), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(479, 4803), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(650, 7403), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(480, 4804), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(651, 7404), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(481, 4805), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(652, 7405), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(482, 4806), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(653, 7406), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(483, 4807), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(654, 7407), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(484, 4808), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(655, 7408), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(485, 4809), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(656, 7409), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::Sub(619, 4810), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndEqz(657, 7410), // zirgen/circuit/recursion/poseidon2.cpp:371 +PolyExtStep::AndCond(594, 7315, 658), // components/mux.h:59 +PolyExtStep::Get(23), // top(recursion::Top)/code(recursion::Code)/select(OneHot)/checked_bytes(Reg)(components/mux.h:59) +PolyExtStep::Sub(320, 285), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::AndEqz(0, 7412), // zirgen/circuit/recursion/wom.cpp:92 +PolyExtStep::Mul(694, 694), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Mul(694, 665), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Mul(694, 666), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Mul(694, 667), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Mul(665, 667), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Mul(666, 667), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Mul(667, 667), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Mul(321, 694), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(321, 665), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(321, 666), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(321, 667), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(322, 667), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(323, 667), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(324, 667), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(665, 665), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Mul(665, 666), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Mul(666, 666), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Mul(322, 694), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(322, 665), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(322, 666), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(323, 694), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(323, 665), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(323, 666), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(324, 694), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(324, 665), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(324, 666), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(7419, 11), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Mul(7426, 11), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Add(7414, 7414), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Add(7415, 7427), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Add(7416, 7428), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Add(7417, 7429), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Add(7418, 7418), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Add(7421, 7430), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Add(7422, 7431), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Add(7423, 7432), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Add(7424, 7435), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Add(7425, 7438), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(7445, 11), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Mul(7450, 11), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Add(7442, 7415), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Add(7443, 7428), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Add(7444, 7417), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Add(7447, 7433), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Add(7448, 7434), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Add(7449, 7437), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Add(7453, 7439), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Add(7454, 7416), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Add(7441, 7451), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Add(7456, 7440), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Add(7457, 7436), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Add(7446, 7452), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Mul(7455, 11), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Mul(7458, 11), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Add(7413, 7465), // zirgen/circuit/recursion/checked_bytes.cpp:50 +PolyExtStep::Add(7420, 7466), // zirgen/circuit/recursion/checked_bytes.cpp:49 +PolyExtStep::Sub(668, 7467), // zirgen/components/fpext.cpp:38 +PolyExtStep::AndEqz(660, 7469), // zirgen/components/fpext.cpp:38 +PolyExtStep::Sub(669, 7461), // zirgen/components/fpext.cpp:38 +PolyExtStep::AndEqz(661, 7470), // zirgen/components/fpext.cpp:38 +PolyExtStep::Sub(670, 7459), // zirgen/components/fpext.cpp:38 +PolyExtStep::AndEqz(662, 7471), // zirgen/components/fpext.cpp:38 +PolyExtStep::Sub(671, 7460), // zirgen/components/fpext.cpp:38 +PolyExtStep::AndEqz(663, 7472), // zirgen/components/fpext.cpp:38 +PolyExtStep::Mul(668, 668), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Mul(668, 669), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Mul(668, 670), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Mul(668, 671), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Mul(668, 694), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(668, 665), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(668, 666), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(668, 667), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(668, 321), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(668, 322), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(668, 323), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(668, 324), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(669, 671), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Mul(669, 667), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(669, 324), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(670, 671), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Mul(670, 667), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(670, 324), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(671, 671), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Mul(671, 667), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(671, 324), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(669, 669), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Mul(669, 670), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Mul(669, 694), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(669, 665), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(669, 666), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(669, 321), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(669, 322), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(669, 323), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(670, 670), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Mul(670, 694), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(670, 665), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(670, 666), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(670, 321), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(670, 322), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(670, 323), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(671, 694), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(671, 665), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(671, 666), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(671, 321), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(671, 322), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(671, 323), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(7491, 11), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Mul(7492, 11), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(7493, 11), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Add(7474, 7474), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Add(7475, 7494), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Add(7476, 7495), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Add(7478, 7496), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Add(7479, 7497), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Add(7480, 7498), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Add(7482, 7499), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Add(7483, 7500), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Add(7484, 7501), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Add(7485, 7502), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Add(7486, 7505), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Add(7487, 7508), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Add(7488, 7488), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Add(7489, 7511), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Add(7490, 7514), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(7530, 11), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Mul(7531, 11), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(7532, 11), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Add(7518, 7533), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Add(7519, 7475), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Add(7520, 7495), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Add(7521, 7534), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Add(7522, 7503), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Add(7523, 7504), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Add(7525, 7506), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Add(7526, 7507), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Add(7527, 7485), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Add(7528, 7510), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Add(7529, 7513), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Add(7537, 7515), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Add(7538, 7476), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Add(7540, 7516), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Add(7541, 7509), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Add(7542, 7517), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Add(7543, 7512), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Add(7524, 7535), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(7536, 667), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7536, 324), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7539, 324), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7536, 694), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7536, 665), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7536, 666), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7536, 321), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7536, 322), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7536, 323), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7539, 321), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7539, 322), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7539, 323), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7544, 11), // zirgen/circuit/recursion/checked_bytes.cpp:55 +PolyExtStep::Mul(7545, 11), // zirgen/circuit/recursion/checked_bytes.cpp:53 +PolyExtStep::Mul(7546, 11), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Add(7473, 7566), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Add(7477, 7567), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Add(7481, 7568), // zirgen/circuit/recursion/checked_bytes.cpp:52 +PolyExtStep::Mul(7547, 667), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7547, 324), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7548, 667), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7548, 324), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7549, 324), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7550, 324), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7569, 694), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7569, 665), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7569, 666), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7569, 667), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7569, 321), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7569, 322), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7569, 323), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7569, 324), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7570, 321), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7570, 322), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7570, 323), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7570, 324), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7547, 694), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7547, 665), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7547, 666), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7547, 321), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7547, 322), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7547, 323), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7548, 694), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7548, 665), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7548, 666), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7548, 321), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7548, 322), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7548, 323), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7549, 321), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7549, 322), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7549, 323), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7550, 321), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7550, 322), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7550, 323), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7574, 11), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7575, 11), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7577, 11), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Add(7572, 7598), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Add(7573, 7601), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Add(7576, 7607), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Add(7554, 7592), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Add(7555, 7595), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Add(7556, 7604), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Add(7579, 7557), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Add(7580, 7558), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Add(7581, 7559), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Add(7583, 7560), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Add(7584, 7561), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Add(7585, 7562), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Add(7587, 7563), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Add(7588, 7564), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Add(7589, 7565), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7611, 11), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7612, 11), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7613, 11), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Add(7614, 7597), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Add(7615, 7600), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Add(7616, 7606), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Add(7618, 7590), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Add(7619, 7591), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Add(7621, 7593), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Add(7622, 7594), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Add(7624, 7602), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Add(7625, 7603), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Add(7632, 7608), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Add(7633, 7596), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Add(7634, 7609), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Add(7635, 7599), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Add(7636, 7610), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Add(7637, 7605), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Add(7617, 7626), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Add(7620, 7627), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Add(7623, 7628), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Mul(7629, 11), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Mul(7630, 11), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Mul(7631, 11), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Add(7578, 7647), // zirgen/circuit/recursion/checked_bytes.cpp:57 +PolyExtStep::Add(7582, 7648), // zirgen/circuit/recursion/checked_bytes.cpp:56 +PolyExtStep::Add(7586, 7649), // zirgen/circuit/recursion/checked_bytes.cpp:54 +PolyExtStep::Sub(672, 7650), // zirgen/components/fpext.cpp:38 +PolyExtStep::AndEqz(664, 7653), // zirgen/components/fpext.cpp:38 +PolyExtStep::Sub(673, 7644), // zirgen/components/fpext.cpp:38 +PolyExtStep::AndEqz(665, 7654), // zirgen/components/fpext.cpp:38 +PolyExtStep::Sub(674, 7638), // zirgen/components/fpext.cpp:38 +PolyExtStep::AndEqz(666, 7655), // zirgen/components/fpext.cpp:38 +PolyExtStep::Sub(808, 7639), // zirgen/components/fpext.cpp:38 +PolyExtStep::AndEqz(667, 7656), // zirgen/components/fpext.cpp:38 +PolyExtStep::Mul(672, 7462), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(672, 7463), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(672, 7464), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(672, 7468), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(672, 668), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(672, 669), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(672, 670), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(672, 671), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(672, 694), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(672, 665), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(672, 666), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(672, 667), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(672, 321), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(672, 322), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(672, 323), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(672, 324), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(673, 7463), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(673, 671), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(673, 667), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(673, 324), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(674, 7463), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(674, 671), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(674, 667), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(674, 324), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(808, 7463), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(808, 671), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(808, 667), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(808, 324), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(673, 7462), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(673, 7464), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(673, 7468), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(673, 668), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(673, 669), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(673, 670), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(673, 694), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(673, 665), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(673, 666), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(673, 321), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(673, 322), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(673, 323), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(674, 7462), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(674, 7464), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(674, 7468), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(674, 668), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(674, 669), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(674, 670), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(674, 694), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(674, 665), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(674, 666), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(674, 321), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(674, 322), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(674, 323), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(808, 7462), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(808, 7464), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(808, 7468), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(808, 668), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(808, 669), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(808, 670), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(808, 694), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(808, 665), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(808, 666), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(808, 321), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(808, 322), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(808, 323), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(7681, 11), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(7682, 11), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(7683, 11), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(7684, 11), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Add(7657, 7686), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Add(7658, 7685), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Add(7659, 7687), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Add(7662, 7688), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Add(7663, 7689), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Add(7664, 7690), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Add(7666, 7691), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Add(7667, 7692), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Add(7668, 7693), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Add(7670, 7694), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Add(7671, 7695), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Add(7672, 7696), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Add(7673, 7697), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Add(7674, 7702), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Add(7675, 7705), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Add(7676, 7708), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Add(7677, 7709), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Add(7678, 7714), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Add(7679, 7717), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Add(7680, 7720), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(7741, 11), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(7742, 11), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(7743, 11), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(7744, 11), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Add(7725, 7699), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Add(7726, 7698), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Add(7728, 7746), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Add(7729, 7700), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Add(7730, 7701), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Add(7732, 7703), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Add(7733, 7704), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Add(7735, 7706), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Add(7736, 7707), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Add(7737, 7710), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Add(7738, 7713), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Add(7739, 7716), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Add(7740, 7719), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Add(7749, 7721), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Add(7750, 7711), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Add(7752, 7722), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Add(7753, 7712), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Add(7754, 7723), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Add(7755, 7715), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Add(7756, 7724), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Add(7757, 7718), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Add(7727, 7745), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Add(7731, 7747), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Add(7734, 7748), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(7751, 324), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7751, 321), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7751, 322), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7751, 323), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7758, 11), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Mul(7759, 11), // zirgen/circuit/recursion/checked_bytes.cpp:62 +PolyExtStep::Mul(7760, 11), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Mul(7761, 11), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Add(7661, 7778), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Add(7660, 7777), // zirgen/circuit/recursion/checked_bytes.cpp:61 +PolyExtStep::Add(7665, 7779), // zirgen/circuit/recursion/checked_bytes.cpp:60 +PolyExtStep::Add(7669, 7780), // zirgen/circuit/recursion/checked_bytes.cpp:59 +PolyExtStep::Mul(7764, 324), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7765, 324), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7781, 321), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7781, 322), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7781, 323), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7781, 324), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7764, 321), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7764, 322), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7764, 323), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7765, 321), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7765, 322), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7765, 323), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7786, 11), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Add(7785, 7796), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Add(7773, 7793), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Add(7788, 7774), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Add(7789, 7775), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Add(7790, 7776), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7798, 11), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Add(7799, 7795), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Add(7801, 7791), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Add(7802, 7792), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Add(7805, 7797), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Add(7806, 7794), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Add(7800, 7803), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Mul(7804, 11), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Add(7787, 7810), // zirgen/circuit/recursion/checked_bytes.cpp:63 +PolyExtStep::Sub(509, 1), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(509, 2), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(509, 3), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(509, 7812), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(7815, 7813), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(7816, 7814), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::AndEqz(668, 7817), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(699, 281), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(699, 4), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(699, 8), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(699, 7819), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(7821, 7820), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(7822, 7818), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::AndEqz(669, 7823), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(908, 14), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(908, 15), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(908, 282), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(908, 7824), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(7827, 7825), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(7828, 7826), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::AndEqz(670, 7829), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(980, 17), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(980, 283), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(980, 16), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(980, 7832), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(7833, 7830), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(7834, 7831), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::AndEqz(671, 7835), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Add(509, 699), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(7836, 908), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(7837, 980), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Mul(317, 19), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Mul(7839, 4450), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Sub(510, 1), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(510, 2), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(510, 3), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(7840, 7838), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Mul(510, 7841), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(7845, 7842), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(7846, 7843), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::AndEqz(672, 7847), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(700, 281), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(700, 4), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(700, 8), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(700, 7849), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(7851, 7850), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(7852, 7848), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::AndEqz(673, 7853), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(909, 14), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(909, 15), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(909, 282), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(909, 7854), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(7857, 7855), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(7858, 7856), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::AndEqz(674, 7859), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(981, 17), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(981, 283), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(981, 16), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(981, 7862), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(7863, 7860), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(7864, 7861), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::AndEqz(675, 7865), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Add(510, 700), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(7866, 909), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(7867, 981), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Mul(7868, 321), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7868, 322), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7868, 323), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7868, 324), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7839, 4451), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Sub(511, 1), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(511, 2), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(511, 3), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(7873, 7868), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Mul(511, 7874), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(7878, 7875), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(7879, 7876), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(7838, 7869), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::AndEqz(676, 7880), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(701, 281), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(701, 4), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(701, 8), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(701, 7883), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(7885, 7884), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(7886, 7882), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::AndEqz(677, 7887), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(917, 14), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(917, 15), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(917, 282), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(917, 7888), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(7891, 7889), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(7892, 7890), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::AndEqz(678, 7893), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(989, 17), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(989, 283), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(989, 16), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(989, 7896), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(7897, 7894), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(7898, 7895), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::AndEqz(679, 7899), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Add(511, 701), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(7900, 917), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(7901, 989), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Mul(7902, 694), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7902, 665), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7902, 666), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7902, 667), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7839, 4452), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Sub(512, 1), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(512, 2), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(512, 3), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(7907, 7902), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Mul(512, 7908), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(7912, 7909), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(7913, 7910), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(7870, 7904), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(7871, 7905), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(7872, 7906), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(7881, 7903), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::AndEqz(680, 7914), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(702, 281), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(702, 4), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(702, 8), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(702, 7920), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(7922, 7921), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(7923, 7919), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::AndEqz(681, 7924), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(918, 14), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(918, 15), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(918, 282), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(918, 7925), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(7928, 7926), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(7929, 7927), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::AndEqz(682, 7930), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(990, 17), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(990, 283), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(990, 16), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(990, 7933), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(7934, 7931), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(7935, 7932), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::AndEqz(683, 7936), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Add(512, 702), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(7937, 918), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(7938, 990), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Mul(7939, 7462), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7939, 7463), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7939, 7464), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7939, 7468), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7839, 4453), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Sub(513, 1), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(513, 2), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(513, 3), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(7944, 7939), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Mul(513, 7945), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(7949, 7946), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(7950, 7947), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(7915, 7942), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(7916, 7940), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(7917, 7941), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(7918, 7943), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::AndEqz(684, 7951), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(703, 281), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(703, 4), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(703, 8), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(703, 7957), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(7959, 7958), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(7960, 7956), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::AndEqz(685, 7961), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(926, 14), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(926, 15), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(926, 282), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(926, 7962), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(7965, 7963), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(7966, 7964), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::AndEqz(686, 7967), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(998, 17), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(998, 283), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(998, 16), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(998, 7970), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(7971, 7968), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(7972, 7969), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::AndEqz(687, 7973), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Add(513, 703), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(7974, 926), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(7975, 998), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Mul(7976, 668), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7976, 669), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7976, 670), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7976, 671), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7839, 4454), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Sub(514, 1), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(514, 2), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(514, 3), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(7981, 7976), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Mul(514, 7982), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(7986, 7983), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(7987, 7984), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(7952, 7978), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(7953, 7979), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(7954, 7980), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(7955, 7977), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::AndEqz(688, 7988), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(704, 281), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(704, 4), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(704, 8), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(704, 7994), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(7996, 7995), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(7997, 7993), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::AndEqz(689, 7998), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(927, 14), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(927, 15), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(927, 282), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(927, 7999), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8002, 8000), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8003, 8001), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::AndEqz(690, 8004), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(999, 17), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(999, 283), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(999, 16), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(999, 8007), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8008, 8005), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8009, 8006), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::AndEqz(691, 8010), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Add(514, 704), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8011, 927), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8012, 999), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Mul(8013, 7551), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8013, 7552), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8013, 7553), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8013, 7571), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7839, 4455), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Sub(515, 1), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(515, 2), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(515, 3), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8018, 8013), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Mul(515, 8019), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8023, 8020), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8024, 8021), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(7989, 8016), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(7990, 8014), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(7991, 8015), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(7992, 8017), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::AndEqz(692, 8025), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(705, 281), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(705, 4), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(705, 8), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(705, 8031), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8033, 8032), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8034, 8030), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::AndEqz(693, 8035), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(935, 14), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(935, 15), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(935, 282), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(935, 8036), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8039, 8037), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8040, 8038), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::AndEqz(694, 8041), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(1007, 17), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1007, 283), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1007, 16), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(1007, 8044), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8045, 8042), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8046, 8043), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::AndEqz(695, 8047), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Add(515, 705), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8048, 935), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8049, 1007), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Mul(8050, 7549), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8050, 7550), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8050, 7539), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8050, 7570), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7839, 4456), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Sub(516, 1), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(516, 2), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(516, 3), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8055, 8050), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Mul(516, 8056), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8060, 8057), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8061, 8058), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8026, 8053), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8027, 8051), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8028, 8052), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8029, 8054), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::AndEqz(696, 8062), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(706, 281), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(706, 4), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(706, 8), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(706, 8068), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8070, 8069), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8071, 8067), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::AndEqz(697, 8072), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(936, 14), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(936, 15), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(936, 282), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(936, 8073), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8076, 8074), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8077, 8075), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::AndEqz(698, 8078), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(1008, 17), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1008, 283), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1008, 16), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(1008, 8081), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8082, 8079), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8083, 8080), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::AndEqz(699, 8084), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Add(516, 706), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8085, 936), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8086, 1008), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Mul(8087, 7642), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8087, 7643), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8087, 7646), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8087, 7652), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7839, 4457), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Sub(517, 1), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(517, 2), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(517, 3), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8092, 8087), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Mul(517, 8093), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8097, 8094), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8098, 8095), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8063, 8090), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8064, 8088), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8065, 8089), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8066, 8091), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::AndEqz(700, 8099), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(707, 281), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(707, 4), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(707, 8), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(707, 8105), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8107, 8106), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8108, 8104), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::AndEqz(701, 8109), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(944, 14), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(944, 15), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(944, 282), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(944, 8110), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8113, 8111), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8114, 8112), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::AndEqz(702, 8115), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(1016, 17), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1016, 283), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1016, 16), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(1016, 8118), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8119, 8116), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8120, 8117), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::AndEqz(703, 8121), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Add(517, 707), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8122, 944), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8123, 1016), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Mul(8124, 7547), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8124, 7548), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8124, 7536), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8124, 7569), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7839, 4458), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Sub(518, 1), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(518, 2), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(518, 3), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8129, 8124), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Mul(518, 8130), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8134, 8131), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8135, 8132), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8100, 8127), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8101, 8125), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8102, 8126), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8103, 8128), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::AndEqz(704, 8136), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(708, 281), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(708, 4), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(708, 8), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(708, 8142), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8144, 8143), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8145, 8141), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::AndEqz(705, 8146), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(945, 14), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(945, 15), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(945, 282), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(945, 8147), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8150, 8148), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8151, 8149), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::AndEqz(706, 8152), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(1017, 17), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1017, 283), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1017, 16), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(1017, 8155), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8156, 8153), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8157, 8154), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::AndEqz(707, 8158), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Add(518, 708), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8159, 945), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8160, 1017), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Mul(8161, 7640), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8161, 7641), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8161, 7645), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8161, 7651), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7839, 4459), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Sub(519, 1), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(519, 2), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(519, 3), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8166, 8161), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Mul(519, 8167), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8171, 8168), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8172, 8169), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8137, 8164), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8138, 8162), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8139, 8163), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8140, 8165), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::AndEqz(708, 8173), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(710, 281), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(710, 4), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(710, 8), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(710, 8179), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8181, 8180), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8182, 8178), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::AndEqz(709, 8183), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(953, 14), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(953, 15), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(953, 282), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(953, 8184), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8187, 8185), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8188, 8186), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::AndEqz(710, 8189), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(1025, 17), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1025, 283), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1025, 16), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(1025, 8192), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8193, 8190), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8194, 8191), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::AndEqz(711, 8195), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Add(519, 710), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8196, 953), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8197, 1025), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Mul(8198, 672), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8198, 673), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8198, 674), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8198, 808), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7839, 4436), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Sub(521, 1), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(521, 2), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(521, 3), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8203, 8198), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Mul(521, 8204), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8208, 8205), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8209, 8206), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8174, 8200), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8175, 8201), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8176, 8202), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8177, 8199), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::AndEqz(712, 8210), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(712, 281), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(712, 4), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(712, 8), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(712, 8216), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8218, 8217), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8219, 8215), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::AndEqz(713, 8220), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(954, 14), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(954, 15), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(954, 282), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(954, 8221), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8224, 8222), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8225, 8223), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::AndEqz(714, 8226), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(1026, 17), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1026, 283), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1026, 16), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(1026, 8229), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8230, 8227), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8231, 8228), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::AndEqz(715, 8232), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Add(521, 712), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8233, 954), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8234, 1026), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Mul(8235, 7768), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8235, 7769), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8235, 7772), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8235, 7784), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7839, 4437), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Sub(523, 1), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(523, 2), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(523, 3), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8240, 8235), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Mul(523, 8241), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8245, 8242), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8246, 8243), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8211, 8238), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8212, 8236), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8213, 8237), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8214, 8239), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::AndEqz(716, 8247), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(714, 281), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(714, 4), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(714, 8), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(714, 8253), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8255, 8254), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8256, 8252), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::AndEqz(717, 8257), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(962, 14), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(962, 15), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(962, 282), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(962, 8258), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8261, 8259), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8262, 8260), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::AndEqz(718, 8263), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(1034, 17), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1034, 283), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1034, 16), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(1034, 8266), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8267, 8264), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8268, 8265), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::AndEqz(719, 8269), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Add(523, 714), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8270, 962), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8271, 1034), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Mul(8272, 7766), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8272, 7767), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8272, 7771), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8272, 7783), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7839, 4438), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Sub(525, 1), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(525, 2), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(525, 3), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8277, 8272), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Mul(525, 8278), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8282, 8279), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8283, 8280), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8248, 8275), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8249, 8273), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8250, 8274), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8251, 8276), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::AndEqz(720, 8284), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(716, 281), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(716, 4), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(716, 8), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(716, 8290), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8292, 8291), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8293, 8289), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::AndEqz(721, 8294), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(963, 14), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(963, 15), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(963, 282), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(963, 8295), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8298, 8296), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8299, 8297), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::AndEqz(722, 8300), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(1035, 17), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1035, 283), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1035, 16), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(1035, 8303), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8304, 8301), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8305, 8302), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::AndEqz(723, 8306), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Add(525, 716), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8307, 963), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8308, 1035), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Mul(8309, 7762), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8309, 7763), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8309, 7770), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8309, 7782), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7839, 4439), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Sub(527, 1), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(527, 2), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(527, 3), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8314, 8309), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Mul(527, 8315), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8319, 8316), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8320, 8317), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8285, 8312), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8286, 8310), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8287, 8311), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8288, 8313), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::AndEqz(724, 8321), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(899, 281), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(899, 4), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(899, 8), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(899, 8327), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8329, 8328), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8330, 8326), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::AndEqz(725, 8331), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(971, 14), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(971, 15), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(971, 282), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(971, 8332), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8335, 8333), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8336, 8334), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::AndEqz(726, 8337), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(1043, 17), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1043, 283), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1043, 16), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(1043, 8340), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8341, 8338), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8342, 8339), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::AndEqz(727, 8343), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Add(527, 899), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8344, 971), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8345, 1043), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Mul(8346, 7764), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8346, 7765), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8346, 7751), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8346, 7781), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7839, 4440), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Sub(698, 1), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(698, 2), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(698, 3), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8351, 8346), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Mul(698, 8352), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8356, 8353), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Mul(8357, 8354), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Add(8322, 8349), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8323, 8347), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8324, 8348), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8325, 8350), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::AndEqz(728, 8358), // zirgen/circuit/recursion/checked_bytes.cpp:98 +PolyExtStep::Sub(900, 281), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(900, 4), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(900, 8), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(900, 8364), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8366, 8365), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Mul(8367, 8363), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::AndEqz(729, 8368), // zirgen/circuit/recursion/checked_bytes.cpp:99 +PolyExtStep::Sub(972, 14), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(972, 15), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(972, 282), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(972, 8369), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8372, 8370), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Mul(8373, 8371), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::AndEqz(730, 8374), // zirgen/circuit/recursion/checked_bytes.cpp:100 +PolyExtStep::Sub(1044, 17), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1044, 283), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Sub(1044, 16), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(1044, 8377), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8378, 8375), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Mul(8379, 8376), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::AndEqz(731, 8380), // zirgen/circuit/recursion/checked_bytes.cpp:101 +PolyExtStep::Add(698, 900), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8381, 972), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Add(8382, 1044), // zirgen/circuit/recursion/checked_bytes.cpp:103 +PolyExtStep::Mul(8383, 7807), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8383, 7808), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8383, 7809), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(8383, 7811), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Mul(7839, 4441), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Add(8388, 8383), // zirgen/circuit/recursion/checked_bytes.cpp:104 +PolyExtStep::Add(8359, 8386), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8360, 8384), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8361, 8385), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Add(8362, 8387), // zirgen/circuit/recursion/checked_bytes.cpp:106 +PolyExtStep::Sub(325, 286), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::AndEqz(732, 8394), // zirgen/circuit/recursion/wom.cpp:97 +PolyExtStep::Sub(326, 8393), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(733, 8395), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(327, 8390), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(734, 8396), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(328, 8391), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(735, 8397), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Sub(329, 8392), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(736, 8398), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::Add(8207, 8244), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(8281, 8318), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(8355, 8389), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(7844, 7877), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(7911, 7948), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(7985, 8022), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(8059, 8096), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(8133, 8170), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Mul(8399, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(8400, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(8401, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(8402, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(8403, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(8404, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(8405, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(8406, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(8244, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(8318, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(8389, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(7877, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(7948, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(8022, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(8096, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(8170, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(8415, 8406), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(8416, 8401), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(8417, 8400), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(8418, 8403), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(8419, 8402), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(8420, 8405), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(8421, 8404), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(8422, 8399), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(8407, 8423), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(8408, 8424), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(8409, 8425), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(8412, 8428), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(8413, 8429), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(8414, 8430), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(319, 4442), // zirgen/circuit/recursion/checked_bytes.cpp:117 +PolyExtStep::Mul(319, 4444), // zirgen/circuit/recursion/checked_bytes.cpp:117 +PolyExtStep::Mul(319, 4446), // zirgen/circuit/recursion/checked_bytes.cpp:117 +PolyExtStep::Mul(319, 4448), // zirgen/circuit/recursion/checked_bytes.cpp:117 +PolyExtStep::Mul(319, 4443), // zirgen/circuit/recursion/checked_bytes.cpp:117 +PolyExtStep::Mul(319, 4445), // zirgen/circuit/recursion/checked_bytes.cpp:117 +PolyExtStep::Mul(319, 4447), // zirgen/circuit/recursion/checked_bytes.cpp:117 +PolyExtStep::Mul(319, 4449), // zirgen/circuit/recursion/checked_bytes.cpp:117 +PolyExtStep::Add(8423, 8436), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(8424, 8433), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(8425, 8432), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(8428, 8435), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(8429, 8434), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(8430, 8431), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(8410, 8426), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(8411, 8427), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(8437, 8441), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(8438, 8442), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Add(8439, 8443), // zirgen/circuit/recursion/poseidon2.cpp:24 +PolyExtStep::Add(8440, 8444), // zirgen/circuit/recursion/poseidon2.cpp:25 +PolyExtStep::Mul(8453, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(8454, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(8455, 4), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Mul(8456, 4), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Mul(8441, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(8442, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(8443, 2), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Mul(8444, 2), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Mul(462, 7844), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8426, 8452), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(8427, 8451), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(8461, 8454), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(8462, 8453), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(8463, 8456), // zirgen/circuit/recursion/poseidon2.cpp:26 +PolyExtStep::Add(8464, 8455), // zirgen/circuit/recursion/poseidon2.cpp:27 +PolyExtStep::Add(8457, 8468), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(8458, 8469), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(8459, 8470), // zirgen/circuit/recursion/poseidon2.cpp:29 +PolyExtStep::Add(8460, 8471), // zirgen/circuit/recursion/poseidon2.cpp:28 +PolyExtStep::Add(8451, 8434), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8452, 8435), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8468, 8473), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(8469, 8472), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(8470, 8475), // zirgen/circuit/recursion/poseidon2.cpp:31 +PolyExtStep::Add(8471, 8474), // zirgen/circuit/recursion/poseidon2.cpp:30 +PolyExtStep::Add(8476, 8436), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8477, 8431), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8466, 8448), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8467, 8449), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8482, 8432), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8483, 8433), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8484, 8450), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8485, 8445), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8486, 8472), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8487, 8473), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8488, 8446), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8489, 8447), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8490, 8474), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8491, 8475), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8492, 8478), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8493, 8479), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8451, 8494), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8452, 8495), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8431, 8495), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8432, 8494), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8433, 8495), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8434, 8494), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8435, 8495), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8436, 8494), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8472, 8494), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8473, 8495), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8474, 8494), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8475, 8495), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8496, 8480), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8497, 8481), // zirgen/circuit/recursion/poseidon2.cpp:45 +PolyExtStep::Add(8466, 8510), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8467, 8511), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8445, 8511), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8446, 8510), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8447, 8511), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8448, 8510), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8449, 8511), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8450, 8510), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8478, 8510), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8479, 8511), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8480, 8510), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Add(8481, 8511), // zirgen/circuit/recursion/poseidon2.cpp:50 +PolyExtStep::Mul(318, 8513), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8524, 8465), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8525, 4476), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(316, 8526), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(737, 8527), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8498), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 7877), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8528, 8529), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8530, 4659), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(288, 8531), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(738, 8532), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8512), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 7911), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8533, 8534), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8535, 4665), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(289, 8536), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(739, 8537), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8499), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 7948), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8538, 8539), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8540, 4671), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(290, 8541), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(740, 8542), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8518), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 7985), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8543, 8544), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8545, 4677), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(291, 8546), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(741, 8547), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8503), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8022), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8548, 8549), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8550, 4683), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(292, 8551), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(742, 8552), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8517), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8059), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8553, 8554), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8555, 4689), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(293, 8556), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(743, 8557), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8504), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8096), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8558, 8559), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8560, 4695), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(294, 8561), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(744, 8562), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8514), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8133), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8563, 8564), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8565, 4701), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(295, 8566), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(745, 8567), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8505), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8170), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8568, 8569), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8570, 4707), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(296, 8571), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(746, 8572), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8519), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8207), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8573, 8574), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8575, 4713), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(287, 8576), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(747, 8577), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8500), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8244), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8578, 8579), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8580, 4719), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(430, 8581), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(748, 8582), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8516), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8281), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8583, 8584), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8585, 4725), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(505, 8586), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(749, 8587), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8501), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8318), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8588, 8589), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8590, 4731), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(476, 8591), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(750, 8592), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8515), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8355), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8593, 8594), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8595, 4737), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(477, 8596), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(751, 8597), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8502), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8389), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8598, 8599), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8600, 4743), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(478, 8601), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(752, 8602), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8521), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8437), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8603, 8604), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8605, 4749), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(479, 8606), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(753, 8607), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8506), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8441), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8608, 8609), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8610, 4755), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(480, 8611), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(754, 8612), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8520), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8438), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8613, 8614), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8615, 4761), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(481, 8616), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(755, 8617), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8507), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8442), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8618, 8619), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8620, 4767), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(482, 8621), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(756, 8622), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8523), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8439), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8623, 8624), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8625, 4773), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(483, 8626), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(757, 8627), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8508), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8443), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8628, 8629), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8630, 4779), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(484, 8631), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(758, 8632), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8522), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8440), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8633, 8634), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8635, 4785), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(485, 8636), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(759, 8637), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::Mul(318, 8509), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Mul(462, 8444), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8638, 8639), // zirgen/circuit/recursion/checked_bytes.cpp:123 +PolyExtStep::Add(8640, 4791), // zirgen/circuit/recursion/checked_bytes.cpp:124 +PolyExtStep::Sub(619, 8641), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndEqz(760, 8642), // zirgen/circuit/recursion/checked_bytes.cpp:125 +PolyExtStep::AndCond(659, 7411, 761), // components/mux.h:59 +PolyExtStep::AndCond(0, 285, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(763, 317, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(764, 319, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(765, 318, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(766, 475, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(767, 695, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(762, 852, 768), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(769, 4415, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(770, 7315, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(771, 284, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(0, 318, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(773, 475, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(774, 506, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(775, 508, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(776, 507, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(777, 664, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(778, 695, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(772, 852, 779), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(780, 4415, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(781, 7315, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(782, 7411, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Get(40), // top(recursion::Top)/recursion::WomHeader/element(recursion::impl::WomPlonkElement)/addr(Reg)(zirgen/circuit/recursion/wom.cpp:71) +PolyExtStep::Sub(899, 8643), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8644), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8644, 8645), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(0, 8646), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Get(42), // top(recursion::Top)/recursion::WomHeader/element(recursion::impl::WomPlonkElement)/data[0](Reg)(zirgen/circuit/recursion/wom.cpp:78) +PolyExtStep::Sub(8647, 900), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8648), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Get(44), // top(recursion::Top)/recursion::WomHeader/element(recursion::impl::WomPlonkElement)/data[1](Reg)(zirgen/circuit/recursion/wom.cpp:78) +PolyExtStep::Sub(8649, 908), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(785, 8650), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Get(46), // top(recursion::Top)/recursion::WomHeader/element(recursion::impl::WomPlonkElement)/data[2](Reg)(zirgen/circuit/recursion/wom.cpp:78) +PolyExtStep::Sub(8651, 909), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(786, 8652), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Get(48), // top(recursion::Top)/recursion::WomHeader/element(recursion::impl::WomPlonkElement)/data[3](Reg)(zirgen/circuit/recursion/wom.cpp:78) +PolyExtStep::Sub(8653, 917), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(787, 8654), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(784, 8645, 788), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::Sub(918, 899), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8655), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8655, 8656), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(789, 8657), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(900, 926), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8658), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(908, 927), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(791, 8659), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(909, 935), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(792, 8660), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(917, 936), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(793, 8661), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(790, 8656, 794), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::Sub(944, 918), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8662), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8662, 8663), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(795, 8664), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(926, 945), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8665), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(927, 953), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(797, 8666), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(935, 954), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(798, 8667), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(936, 962), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(799, 8668), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(796, 8663, 800), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::Sub(963, 944), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8669), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8669, 8670), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(801, 8671), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(945, 971), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8672), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(953, 972), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(803, 8673), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(954, 980), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(804, 8674), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(962, 981), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(805, 8675), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(802, 8670, 806), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::Sub(989, 963), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8676), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8676, 8677), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(807, 8678), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(971, 990), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8679), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(972, 998), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(809, 8680), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(980, 999), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(810, 8681), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(981, 1007), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(811, 8682), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(808, 8677, 812), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::Sub(1008, 989), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8683), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8683, 8684), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(813, 8685), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(990, 1016), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8686), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(998, 1017), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(815, 8687), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(999, 1025), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(816, 8688), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(1007, 1026), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(817, 8689), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(814, 8684, 818), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::Sub(1034, 1008), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8690), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8690, 8691), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(819, 8692), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(1016, 1035), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8693), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(1017, 1043), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(821, 8694), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(1025, 1044), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(822, 8695), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(1026, 1052), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(823, 8696), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(820, 8691, 824), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::Sub(1053, 1034), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8697), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8697, 8698), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(825, 8699), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(1035, 1061), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8700), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(1043, 1062), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(827, 8701), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(1044, 1070), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(828, 8702), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(1052, 1071), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(829, 8703), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(826, 8698, 830), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::Get(39), // top(recursion::Top)/recursion::WomHeader/element(recursion::impl::WomPlonkElement)/addr(Reg)(compiler/edsl/edsl.h:129) +PolyExtStep::Sub(8704, 1053), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8705), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8705, 8706), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(831, 8707), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Get(41), // top(recursion::Top)/recursion::WomHeader/element(recursion::impl::WomPlonkElement)/data[0](Reg)(zirgen/circuit/recursion/wom.cpp:78) +PolyExtStep::Sub(1061, 8708), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8709), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Get(43), // top(recursion::Top)/recursion::WomHeader/element(recursion::impl::WomPlonkElement)/data[1](Reg)(zirgen/circuit/recursion/wom.cpp:78) +PolyExtStep::Sub(1062, 8710), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(833, 8711), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Get(45), // top(recursion::Top)/recursion::WomHeader/element(recursion::impl::WomPlonkElement)/data[2](Reg)(zirgen/circuit/recursion/wom.cpp:78) +PolyExtStep::Sub(1070, 8712), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(834, 8713), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Get(47), // top(recursion::Top)/recursion::WomHeader/element(recursion::impl::WomPlonkElement)/data[3](Reg)(zirgen/circuit/recursion/wom.cpp:78) +PolyExtStep::Sub(1071, 8714), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(835, 8715), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(832, 8706, 836), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::AndCond(783, 284, 837), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndEqz(0, 8704), // zirgen/circuit/recursion/wom.cpp:22 +PolyExtStep::AndEqz(839, 8708), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(840, 8710), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(841, 8712), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndEqz(842, 8714), // zirgen/circuit/recursion/wom.cpp:61 +PolyExtStep::AndCond(0, 317, 843), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Sub(326, 8643), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8716), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8716, 8717), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(0, 8718), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(8647, 327), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8719), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(8649, 328), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(846, 8720), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(8651, 329), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(847, 8721), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(8653, 330), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(848, 8722), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(845, 8717, 849), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::AndCond(844, 319, 850), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Sub(515, 8643), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8723), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8723, 8724), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(0, 8725), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(8647, 516), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8726), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(8649, 517), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(853, 8727), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(8651, 518), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(854, 8728), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(8653, 519), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(855, 8729), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(852, 8724, 856), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::Sub(1, 646), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(646, 8730), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(857, 8731), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(516, 523), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8732), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(517, 525), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(859, 8733), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(518, 527), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(860, 8734), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(519, 698), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(861, 8735), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(858, 8730, 862), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::Sub(8704, 521), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8736), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8736, 8737), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(863, 8738), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(523, 8708), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8739), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(525, 8710), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(865, 8740), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(527, 8712), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(866, 8741), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(698, 8714), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(867, 8742), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(864, 8737, 868), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::AndCond(851, 318, 869), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(870, 475, 869), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Sub(510, 8643), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8743), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8743, 8744), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(0, 8745), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(8647, 511), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8746), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(8649, 512), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(873, 8747), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(8651, 513), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(874, 8748), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(8653, 514), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(875, 8749), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(872, 8744, 876), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::Sub(8704, 510), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8750), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8750, 8751), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(877, 8752), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(511, 8708), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8753), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(512, 8710), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(879, 8754), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(513, 8712), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(880, 8755), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(514, 8714), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(881, 8756), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(878, 8751, 882), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::AndCond(871, 506, 883), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(884, 508, 883), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(885, 507, 883), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(886, 664, 883), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Sub(698, 8643), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8757), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8757, 8758), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(0, 8759), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(8647, 699), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8760), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(8649, 700), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(889, 8761), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(8651, 701), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(890, 8762), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(8653, 702), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(891, 8763), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(888, 8758, 892), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::Sub(703, 698), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8764), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8764, 8765), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(893, 8766), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(0, 727), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(895, 728), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(896, 729), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(897, 730), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(894, 8765, 898), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::Sub(708, 703), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8767), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8767, 8768), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(899, 8769), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(704, 710), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8770), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(705, 712), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(901, 8771), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(706, 714), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(902, 8772), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(707, 716), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(903, 8773), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(900, 8768, 904), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::Sub(8704, 708), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8774), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8774, 8775), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(905, 8776), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(710, 8708), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8777), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(712, 8710), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(907, 8778), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(714, 8712), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(908, 8779), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(716, 8714), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(909, 8780), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(906, 8775, 910), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::AndCond(887, 695, 911), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(838, 852, 912), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(913, 4415, 837), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Sub(8704, 8643), // zirgen/circuit/recursion/wom.cpp:41 +PolyExtStep::AndEqz(0, 8781), // zirgen/circuit/recursion/wom.cpp:41 +PolyExtStep::Sub(8708, 8647), // zirgen/circuit/recursion/wom.cpp:43 +PolyExtStep::AndEqz(915, 8782), // zirgen/circuit/recursion/wom.cpp:43 +PolyExtStep::Sub(8710, 8649), // zirgen/circuit/recursion/wom.cpp:43 +PolyExtStep::AndEqz(916, 8783), // zirgen/circuit/recursion/wom.cpp:43 +PolyExtStep::Sub(8712, 8651), // zirgen/circuit/recursion/wom.cpp:43 +PolyExtStep::AndEqz(917, 8784), // zirgen/circuit/recursion/wom.cpp:43 +PolyExtStep::Sub(8714, 8653), // zirgen/circuit/recursion/wom.cpp:43 +PolyExtStep::AndEqz(918, 8785), // zirgen/circuit/recursion/wom.cpp:43 +PolyExtStep::AndCond(914, 4796, 919), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(920, 5627, 919), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(921, 7315, 837), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Sub(330, 8643), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8786), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8786, 8787), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(0, 8788), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(8647, 332), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8789), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(8649, 334), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(924, 8790), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(8651, 336), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(925, 8791), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(8653, 338), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(926, 8792), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(923, 8787, 927), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::Sub(8704, 330), // zirgen/circuit/recursion/wom.cpp:72 +PolyExtStep::Sub(1, 8793), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Mul(8793, 8794), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::AndEqz(928, 8795), // zirgen/circuit/recursion/wom.cpp:74 +PolyExtStep::Sub(332, 8708), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(0, 8796), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(334, 8710), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(930, 8797), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(336, 8712), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(931, 8798), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::Sub(338, 8714), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndEqz(932, 8799), // zirgen/circuit/recursion/wom.cpp:78 +PolyExtStep::AndCond(929, 8794, 933), // zirgen/circuit/recursion/wom.cpp:76 +PolyExtStep::AndCond(922, 7411, 934), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(935, 284, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(936, 852, 779), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(937, 4415, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(938, 4796, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(939, 5627, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(940, 7315, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(941, 7411, 0), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::GetGlobal(1, 0), // top(recursion::Top)/recursion::WomHeader/mix[0](FpExtReg)/elem[0](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 1), // top(recursion::Top)/recursion::WomHeader/mix[0](FpExtReg)/elem[1](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 10), // top(recursion::Top)/recursion::WomHeader/mix[2](FpExtReg)/elem[2](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 11), // top(recursion::Top)/recursion::WomHeader/mix[2](FpExtReg)/elem[3](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 12), // top(recursion::Top)/recursion::WomHeader/mix[3](FpExtReg)/elem[0](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 13), // top(recursion::Top)/recursion::WomHeader/mix[3](FpExtReg)/elem[1](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 14), // top(recursion::Top)/recursion::WomHeader/mix[3](FpExtReg)/elem[2](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 15), // top(recursion::Top)/recursion::WomHeader/mix[3](FpExtReg)/elem[3](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 16), // top(recursion::Top)/recursion::WomHeader/mix[4](FpExtReg)/elem[0](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 17), // top(recursion::Top)/recursion::WomHeader/mix[4](FpExtReg)/elem[1](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 18), // top(recursion::Top)/recursion::WomHeader/mix[4](FpExtReg)/elem[2](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 19), // top(recursion::Top)/recursion::WomHeader/mix[4](FpExtReg)/elem[3](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 2), // top(recursion::Top)/recursion::WomHeader/mix[0](FpExtReg)/elem[2](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 3), // top(recursion::Top)/recursion::WomHeader/mix[0](FpExtReg)/elem[3](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 4), // top(recursion::Top)/recursion::WomHeader/mix[1](FpExtReg)/elem[0](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 5), // top(recursion::Top)/recursion::WomHeader/mix[1](FpExtReg)/elem[1](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 6), // top(recursion::Top)/recursion::WomHeader/mix[1](FpExtReg)/elem[2](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 7), // top(recursion::Top)/recursion::WomHeader/mix[1](FpExtReg)/elem[3](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 8), // top(recursion::Top)/recursion::WomHeader/mix[2](FpExtReg)/elem[0](Reg)(components/plonk.h:230) +PolyExtStep::GetGlobal(1, 9), // top(recursion::Top)/recursion::WomHeader/mix[2](FpExtReg)/elem[1](Reg)(components/plonk.h:230) +PolyExtStep::Mul(8800, 8704), // components/plonk.h:230 +PolyExtStep::Mul(8800, 325), // components/plonk.h:230 +PolyExtStep::Mul(8800, 330), // components/plonk.h:230 +PolyExtStep::Mul(8800, 509), // components/plonk.h:230 +PolyExtStep::Mul(8800, 514), // components/plonk.h:230 +PolyExtStep::Mul(8800, 519), // components/plonk.h:230 +PolyExtStep::Mul(8800, 698), // components/plonk.h:230 +PolyExtStep::Mul(8800, 703), // components/plonk.h:230 +PolyExtStep::Mul(8800, 708), // components/plonk.h:230 +PolyExtStep::Mul(8800, 320), // components/plonk.h:230 +PolyExtStep::Mul(8800, 899), // components/plonk.h:230 +PolyExtStep::Mul(8800, 918), // components/plonk.h:230 +PolyExtStep::Mul(8800, 944), // components/plonk.h:230 +PolyExtStep::Mul(8800, 963), // components/plonk.h:230 +PolyExtStep::Mul(8800, 989), // components/plonk.h:230 +PolyExtStep::Mul(8800, 1008), // components/plonk.h:230 +PolyExtStep::Mul(8800, 1034), // components/plonk.h:230 +PolyExtStep::Mul(8800, 1053), // components/plonk.h:230 +PolyExtStep::Mul(8801, 8704), // components/plonk.h:230 +PolyExtStep::Mul(8801, 325), // components/plonk.h:230 +PolyExtStep::Mul(8801, 330), // components/plonk.h:230 +PolyExtStep::Mul(8801, 509), // components/plonk.h:230 +PolyExtStep::Mul(8801, 514), // components/plonk.h:230 +PolyExtStep::Mul(8801, 519), // components/plonk.h:230 +PolyExtStep::Mul(8801, 698), // components/plonk.h:230 +PolyExtStep::Mul(8801, 703), // components/plonk.h:230 +PolyExtStep::Mul(8801, 708), // components/plonk.h:230 +PolyExtStep::Mul(8801, 320), // components/plonk.h:230 +PolyExtStep::Mul(8801, 899), // components/plonk.h:230 +PolyExtStep::Mul(8801, 918), // components/plonk.h:230 +PolyExtStep::Mul(8801, 944), // components/plonk.h:230 +PolyExtStep::Mul(8801, 963), // components/plonk.h:230 +PolyExtStep::Mul(8801, 989), // components/plonk.h:230 +PolyExtStep::Mul(8801, 1008), // components/plonk.h:230 +PolyExtStep::Mul(8801, 1034), // components/plonk.h:230 +PolyExtStep::Mul(8801, 1053), // components/plonk.h:230 +PolyExtStep::Mul(8802, 327), // components/plonk.h:230 +PolyExtStep::Mul(8802, 334), // components/plonk.h:230 +PolyExtStep::Mul(8802, 8710), // components/plonk.h:230 +PolyExtStep::Mul(8802, 511), // components/plonk.h:230 +PolyExtStep::Mul(8802, 516), // components/plonk.h:230 +PolyExtStep::Mul(8802, 523), // components/plonk.h:230 +PolyExtStep::Mul(8802, 700), // components/plonk.h:230 +PolyExtStep::Mul(8802, 705), // components/plonk.h:230 +PolyExtStep::Mul(8802, 712), // components/plonk.h:230 +PolyExtStep::Mul(8802, 908), // components/plonk.h:230 +PolyExtStep::Mul(8802, 927), // components/plonk.h:230 +PolyExtStep::Mul(8802, 953), // components/plonk.h:230 +PolyExtStep::Mul(8802, 972), // components/plonk.h:230 +PolyExtStep::Mul(8802, 322), // components/plonk.h:230 +PolyExtStep::Mul(8802, 998), // components/plonk.h:230 +PolyExtStep::Mul(8802, 1017), // components/plonk.h:230 +PolyExtStep::Mul(8802, 1043), // components/plonk.h:230 +PolyExtStep::Mul(8802, 1062), // components/plonk.h:230 +PolyExtStep::Mul(8803, 327), // components/plonk.h:230 +PolyExtStep::Mul(8803, 334), // components/plonk.h:230 +PolyExtStep::Mul(8803, 8710), // components/plonk.h:230 +PolyExtStep::Mul(8803, 511), // components/plonk.h:230 +PolyExtStep::Mul(8803, 516), // components/plonk.h:230 +PolyExtStep::Mul(8803, 523), // components/plonk.h:230 +PolyExtStep::Mul(8803, 700), // components/plonk.h:230 +PolyExtStep::Mul(8803, 705), // components/plonk.h:230 +PolyExtStep::Mul(8803, 712), // components/plonk.h:230 +PolyExtStep::Mul(8803, 908), // components/plonk.h:230 +PolyExtStep::Mul(8803, 927), // components/plonk.h:230 +PolyExtStep::Mul(8803, 953), // components/plonk.h:230 +PolyExtStep::Mul(8803, 972), // components/plonk.h:230 +PolyExtStep::Mul(8803, 322), // components/plonk.h:230 +PolyExtStep::Mul(8803, 998), // components/plonk.h:230 +PolyExtStep::Mul(8803, 1017), // components/plonk.h:230 +PolyExtStep::Mul(8803, 1043), // components/plonk.h:230 +PolyExtStep::Mul(8803, 1062), // components/plonk.h:230 +PolyExtStep::Mul(8805, 328), // components/plonk.h:230 +PolyExtStep::Mul(8805, 336), // components/plonk.h:230 +PolyExtStep::Mul(8805, 512), // components/plonk.h:230 +PolyExtStep::Mul(8805, 517), // components/plonk.h:230 +PolyExtStep::Mul(8805, 8712), // components/plonk.h:230 +PolyExtStep::Mul(8805, 525), // components/plonk.h:230 +PolyExtStep::Mul(8805, 701), // components/plonk.h:230 +PolyExtStep::Mul(8805, 706), // components/plonk.h:230 +PolyExtStep::Mul(8805, 714), // components/plonk.h:230 +PolyExtStep::Mul(8805, 909), // components/plonk.h:230 +PolyExtStep::Mul(8805, 935), // components/plonk.h:230 +PolyExtStep::Mul(8805, 954), // components/plonk.h:230 +PolyExtStep::Mul(8805, 980), // components/plonk.h:230 +PolyExtStep::Mul(8805, 999), // components/plonk.h:230 +PolyExtStep::Mul(8805, 1025), // components/plonk.h:230 +PolyExtStep::Mul(8805, 323), // components/plonk.h:230 +PolyExtStep::Mul(8805, 1044), // components/plonk.h:230 +PolyExtStep::Mul(8805, 1070), // components/plonk.h:230 +PolyExtStep::Mul(8806, 328), // components/plonk.h:230 +PolyExtStep::Mul(8806, 336), // components/plonk.h:230 +PolyExtStep::Mul(8806, 512), // components/plonk.h:230 +PolyExtStep::Mul(8806, 517), // components/plonk.h:230 +PolyExtStep::Mul(8806, 8712), // components/plonk.h:230 +PolyExtStep::Mul(8806, 525), // components/plonk.h:230 +PolyExtStep::Mul(8806, 701), // components/plonk.h:230 +PolyExtStep::Mul(8806, 706), // components/plonk.h:230 +PolyExtStep::Mul(8806, 714), // components/plonk.h:230 +PolyExtStep::Mul(8806, 909), // components/plonk.h:230 +PolyExtStep::Mul(8806, 935), // components/plonk.h:230 +PolyExtStep::Mul(8806, 954), // components/plonk.h:230 +PolyExtStep::Mul(8806, 980), // components/plonk.h:230 +PolyExtStep::Mul(8806, 999), // components/plonk.h:230 +PolyExtStep::Mul(8806, 1025), // components/plonk.h:230 +PolyExtStep::Mul(8806, 323), // components/plonk.h:230 +PolyExtStep::Mul(8806, 1044), // components/plonk.h:230 +PolyExtStep::Mul(8806, 1070), // components/plonk.h:230 +PolyExtStep::Mul(8807, 328), // components/plonk.h:230 +PolyExtStep::Mul(8807, 336), // components/plonk.h:230 +PolyExtStep::Mul(8807, 512), // components/plonk.h:230 +PolyExtStep::Mul(8807, 517), // components/plonk.h:230 +PolyExtStep::Mul(8807, 8712), // components/plonk.h:230 +PolyExtStep::Mul(8807, 525), // components/plonk.h:230 +PolyExtStep::Mul(8807, 701), // components/plonk.h:230 +PolyExtStep::Mul(8807, 706), // components/plonk.h:230 +PolyExtStep::Mul(8807, 714), // components/plonk.h:230 +PolyExtStep::Mul(8807, 909), // components/plonk.h:230 +PolyExtStep::Mul(8807, 935), // components/plonk.h:230 +PolyExtStep::Mul(8807, 954), // components/plonk.h:230 +PolyExtStep::Mul(8807, 980), // components/plonk.h:230 +PolyExtStep::Mul(8807, 999), // components/plonk.h:230 +PolyExtStep::Mul(8807, 1025), // components/plonk.h:230 +PolyExtStep::Mul(8807, 323), // components/plonk.h:230 +PolyExtStep::Mul(8807, 1044), // components/plonk.h:230 +PolyExtStep::Mul(8807, 1070), // components/plonk.h:230 +PolyExtStep::Mul(8809, 329), // components/plonk.h:230 +PolyExtStep::Mul(8809, 338), // components/plonk.h:230 +PolyExtStep::Mul(8809, 513), // components/plonk.h:230 +PolyExtStep::Mul(8809, 518), // components/plonk.h:230 +PolyExtStep::Mul(8809, 527), // components/plonk.h:230 +PolyExtStep::Mul(8809, 702), // components/plonk.h:230 +PolyExtStep::Mul(8809, 8714), // components/plonk.h:230 +PolyExtStep::Mul(8809, 707), // components/plonk.h:230 +PolyExtStep::Mul(8809, 716), // components/plonk.h:230 +PolyExtStep::Mul(8809, 917), // components/plonk.h:230 +PolyExtStep::Mul(8809, 936), // components/plonk.h:230 +PolyExtStep::Mul(8809, 962), // components/plonk.h:230 +PolyExtStep::Mul(8809, 981), // components/plonk.h:230 +PolyExtStep::Mul(8809, 1007), // components/plonk.h:230 +PolyExtStep::Mul(8809, 1026), // components/plonk.h:230 +PolyExtStep::Mul(8809, 1052), // components/plonk.h:230 +PolyExtStep::Mul(8809, 1071), // components/plonk.h:230 +PolyExtStep::Mul(8809, 324), // components/plonk.h:230 +PolyExtStep::Mul(8810, 329), // components/plonk.h:230 +PolyExtStep::Mul(8810, 338), // components/plonk.h:230 +PolyExtStep::Mul(8810, 513), // components/plonk.h:230 +PolyExtStep::Mul(8810, 518), // components/plonk.h:230 +PolyExtStep::Mul(8810, 527), // components/plonk.h:230 +PolyExtStep::Mul(8810, 702), // components/plonk.h:230 +PolyExtStep::Mul(8810, 8714), // components/plonk.h:230 +PolyExtStep::Mul(8810, 707), // components/plonk.h:230 +PolyExtStep::Mul(8810, 716), // components/plonk.h:230 +PolyExtStep::Mul(8810, 917), // components/plonk.h:230 +PolyExtStep::Mul(8810, 936), // components/plonk.h:230 +PolyExtStep::Mul(8810, 962), // components/plonk.h:230 +PolyExtStep::Mul(8810, 981), // components/plonk.h:230 +PolyExtStep::Mul(8810, 1007), // components/plonk.h:230 +PolyExtStep::Mul(8810, 1026), // components/plonk.h:230 +PolyExtStep::Mul(8810, 1052), // components/plonk.h:230 +PolyExtStep::Mul(8810, 1071), // components/plonk.h:230 +PolyExtStep::Mul(8810, 324), // components/plonk.h:230 +PolyExtStep::Mul(8811, 329), // components/plonk.h:230 +PolyExtStep::Mul(8811, 338), // components/plonk.h:230 +PolyExtStep::Mul(8811, 513), // components/plonk.h:230 +PolyExtStep::Mul(8811, 518), // components/plonk.h:230 +PolyExtStep::Mul(8811, 527), // components/plonk.h:230 +PolyExtStep::Mul(8811, 702), // components/plonk.h:230 +PolyExtStep::Mul(8811, 8714), // components/plonk.h:230 +PolyExtStep::Mul(8811, 707), // components/plonk.h:230 +PolyExtStep::Mul(8811, 716), // components/plonk.h:230 +PolyExtStep::Mul(8811, 917), // components/plonk.h:230 +PolyExtStep::Mul(8811, 936), // components/plonk.h:230 +PolyExtStep::Mul(8811, 962), // components/plonk.h:230 +PolyExtStep::Mul(8811, 981), // components/plonk.h:230 +PolyExtStep::Mul(8811, 1007), // components/plonk.h:230 +PolyExtStep::Mul(8811, 1026), // components/plonk.h:230 +PolyExtStep::Mul(8811, 1052), // components/plonk.h:230 +PolyExtStep::Mul(8811, 1071), // components/plonk.h:230 +PolyExtStep::Mul(8811, 324), // components/plonk.h:230 +PolyExtStep::Mul(8812, 8704), // components/plonk.h:230 +PolyExtStep::Mul(8812, 325), // components/plonk.h:230 +PolyExtStep::Mul(8812, 330), // components/plonk.h:230 +PolyExtStep::Mul(8812, 509), // components/plonk.h:230 +PolyExtStep::Mul(8812, 514), // components/plonk.h:230 +PolyExtStep::Mul(8812, 519), // components/plonk.h:230 +PolyExtStep::Mul(8812, 698), // components/plonk.h:230 +PolyExtStep::Mul(8812, 703), // components/plonk.h:230 +PolyExtStep::Mul(8812, 708), // components/plonk.h:230 +PolyExtStep::Mul(8812, 320), // components/plonk.h:230 +PolyExtStep::Mul(8812, 899), // components/plonk.h:230 +PolyExtStep::Mul(8812, 918), // components/plonk.h:230 +PolyExtStep::Mul(8812, 944), // components/plonk.h:230 +PolyExtStep::Mul(8812, 963), // components/plonk.h:230 +PolyExtStep::Mul(8812, 989), // components/plonk.h:230 +PolyExtStep::Mul(8812, 1008), // components/plonk.h:230 +PolyExtStep::Mul(8812, 1034), // components/plonk.h:230 +PolyExtStep::Mul(8812, 1053), // components/plonk.h:230 +PolyExtStep::Mul(8813, 8704), // components/plonk.h:230 +PolyExtStep::Mul(8813, 325), // components/plonk.h:230 +PolyExtStep::Mul(8813, 330), // components/plonk.h:230 +PolyExtStep::Mul(8813, 509), // components/plonk.h:230 +PolyExtStep::Mul(8813, 514), // components/plonk.h:230 +PolyExtStep::Mul(8813, 519), // components/plonk.h:230 +PolyExtStep::Mul(8813, 698), // components/plonk.h:230 +PolyExtStep::Mul(8813, 703), // components/plonk.h:230 +PolyExtStep::Mul(8813, 708), // components/plonk.h:230 +PolyExtStep::Mul(8813, 320), // components/plonk.h:230 +PolyExtStep::Mul(8813, 899), // components/plonk.h:230 +PolyExtStep::Mul(8813, 918), // components/plonk.h:230 +PolyExtStep::Mul(8813, 944), // components/plonk.h:230 +PolyExtStep::Mul(8813, 963), // components/plonk.h:230 +PolyExtStep::Mul(8813, 989), // components/plonk.h:230 +PolyExtStep::Mul(8813, 1008), // components/plonk.h:230 +PolyExtStep::Mul(8813, 1034), // components/plonk.h:230 +PolyExtStep::Mul(8813, 1053), // components/plonk.h:230 +PolyExtStep::Mul(8815, 8708), // components/plonk.h:230 +PolyExtStep::Mul(8815, 326), // components/plonk.h:230 +PolyExtStep::Mul(8815, 332), // components/plonk.h:230 +PolyExtStep::Mul(8815, 510), // components/plonk.h:230 +PolyExtStep::Mul(8815, 515), // components/plonk.h:230 +PolyExtStep::Mul(8815, 521), // components/plonk.h:230 +PolyExtStep::Mul(8815, 699), // components/plonk.h:230 +PolyExtStep::Mul(8815, 704), // components/plonk.h:230 +PolyExtStep::Mul(8815, 710), // components/plonk.h:230 +PolyExtStep::Mul(8815, 900), // components/plonk.h:230 +PolyExtStep::Mul(8815, 926), // components/plonk.h:230 +PolyExtStep::Mul(8815, 321), // components/plonk.h:230 +PolyExtStep::Mul(8815, 945), // components/plonk.h:230 +PolyExtStep::Mul(8815, 971), // components/plonk.h:230 +PolyExtStep::Mul(8815, 990), // components/plonk.h:230 +PolyExtStep::Mul(8815, 1016), // components/plonk.h:230 +PolyExtStep::Mul(8815, 1035), // components/plonk.h:230 +PolyExtStep::Mul(8815, 1061), // components/plonk.h:230 +PolyExtStep::Mul(8816, 8708), // components/plonk.h:230 +PolyExtStep::Mul(8816, 326), // components/plonk.h:230 +PolyExtStep::Mul(8816, 332), // components/plonk.h:230 +PolyExtStep::Mul(8816, 510), // components/plonk.h:230 +PolyExtStep::Mul(8816, 515), // components/plonk.h:230 +PolyExtStep::Mul(8816, 521), // components/plonk.h:230 +PolyExtStep::Mul(8816, 699), // components/plonk.h:230 +PolyExtStep::Mul(8816, 704), // components/plonk.h:230 +PolyExtStep::Mul(8816, 710), // components/plonk.h:230 +PolyExtStep::Mul(8816, 900), // components/plonk.h:230 +PolyExtStep::Mul(8816, 926), // components/plonk.h:230 +PolyExtStep::Mul(8816, 321), // components/plonk.h:230 +PolyExtStep::Mul(8816, 945), // components/plonk.h:230 +PolyExtStep::Mul(8816, 971), // components/plonk.h:230 +PolyExtStep::Mul(8816, 990), // components/plonk.h:230 +PolyExtStep::Mul(8816, 1016), // components/plonk.h:230 +PolyExtStep::Mul(8816, 1035), // components/plonk.h:230 +PolyExtStep::Mul(8816, 1061), // components/plonk.h:230 +PolyExtStep::Mul(8817, 8708), // components/plonk.h:230 +PolyExtStep::Mul(8817, 326), // components/plonk.h:230 +PolyExtStep::Mul(8817, 332), // components/plonk.h:230 +PolyExtStep::Mul(8817, 510), // components/plonk.h:230 +PolyExtStep::Mul(8817, 515), // components/plonk.h:230 +PolyExtStep::Mul(8817, 521), // components/plonk.h:230 +PolyExtStep::Mul(8817, 699), // components/plonk.h:230 +PolyExtStep::Mul(8817, 704), // components/plonk.h:230 +PolyExtStep::Mul(8817, 710), // components/plonk.h:230 +PolyExtStep::Mul(8817, 900), // components/plonk.h:230 +PolyExtStep::Mul(8817, 926), // components/plonk.h:230 +PolyExtStep::Mul(8817, 321), // components/plonk.h:230 +PolyExtStep::Mul(8817, 945), // components/plonk.h:230 +PolyExtStep::Mul(8817, 971), // components/plonk.h:230 +PolyExtStep::Mul(8817, 990), // components/plonk.h:230 +PolyExtStep::Mul(8817, 1016), // components/plonk.h:230 +PolyExtStep::Mul(8817, 1035), // components/plonk.h:230 +PolyExtStep::Mul(8817, 1061), // components/plonk.h:230 +PolyExtStep::Mul(8819, 327), // components/plonk.h:230 +PolyExtStep::Mul(8819, 334), // components/plonk.h:230 +PolyExtStep::Mul(8819, 8710), // components/plonk.h:230 +PolyExtStep::Mul(8819, 511), // components/plonk.h:230 +PolyExtStep::Mul(8819, 516), // components/plonk.h:230 +PolyExtStep::Mul(8819, 523), // components/plonk.h:230 +PolyExtStep::Mul(8819, 700), // components/plonk.h:230 +PolyExtStep::Mul(8819, 705), // components/plonk.h:230 +PolyExtStep::Mul(8819, 712), // components/plonk.h:230 +PolyExtStep::Mul(8819, 908), // components/plonk.h:230 +PolyExtStep::Mul(8819, 927), // components/plonk.h:230 +PolyExtStep::Mul(8819, 953), // components/plonk.h:230 +PolyExtStep::Mul(8819, 972), // components/plonk.h:230 +PolyExtStep::Mul(8819, 322), // components/plonk.h:230 +PolyExtStep::Mul(8819, 998), // components/plonk.h:230 +PolyExtStep::Mul(8819, 1017), // components/plonk.h:230 +PolyExtStep::Mul(8819, 1043), // components/plonk.h:230 +PolyExtStep::Mul(8819, 1062), // components/plonk.h:230 +PolyExtStep::Mul(8804, 328), // components/plonk.h:230 +PolyExtStep::Mul(8804, 336), // components/plonk.h:230 +PolyExtStep::Mul(8804, 512), // components/plonk.h:230 +PolyExtStep::Mul(8804, 517), // components/plonk.h:230 +PolyExtStep::Mul(8804, 8712), // components/plonk.h:230 +PolyExtStep::Mul(8804, 525), // components/plonk.h:230 +PolyExtStep::Mul(8804, 701), // components/plonk.h:230 +PolyExtStep::Mul(8804, 706), // components/plonk.h:230 +PolyExtStep::Mul(8804, 714), // components/plonk.h:230 +PolyExtStep::Mul(8804, 909), // components/plonk.h:230 +PolyExtStep::Mul(8804, 935), // components/plonk.h:230 +PolyExtStep::Mul(8804, 954), // components/plonk.h:230 +PolyExtStep::Mul(8804, 980), // components/plonk.h:230 +PolyExtStep::Mul(8804, 999), // components/plonk.h:230 +PolyExtStep::Mul(8804, 1025), // components/plonk.h:230 +PolyExtStep::Mul(8804, 323), // components/plonk.h:230 +PolyExtStep::Mul(8804, 1044), // components/plonk.h:230 +PolyExtStep::Mul(8804, 1070), // components/plonk.h:230 +PolyExtStep::Mul(8808, 329), // components/plonk.h:230 +PolyExtStep::Mul(8808, 338), // components/plonk.h:230 +PolyExtStep::Mul(8808, 513), // components/plonk.h:230 +PolyExtStep::Mul(8808, 518), // components/plonk.h:230 +PolyExtStep::Mul(8808, 527), // components/plonk.h:230 +PolyExtStep::Mul(8808, 702), // components/plonk.h:230 +PolyExtStep::Mul(8808, 8714), // components/plonk.h:230 +PolyExtStep::Mul(8808, 707), // components/plonk.h:230 +PolyExtStep::Mul(8808, 716), // components/plonk.h:230 +PolyExtStep::Mul(8808, 917), // components/plonk.h:230 +PolyExtStep::Mul(8808, 936), // components/plonk.h:230 +PolyExtStep::Mul(8808, 962), // components/plonk.h:230 +PolyExtStep::Mul(8808, 981), // components/plonk.h:230 +PolyExtStep::Mul(8808, 1007), // components/plonk.h:230 +PolyExtStep::Mul(8808, 1026), // components/plonk.h:230 +PolyExtStep::Mul(8808, 1052), // components/plonk.h:230 +PolyExtStep::Mul(8808, 1071), // components/plonk.h:230 +PolyExtStep::Mul(8808, 324), // components/plonk.h:230 +PolyExtStep::Mul(8814, 8708), // components/plonk.h:230 +PolyExtStep::Mul(8814, 326), // components/plonk.h:230 +PolyExtStep::Mul(8814, 332), // components/plonk.h:230 +PolyExtStep::Mul(8814, 510), // components/plonk.h:230 +PolyExtStep::Mul(8814, 515), // components/plonk.h:230 +PolyExtStep::Mul(8814, 521), // components/plonk.h:230 +PolyExtStep::Mul(8814, 699), // components/plonk.h:230 +PolyExtStep::Mul(8814, 704), // components/plonk.h:230 +PolyExtStep::Mul(8814, 710), // components/plonk.h:230 +PolyExtStep::Mul(8814, 900), // components/plonk.h:230 +PolyExtStep::Mul(8814, 926), // components/plonk.h:230 +PolyExtStep::Mul(8814, 321), // components/plonk.h:230 +PolyExtStep::Mul(8814, 945), // components/plonk.h:230 +PolyExtStep::Mul(8814, 971), // components/plonk.h:230 +PolyExtStep::Mul(8814, 990), // components/plonk.h:230 +PolyExtStep::Mul(8814, 1016), // components/plonk.h:230 +PolyExtStep::Mul(8814, 1035), // components/plonk.h:230 +PolyExtStep::Mul(8814, 1061), // components/plonk.h:230 +PolyExtStep::Mul(8818, 327), // components/plonk.h:230 +PolyExtStep::Mul(8818, 334), // components/plonk.h:230 +PolyExtStep::Mul(8818, 8710), // components/plonk.h:230 +PolyExtStep::Mul(8818, 511), // components/plonk.h:230 +PolyExtStep::Mul(8818, 516), // components/plonk.h:230 +PolyExtStep::Mul(8818, 523), // components/plonk.h:230 +PolyExtStep::Mul(8818, 700), // components/plonk.h:230 +PolyExtStep::Mul(8818, 705), // components/plonk.h:230 +PolyExtStep::Mul(8818, 712), // components/plonk.h:230 +PolyExtStep::Mul(8818, 908), // components/plonk.h:230 +PolyExtStep::Mul(8818, 927), // components/plonk.h:230 +PolyExtStep::Mul(8818, 953), // components/plonk.h:230 +PolyExtStep::Mul(8818, 972), // components/plonk.h:230 +PolyExtStep::Mul(8818, 322), // components/plonk.h:230 +PolyExtStep::Mul(8818, 998), // components/plonk.h:230 +PolyExtStep::Mul(8818, 1017), // components/plonk.h:230 +PolyExtStep::Mul(8818, 1043), // components/plonk.h:230 +PolyExtStep::Mul(8818, 1062), // components/plonk.h:230 +PolyExtStep::Add(8820, 1), // components/plonk.h:230 +PolyExtStep::Add(8821, 1), // components/plonk.h:230 +PolyExtStep::Add(8822, 1), // components/plonk.h:230 +PolyExtStep::Add(8823, 1), // components/plonk.h:230 +PolyExtStep::Add(8824, 1), // components/plonk.h:230 +PolyExtStep::Add(8825, 1), // components/plonk.h:230 +PolyExtStep::Add(8826, 1), // components/plonk.h:230 +PolyExtStep::Add(8827, 1), // components/plonk.h:230 +PolyExtStep::Add(8828, 1), // components/plonk.h:230 +PolyExtStep::Add(8829, 1), // components/plonk.h:230 +PolyExtStep::Add(8830, 1), // components/plonk.h:230 +PolyExtStep::Add(8831, 1), // components/plonk.h:230 +PolyExtStep::Add(8832, 1), // components/plonk.h:230 +PolyExtStep::Add(8833, 1), // components/plonk.h:230 +PolyExtStep::Add(8834, 1), // components/plonk.h:230 +PolyExtStep::Add(8835, 1), // components/plonk.h:230 +PolyExtStep::Add(8836, 1), // components/plonk.h:230 +PolyExtStep::Add(8837, 1), // components/plonk.h:230 +PolyExtStep::Add(9180, 9144), // components/plonk.h:230 +PolyExtStep::Add(9181, 9145), // components/plonk.h:230 +PolyExtStep::Add(9182, 9146), // components/plonk.h:230 +PolyExtStep::Add(9183, 9147), // components/plonk.h:230 +PolyExtStep::Add(9184, 9148), // components/plonk.h:230 +PolyExtStep::Add(9185, 9149), // components/plonk.h:230 +PolyExtStep::Add(9186, 9150), // components/plonk.h:230 +PolyExtStep::Add(9187, 9151), // components/plonk.h:230 +PolyExtStep::Add(9188, 9152), // components/plonk.h:230 +PolyExtStep::Add(9189, 9155), // components/plonk.h:230 +PolyExtStep::Add(9190, 9153), // components/plonk.h:230 +PolyExtStep::Add(9191, 9154), // components/plonk.h:230 +PolyExtStep::Add(9192, 9156), // components/plonk.h:230 +PolyExtStep::Add(9193, 9157), // components/plonk.h:230 +PolyExtStep::Add(9194, 9158), // components/plonk.h:230 +PolyExtStep::Add(9195, 9159), // components/plonk.h:230 +PolyExtStep::Add(9196, 9160), // components/plonk.h:230 +PolyExtStep::Add(9197, 9161), // components/plonk.h:230 +PolyExtStep::Add(9198, 9164), // components/plonk.h:230 +PolyExtStep::Add(9199, 9162), // components/plonk.h:230 +PolyExtStep::Add(9200, 9163), // components/plonk.h:230 +PolyExtStep::Add(9201, 9165), // components/plonk.h:230 +PolyExtStep::Add(9202, 9166), // components/plonk.h:230 +PolyExtStep::Add(9203, 9167), // components/plonk.h:230 +PolyExtStep::Add(9204, 9168), // components/plonk.h:230 +PolyExtStep::Add(9205, 9169), // components/plonk.h:230 +PolyExtStep::Add(9206, 9170), // components/plonk.h:230 +PolyExtStep::Add(9207, 9175), // components/plonk.h:230 +PolyExtStep::Add(9208, 9171), // components/plonk.h:230 +PolyExtStep::Add(9209, 9172), // components/plonk.h:230 +PolyExtStep::Add(9210, 9173), // components/plonk.h:230 +PolyExtStep::Add(9211, 9174), // components/plonk.h:230 +PolyExtStep::Add(9212, 9176), // components/plonk.h:230 +PolyExtStep::Add(9213, 9177), // components/plonk.h:230 +PolyExtStep::Add(9214, 9178), // components/plonk.h:230 +PolyExtStep::Add(9215, 9179), // components/plonk.h:230 +PolyExtStep::Add(8838, 9036), // components/plonk.h:230 +PolyExtStep::Add(8839, 9037), // components/plonk.h:230 +PolyExtStep::Add(8840, 9038), // components/plonk.h:230 +PolyExtStep::Add(8841, 9039), // components/plonk.h:230 +PolyExtStep::Add(8842, 9040), // components/plonk.h:230 +PolyExtStep::Add(8843, 9041), // components/plonk.h:230 +PolyExtStep::Add(8844, 9042), // components/plonk.h:230 +PolyExtStep::Add(8845, 9043), // components/plonk.h:230 +PolyExtStep::Add(8846, 9044), // components/plonk.h:230 +PolyExtStep::Add(8847, 9047), // components/plonk.h:230 +PolyExtStep::Add(8848, 9045), // components/plonk.h:230 +PolyExtStep::Add(8849, 9046), // components/plonk.h:230 +PolyExtStep::Add(8850, 9048), // components/plonk.h:230 +PolyExtStep::Add(8851, 9049), // components/plonk.h:230 +PolyExtStep::Add(8852, 9050), // components/plonk.h:230 +PolyExtStep::Add(8853, 9051), // components/plonk.h:230 +PolyExtStep::Add(8854, 9052), // components/plonk.h:230 +PolyExtStep::Add(8855, 9053), // components/plonk.h:230 +PolyExtStep::Add(9000, 9054), // components/plonk.h:230 +PolyExtStep::Add(9001, 9055), // components/plonk.h:230 +PolyExtStep::Add(9002, 9056), // components/plonk.h:230 +PolyExtStep::Add(9003, 9057), // components/plonk.h:230 +PolyExtStep::Add(9004, 9058), // components/plonk.h:230 +PolyExtStep::Add(9005, 9059), // components/plonk.h:230 +PolyExtStep::Add(9006, 9060), // components/plonk.h:230 +PolyExtStep::Add(9007, 9061), // components/plonk.h:230 +PolyExtStep::Add(9008, 9062), // components/plonk.h:230 +PolyExtStep::Add(9009, 9065), // components/plonk.h:230 +PolyExtStep::Add(9010, 9063), // components/plonk.h:230 +PolyExtStep::Add(9011, 9064), // components/plonk.h:230 +PolyExtStep::Add(9012, 9066), // components/plonk.h:230 +PolyExtStep::Add(9013, 9067), // components/plonk.h:230 +PolyExtStep::Add(9014, 9068), // components/plonk.h:230 +PolyExtStep::Add(9015, 9069), // components/plonk.h:230 +PolyExtStep::Add(9016, 9070), // components/plonk.h:230 +PolyExtStep::Add(9017, 9071), // components/plonk.h:230 +PolyExtStep::Add(9018, 9072), // components/plonk.h:230 +PolyExtStep::Add(9019, 9073), // components/plonk.h:230 +PolyExtStep::Add(9020, 9074), // components/plonk.h:230 +PolyExtStep::Add(9021, 9075), // components/plonk.h:230 +PolyExtStep::Add(9022, 9076), // components/plonk.h:230 +PolyExtStep::Add(9023, 9077), // components/plonk.h:230 +PolyExtStep::Add(9024, 9078), // components/plonk.h:230 +PolyExtStep::Add(9025, 9079), // components/plonk.h:230 +PolyExtStep::Add(9026, 9080), // components/plonk.h:230 +PolyExtStep::Add(9027, 9083), // components/plonk.h:230 +PolyExtStep::Add(9028, 9081), // components/plonk.h:230 +PolyExtStep::Add(9029, 9082), // components/plonk.h:230 +PolyExtStep::Add(9030, 9084), // components/plonk.h:230 +PolyExtStep::Add(9031, 9085), // components/plonk.h:230 +PolyExtStep::Add(9032, 9086), // components/plonk.h:230 +PolyExtStep::Add(9033, 9087), // components/plonk.h:230 +PolyExtStep::Add(9034, 9088), // components/plonk.h:230 +PolyExtStep::Add(9035, 9089), // components/plonk.h:230 +PolyExtStep::Add(9216, 9112), // components/plonk.h:230 +PolyExtStep::Add(9217, 9108), // components/plonk.h:230 +PolyExtStep::Add(9218, 9109), // components/plonk.h:230 +PolyExtStep::Add(9219, 9110), // components/plonk.h:230 +PolyExtStep::Add(9220, 9111), // components/plonk.h:230 +PolyExtStep::Add(9221, 9113), // components/plonk.h:230 +PolyExtStep::Add(9222, 9114), // components/plonk.h:230 +PolyExtStep::Add(9223, 9115), // components/plonk.h:230 +PolyExtStep::Add(9224, 9116), // components/plonk.h:230 +PolyExtStep::Add(9225, 9123), // components/plonk.h:230 +PolyExtStep::Add(9226, 9117), // components/plonk.h:230 +PolyExtStep::Add(9227, 9118), // components/plonk.h:230 +PolyExtStep::Add(9228, 9119), // components/plonk.h:230 +PolyExtStep::Add(9229, 9120), // components/plonk.h:230 +PolyExtStep::Add(9230, 9121), // components/plonk.h:230 +PolyExtStep::Add(9231, 9122), // components/plonk.h:230 +PolyExtStep::Add(9232, 9124), // components/plonk.h:230 +PolyExtStep::Add(9233, 9125), // components/plonk.h:230 +PolyExtStep::Add(9234, 9092), // components/plonk.h:230 +PolyExtStep::Add(9235, 9090), // components/plonk.h:230 +PolyExtStep::Add(9236, 9091), // components/plonk.h:230 +PolyExtStep::Add(9237, 9093), // components/plonk.h:230 +PolyExtStep::Add(9238, 9094), // components/plonk.h:230 +PolyExtStep::Add(9239, 9095), // components/plonk.h:230 +PolyExtStep::Add(9240, 9096), // components/plonk.h:230 +PolyExtStep::Add(9241, 9097), // components/plonk.h:230 +PolyExtStep::Add(9242, 9098), // components/plonk.h:230 +PolyExtStep::Add(9243, 9103), // components/plonk.h:230 +PolyExtStep::Add(9244, 9099), // components/plonk.h:230 +PolyExtStep::Add(9245, 9100), // components/plonk.h:230 +PolyExtStep::Add(9246, 9101), // components/plonk.h:230 +PolyExtStep::Add(9247, 9102), // components/plonk.h:230 +PolyExtStep::Add(9248, 9104), // components/plonk.h:230 +PolyExtStep::Add(9249, 9105), // components/plonk.h:230 +PolyExtStep::Add(9250, 9106), // components/plonk.h:230 +PolyExtStep::Add(9251, 9107), // components/plonk.h:230 +PolyExtStep::Add(9252, 8858), // components/plonk.h:230 +PolyExtStep::Add(9253, 8856), // components/plonk.h:230 +PolyExtStep::Add(9254, 8857), // components/plonk.h:230 +PolyExtStep::Add(9255, 8859), // components/plonk.h:230 +PolyExtStep::Add(9256, 8860), // components/plonk.h:230 +PolyExtStep::Add(9257, 8861), // components/plonk.h:230 +PolyExtStep::Add(9258, 8862), // components/plonk.h:230 +PolyExtStep::Add(9259, 8863), // components/plonk.h:230 +PolyExtStep::Add(9260, 8864), // components/plonk.h:230 +PolyExtStep::Add(9261, 8869), // components/plonk.h:230 +PolyExtStep::Add(9262, 8865), // components/plonk.h:230 +PolyExtStep::Add(9263, 8866), // components/plonk.h:230 +PolyExtStep::Add(9264, 8867), // components/plonk.h:230 +PolyExtStep::Add(9265, 8868), // components/plonk.h:230 +PolyExtStep::Add(9266, 8870), // components/plonk.h:230 +PolyExtStep::Add(9267, 8871), // components/plonk.h:230 +PolyExtStep::Add(9268, 8872), // components/plonk.h:230 +PolyExtStep::Add(9269, 8873), // components/plonk.h:230 +PolyExtStep::Add(9270, 8876), // components/plonk.h:230 +PolyExtStep::Add(9271, 8874), // components/plonk.h:230 +PolyExtStep::Add(9272, 8875), // components/plonk.h:230 +PolyExtStep::Add(9273, 8877), // components/plonk.h:230 +PolyExtStep::Add(9274, 8878), // components/plonk.h:230 +PolyExtStep::Add(9275, 8879), // components/plonk.h:230 +PolyExtStep::Add(9276, 8880), // components/plonk.h:230 +PolyExtStep::Add(9277, 8881), // components/plonk.h:230 +PolyExtStep::Add(9278, 8882), // components/plonk.h:230 +PolyExtStep::Add(9279, 8887), // components/plonk.h:230 +PolyExtStep::Add(9280, 8883), // components/plonk.h:230 +PolyExtStep::Add(9281, 8884), // components/plonk.h:230 +PolyExtStep::Add(9282, 8885), // components/plonk.h:230 +PolyExtStep::Add(9283, 8886), // components/plonk.h:230 +PolyExtStep::Add(9284, 8888), // components/plonk.h:230 +PolyExtStep::Add(9285, 8889), // components/plonk.h:230 +PolyExtStep::Add(9286, 8890), // components/plonk.h:230 +PolyExtStep::Add(9287, 8891), // components/plonk.h:230 +PolyExtStep::Add(9288, 9132), // components/plonk.h:230 +PolyExtStep::Add(9289, 9126), // components/plonk.h:230 +PolyExtStep::Add(9290, 9127), // components/plonk.h:230 +PolyExtStep::Add(9292, 9129), // components/plonk.h:230 +PolyExtStep::Add(9293, 9130), // components/plonk.h:230 +PolyExtStep::Add(9295, 9133), // components/plonk.h:230 +PolyExtStep::Add(9296, 9134), // components/plonk.h:230 +PolyExtStep::Add(9299, 9136), // components/plonk.h:230 +PolyExtStep::Add(9300, 9137), // components/plonk.h:230 +PolyExtStep::Add(9302, 9139), // components/plonk.h:230 +PolyExtStep::Add(9303, 9140), // components/plonk.h:230 +PolyExtStep::Add(9305, 9142), // components/plonk.h:230 +PolyExtStep::Add(9291, 9128), // components/plonk.h:230 +PolyExtStep::Add(9294, 9131), // components/plonk.h:230 +PolyExtStep::Add(9297, 9143), // components/plonk.h:230 +PolyExtStep::Add(9298, 9135), // components/plonk.h:230 +PolyExtStep::Add(9301, 9138), // components/plonk.h:230 +PolyExtStep::Add(9304, 9141), // components/plonk.h:230 +PolyExtStep::Add(9306, 8896), // components/plonk.h:230 +PolyExtStep::Add(9307, 8892), // components/plonk.h:230 +PolyExtStep::Add(9308, 8893), // components/plonk.h:230 +PolyExtStep::Add(9309, 8894), // components/plonk.h:230 +PolyExtStep::Add(9310, 8895), // components/plonk.h:230 +PolyExtStep::Add(9311, 8897), // components/plonk.h:230 +PolyExtStep::Add(9312, 8898), // components/plonk.h:230 +PolyExtStep::Add(9313, 8899), // components/plonk.h:230 +PolyExtStep::Add(9314, 8900), // components/plonk.h:230 +PolyExtStep::Add(9315, 8907), // components/plonk.h:230 +PolyExtStep::Add(9316, 8901), // components/plonk.h:230 +PolyExtStep::Add(9317, 8902), // components/plonk.h:230 +PolyExtStep::Add(9318, 8903), // components/plonk.h:230 +PolyExtStep::Add(9319, 8904), // components/plonk.h:230 +PolyExtStep::Add(9320, 8905), // components/plonk.h:230 +PolyExtStep::Add(9321, 8906), // components/plonk.h:230 +PolyExtStep::Add(9322, 8908), // components/plonk.h:230 +PolyExtStep::Add(9323, 8909), // components/plonk.h:230 +PolyExtStep::Add(9324, 8914), // components/plonk.h:230 +PolyExtStep::Add(9325, 8910), // components/plonk.h:230 +PolyExtStep::Add(9326, 8911), // components/plonk.h:230 +PolyExtStep::Add(9327, 8912), // components/plonk.h:230 +PolyExtStep::Add(9328, 8913), // components/plonk.h:230 +PolyExtStep::Add(9329, 8915), // components/plonk.h:230 +PolyExtStep::Add(9330, 8916), // components/plonk.h:230 +PolyExtStep::Add(9331, 8917), // components/plonk.h:230 +PolyExtStep::Add(9332, 8918), // components/plonk.h:230 +PolyExtStep::Add(9333, 8925), // components/plonk.h:230 +PolyExtStep::Add(9334, 8919), // components/plonk.h:230 +PolyExtStep::Add(9335, 8920), // components/plonk.h:230 +PolyExtStep::Add(9336, 8921), // components/plonk.h:230 +PolyExtStep::Add(9337, 8922), // components/plonk.h:230 +PolyExtStep::Add(9338, 8923), // components/plonk.h:230 +PolyExtStep::Add(9339, 8924), // components/plonk.h:230 +PolyExtStep::Add(9340, 8926), // components/plonk.h:230 +PolyExtStep::Add(9341, 8927), // components/plonk.h:230 +PolyExtStep::Add(9342, 8932), // components/plonk.h:230 +PolyExtStep::Add(9343, 8928), // components/plonk.h:230 +PolyExtStep::Add(9344, 8929), // components/plonk.h:230 +PolyExtStep::Add(9345, 8930), // components/plonk.h:230 +PolyExtStep::Add(9346, 8931), // components/plonk.h:230 +PolyExtStep::Add(9347, 8933), // components/plonk.h:230 +PolyExtStep::Add(9348, 8934), // components/plonk.h:230 +PolyExtStep::Add(9349, 8935), // components/plonk.h:230 +PolyExtStep::Add(9350, 8936), // components/plonk.h:230 +PolyExtStep::Add(9351, 8943), // components/plonk.h:230 +PolyExtStep::Add(9352, 8937), // components/plonk.h:230 +PolyExtStep::Add(9353, 8938), // components/plonk.h:230 +PolyExtStep::Add(9354, 8939), // components/plonk.h:230 +PolyExtStep::Add(9355, 8940), // components/plonk.h:230 +PolyExtStep::Add(9356, 8941), // components/plonk.h:230 +PolyExtStep::Add(9357, 8942), // components/plonk.h:230 +PolyExtStep::Add(9358, 8944), // components/plonk.h:230 +PolyExtStep::Add(9359, 8945), // components/plonk.h:230 +PolyExtStep::Add(9378, 8952), // components/plonk.h:230 +PolyExtStep::Add(9379, 8946), // components/plonk.h:230 +PolyExtStep::Add(9380, 8947), // components/plonk.h:230 +PolyExtStep::Add(9382, 8949), // components/plonk.h:230 +PolyExtStep::Add(9383, 8950), // components/plonk.h:230 +PolyExtStep::Add(9385, 8953), // components/plonk.h:230 +PolyExtStep::Add(9386, 8954), // components/plonk.h:230 +PolyExtStep::Add(9389, 8956), // components/plonk.h:230 +PolyExtStep::Add(9390, 8957), // components/plonk.h:230 +PolyExtStep::Add(9392, 8959), // components/plonk.h:230 +PolyExtStep::Add(9393, 8960), // components/plonk.h:230 +PolyExtStep::Add(9395, 8962), // components/plonk.h:230 +PolyExtStep::Add(9396, 8970), // components/plonk.h:230 +PolyExtStep::Add(9397, 8964), // components/plonk.h:230 +PolyExtStep::Add(9398, 8965), // components/plonk.h:230 +PolyExtStep::Add(9400, 8967), // components/plonk.h:230 +PolyExtStep::Add(9401, 8968), // components/plonk.h:230 +PolyExtStep::Add(9403, 8971), // components/plonk.h:230 +PolyExtStep::Add(9404, 8972), // components/plonk.h:230 +PolyExtStep::Add(9407, 8974), // components/plonk.h:230 +PolyExtStep::Add(9408, 8975), // components/plonk.h:230 +PolyExtStep::Add(9410, 8977), // components/plonk.h:230 +PolyExtStep::Add(9411, 8978), // components/plonk.h:230 +PolyExtStep::Add(9413, 8980), // components/plonk.h:230 +PolyExtStep::Add(9414, 8988), // components/plonk.h:230 +PolyExtStep::Add(9415, 8982), // components/plonk.h:230 +PolyExtStep::Add(9416, 8983), // components/plonk.h:230 +PolyExtStep::Add(9418, 8985), // components/plonk.h:230 +PolyExtStep::Add(9419, 8986), // components/plonk.h:230 +PolyExtStep::Add(9421, 8989), // components/plonk.h:230 +PolyExtStep::Add(9422, 8990), // components/plonk.h:230 +PolyExtStep::Add(9425, 8992), // components/plonk.h:230 +PolyExtStep::Add(9426, 8993), // components/plonk.h:230 +PolyExtStep::Add(9428, 8995), // components/plonk.h:230 +PolyExtStep::Add(9429, 8996), // components/plonk.h:230 +PolyExtStep::Add(9431, 8998), // components/plonk.h:230 +PolyExtStep::Add(9381, 8948), // components/plonk.h:230 +PolyExtStep::Add(9384, 8951), // components/plonk.h:230 +PolyExtStep::Add(9387, 8963), // components/plonk.h:230 +PolyExtStep::Add(9388, 8955), // components/plonk.h:230 +PolyExtStep::Add(9391, 8958), // components/plonk.h:230 +PolyExtStep::Add(9394, 8961), // components/plonk.h:230 +PolyExtStep::Add(9399, 8966), // components/plonk.h:230 +PolyExtStep::Add(9402, 8969), // components/plonk.h:230 +PolyExtStep::Add(9405, 8981), // components/plonk.h:230 +PolyExtStep::Add(9406, 8973), // components/plonk.h:230 +PolyExtStep::Add(9409, 8976), // components/plonk.h:230 +PolyExtStep::Add(9412, 8979), // components/plonk.h:230 +PolyExtStep::Add(9417, 8984), // components/plonk.h:230 +PolyExtStep::Add(9420, 8987), // components/plonk.h:230 +PolyExtStep::Add(9423, 8999), // components/plonk.h:230 +PolyExtStep::Add(9424, 8991), // components/plonk.h:230 +PolyExtStep::Add(9427, 8994), // components/plonk.h:230 +PolyExtStep::Add(9430, 8997), // components/plonk.h:230 +PolyExtStep::Mul(9468, 9459), // components/plonk.h:232 +PolyExtStep::Mul(9469, 9461), // components/plonk.h:232 +PolyExtStep::Mul(9470, 9457), // components/plonk.h:232 +PolyExtStep::Mul(9471, 9463), // components/plonk.h:232 +PolyExtStep::Mul(9472, 9465), // components/plonk.h:232 +PolyExtStep::Mul(9473, 9467), // components/plonk.h:232 +PolyExtStep::Mul(9468, 9435), // components/plonk.h:232 +PolyExtStep::Mul(9468, 9447), // components/plonk.h:232 +PolyExtStep::Mul(9468, 9363), // components/plonk.h:232 +PolyExtStep::Mul(9469, 9437), // components/plonk.h:232 +PolyExtStep::Mul(9469, 9449), // components/plonk.h:232 +PolyExtStep::Mul(9469, 9365), // components/plonk.h:232 +PolyExtStep::Mul(9470, 9433), // components/plonk.h:232 +PolyExtStep::Mul(9470, 9445), // components/plonk.h:232 +PolyExtStep::Mul(9470, 9361), // components/plonk.h:232 +PolyExtStep::Mul(9471, 9439), // components/plonk.h:232 +PolyExtStep::Mul(9471, 9451), // components/plonk.h:232 +PolyExtStep::Mul(9471, 9367), // components/plonk.h:232 +PolyExtStep::Mul(9472, 9441), // components/plonk.h:232 +PolyExtStep::Mul(9472, 9453), // components/plonk.h:232 +PolyExtStep::Mul(9472, 9369), // components/plonk.h:232 +PolyExtStep::Mul(9473, 9443), // components/plonk.h:232 +PolyExtStep::Mul(9473, 9455), // components/plonk.h:232 +PolyExtStep::Mul(9473, 9371), // components/plonk.h:232 +PolyExtStep::Mul(9474, 9459), // components/plonk.h:232 +PolyExtStep::Mul(9475, 9461), // components/plonk.h:232 +PolyExtStep::Mul(9476, 9457), // components/plonk.h:232 +PolyExtStep::Mul(9477, 9463), // components/plonk.h:232 +PolyExtStep::Mul(9478, 9465), // components/plonk.h:232 +PolyExtStep::Mul(9479, 9467), // components/plonk.h:232 +PolyExtStep::Mul(9480, 9459), // components/plonk.h:232 +PolyExtStep::Mul(9481, 9461), // components/plonk.h:232 +PolyExtStep::Mul(9482, 9457), // components/plonk.h:232 +PolyExtStep::Mul(9483, 9463), // components/plonk.h:232 +PolyExtStep::Mul(9484, 9465), // components/plonk.h:232 +PolyExtStep::Mul(9485, 9467), // components/plonk.h:232 +PolyExtStep::Mul(9372, 9435), // components/plonk.h:232 +PolyExtStep::Mul(9372, 9447), // components/plonk.h:232 +PolyExtStep::Mul(9372, 9459), // components/plonk.h:232 +PolyExtStep::Mul(9372, 9363), // components/plonk.h:232 +PolyExtStep::Mul(9373, 9437), // components/plonk.h:232 +PolyExtStep::Mul(9373, 9449), // components/plonk.h:232 +PolyExtStep::Mul(9373, 9461), // components/plonk.h:232 +PolyExtStep::Mul(9373, 9365), // components/plonk.h:232 +PolyExtStep::Mul(9374, 9433), // components/plonk.h:232 +PolyExtStep::Mul(9374, 9445), // components/plonk.h:232 +PolyExtStep::Mul(9374, 9457), // components/plonk.h:232 +PolyExtStep::Mul(9374, 9361), // components/plonk.h:232 +PolyExtStep::Mul(9375, 9439), // components/plonk.h:232 +PolyExtStep::Mul(9375, 9451), // components/plonk.h:232 +PolyExtStep::Mul(9375, 9463), // components/plonk.h:232 +PolyExtStep::Mul(9375, 9367), // components/plonk.h:232 +PolyExtStep::Mul(9376, 9441), // components/plonk.h:232 +PolyExtStep::Mul(9376, 9453), // components/plonk.h:232 +PolyExtStep::Mul(9376, 9465), // components/plonk.h:232 +PolyExtStep::Mul(9376, 9369), // components/plonk.h:232 +PolyExtStep::Mul(9377, 9443), // components/plonk.h:232 +PolyExtStep::Mul(9377, 9455), // components/plonk.h:232 +PolyExtStep::Mul(9377, 9467), // components/plonk.h:232 +PolyExtStep::Mul(9377, 9371), // components/plonk.h:232 +PolyExtStep::Mul(9474, 9435), // components/plonk.h:232 +PolyExtStep::Mul(9474, 9447), // components/plonk.h:232 +PolyExtStep::Mul(9474, 9363), // components/plonk.h:232 +PolyExtStep::Mul(9475, 9437), // components/plonk.h:232 +PolyExtStep::Mul(9475, 9449), // components/plonk.h:232 +PolyExtStep::Mul(9475, 9365), // components/plonk.h:232 +PolyExtStep::Mul(9476, 9433), // components/plonk.h:232 +PolyExtStep::Mul(9476, 9445), // components/plonk.h:232 +PolyExtStep::Mul(9476, 9361), // components/plonk.h:232 +PolyExtStep::Mul(9477, 9439), // components/plonk.h:232 +PolyExtStep::Mul(9477, 9451), // components/plonk.h:232 +PolyExtStep::Mul(9477, 9367), // components/plonk.h:232 +PolyExtStep::Mul(9478, 9441), // components/plonk.h:232 +PolyExtStep::Mul(9478, 9453), // components/plonk.h:232 +PolyExtStep::Mul(9478, 9369), // components/plonk.h:232 +PolyExtStep::Mul(9479, 9443), // components/plonk.h:232 +PolyExtStep::Mul(9479, 9455), // components/plonk.h:232 +PolyExtStep::Mul(9479, 9371), // components/plonk.h:232 +PolyExtStep::Mul(9480, 9435), // components/plonk.h:232 +PolyExtStep::Mul(9480, 9447), // components/plonk.h:232 +PolyExtStep::Mul(9480, 9363), // components/plonk.h:232 +PolyExtStep::Mul(9481, 9437), // components/plonk.h:232 +PolyExtStep::Mul(9481, 9449), // components/plonk.h:232 +PolyExtStep::Mul(9481, 9365), // components/plonk.h:232 +PolyExtStep::Mul(9482, 9433), // components/plonk.h:232 +PolyExtStep::Mul(9482, 9445), // components/plonk.h:232 +PolyExtStep::Mul(9482, 9361), // components/plonk.h:232 +PolyExtStep::Mul(9483, 9439), // components/plonk.h:232 +PolyExtStep::Mul(9483, 9451), // components/plonk.h:232 +PolyExtStep::Mul(9483, 9367), // components/plonk.h:232 +PolyExtStep::Mul(9484, 9441), // components/plonk.h:232 +PolyExtStep::Mul(9484, 9453), // components/plonk.h:232 +PolyExtStep::Mul(9484, 9369), // components/plonk.h:232 +PolyExtStep::Mul(9485, 9443), // components/plonk.h:232 +PolyExtStep::Mul(9485, 9455), // components/plonk.h:232 +PolyExtStep::Mul(9485, 9371), // components/plonk.h:232 +PolyExtStep::Mul(9516, 11), // components/plonk.h:232 +PolyExtStep::Mul(9517, 11), // components/plonk.h:232 +PolyExtStep::Mul(9518, 11), // components/plonk.h:232 +PolyExtStep::Mul(9519, 11), // components/plonk.h:232 +PolyExtStep::Mul(9520, 11), // components/plonk.h:232 +PolyExtStep::Mul(9521, 11), // components/plonk.h:232 +PolyExtStep::Add(9510, 9565), // components/plonk.h:232 +PolyExtStep::Add(9511, 9568), // components/plonk.h:232 +PolyExtStep::Add(9512, 9571), // components/plonk.h:232 +PolyExtStep::Add(9513, 9574), // components/plonk.h:232 +PolyExtStep::Add(9514, 9577), // components/plonk.h:232 +PolyExtStep::Add(9515, 9580), // components/plonk.h:232 +PolyExtStep::Add(9486, 9547), // components/plonk.h:232 +PolyExtStep::Add(9487, 9550), // components/plonk.h:232 +PolyExtStep::Add(9488, 9553), // components/plonk.h:232 +PolyExtStep::Add(9489, 9556), // components/plonk.h:232 +PolyExtStep::Add(9490, 9559), // components/plonk.h:232 +PolyExtStep::Add(9491, 9562), // components/plonk.h:232 +PolyExtStep::Add(9522, 9494), // components/plonk.h:232 +PolyExtStep::Add(9523, 9492), // components/plonk.h:232 +PolyExtStep::Add(9524, 9493), // components/plonk.h:232 +PolyExtStep::Add(9526, 9497), // components/plonk.h:232 +PolyExtStep::Add(9527, 9495), // components/plonk.h:232 +PolyExtStep::Add(9528, 9496), // components/plonk.h:232 +PolyExtStep::Add(9530, 9500), // components/plonk.h:232 +PolyExtStep::Add(9531, 9498), // components/plonk.h:232 +PolyExtStep::Add(9532, 9499), // components/plonk.h:232 +PolyExtStep::Add(9534, 9503), // components/plonk.h:232 +PolyExtStep::Add(9535, 9501), // components/plonk.h:232 +PolyExtStep::Add(9536, 9502), // components/plonk.h:232 +PolyExtStep::Add(9538, 9506), // components/plonk.h:232 +PolyExtStep::Add(9539, 9504), // components/plonk.h:232 +PolyExtStep::Add(9540, 9505), // components/plonk.h:232 +PolyExtStep::Add(9542, 9509), // components/plonk.h:232 +PolyExtStep::Add(9543, 9507), // components/plonk.h:232 +PolyExtStep::Add(9544, 9508), // components/plonk.h:232 +PolyExtStep::Mul(9588, 11), // components/plonk.h:232 +PolyExtStep::Mul(9589, 11), // components/plonk.h:232 +PolyExtStep::Mul(9590, 11), // components/plonk.h:232 +PolyExtStep::Mul(9591, 11), // components/plonk.h:232 +PolyExtStep::Mul(9592, 11), // components/plonk.h:232 +PolyExtStep::Mul(9593, 11), // components/plonk.h:232 +PolyExtStep::Add(9594, 9564), // components/plonk.h:232 +PolyExtStep::Add(9595, 9567), // components/plonk.h:232 +PolyExtStep::Add(9596, 9570), // components/plonk.h:232 +PolyExtStep::Add(9597, 9573), // components/plonk.h:232 +PolyExtStep::Add(9598, 9576), // components/plonk.h:232 +PolyExtStep::Add(9599, 9579), // components/plonk.h:232 +PolyExtStep::Add(9600, 9618), // components/plonk.h:232 +PolyExtStep::Add(9601, 9548), // components/plonk.h:232 +PolyExtStep::Add(9602, 9546), // components/plonk.h:232 +PolyExtStep::Add(9603, 9619), // components/plonk.h:232 +PolyExtStep::Add(9604, 9551), // components/plonk.h:232 +PolyExtStep::Add(9605, 9549), // components/plonk.h:232 +PolyExtStep::Add(9606, 9620), // components/plonk.h:232 +PolyExtStep::Add(9607, 9554), // components/plonk.h:232 +PolyExtStep::Add(9608, 9552), // components/plonk.h:232 +PolyExtStep::Add(9609, 9621), // components/plonk.h:232 +PolyExtStep::Add(9610, 9557), // components/plonk.h:232 +PolyExtStep::Add(9611, 9555), // components/plonk.h:232 +PolyExtStep::Add(9612, 9622), // components/plonk.h:232 +PolyExtStep::Add(9613, 9560), // components/plonk.h:232 +PolyExtStep::Add(9614, 9558), // components/plonk.h:232 +PolyExtStep::Add(9615, 9623), // components/plonk.h:232 +PolyExtStep::Add(9616, 9563), // components/plonk.h:232 +PolyExtStep::Add(9617, 9561), // components/plonk.h:232 +PolyExtStep::Mul(9630, 9460), // components/plonk.h:232 +PolyExtStep::Mul(9633, 9462), // components/plonk.h:232 +PolyExtStep::Mul(9636, 9458), // components/plonk.h:232 +PolyExtStep::Mul(9639, 9464), // components/plonk.h:232 +PolyExtStep::Mul(9642, 9466), // components/plonk.h:232 +PolyExtStep::Mul(9645, 9456), // components/plonk.h:232 +PolyExtStep::Mul(9624, 11), // components/plonk.h:232 +PolyExtStep::Mul(9625, 11), // components/plonk.h:232 +PolyExtStep::Mul(9626, 11), // components/plonk.h:232 +PolyExtStep::Mul(9627, 11), // components/plonk.h:232 +PolyExtStep::Mul(9628, 11), // components/plonk.h:232 +PolyExtStep::Mul(9629, 11), // components/plonk.h:232 +PolyExtStep::Mul(9630, 9436), // components/plonk.h:232 +PolyExtStep::Mul(9630, 9448), // components/plonk.h:232 +PolyExtStep::Mul(9630, 9364), // components/plonk.h:232 +PolyExtStep::Mul(9633, 9438), // components/plonk.h:232 +PolyExtStep::Mul(9633, 9450), // components/plonk.h:232 +PolyExtStep::Mul(9633, 9366), // components/plonk.h:232 +PolyExtStep::Mul(9636, 9434), // components/plonk.h:232 +PolyExtStep::Mul(9636, 9446), // components/plonk.h:232 +PolyExtStep::Mul(9636, 9362), // components/plonk.h:232 +PolyExtStep::Mul(9639, 9440), // components/plonk.h:232 +PolyExtStep::Mul(9639, 9452), // components/plonk.h:232 +PolyExtStep::Mul(9639, 9368), // components/plonk.h:232 +PolyExtStep::Mul(9642, 9442), // components/plonk.h:232 +PolyExtStep::Mul(9642, 9454), // components/plonk.h:232 +PolyExtStep::Mul(9642, 9370), // components/plonk.h:232 +PolyExtStep::Mul(9645, 9432), // components/plonk.h:232 +PolyExtStep::Mul(9645, 9444), // components/plonk.h:232 +PolyExtStep::Mul(9645, 9360), // components/plonk.h:232 +PolyExtStep::Add(9631, 9582), // components/plonk.h:232 +PolyExtStep::Add(9632, 9566), // components/plonk.h:232 +PolyExtStep::Add(9634, 9583), // components/plonk.h:232 +PolyExtStep::Add(9635, 9569), // components/plonk.h:232 +PolyExtStep::Add(9637, 9584), // components/plonk.h:232 +PolyExtStep::Add(9638, 9572), // components/plonk.h:232 +PolyExtStep::Add(9640, 9585), // components/plonk.h:232 +PolyExtStep::Add(9641, 9575), // components/plonk.h:232 +PolyExtStep::Add(9643, 9586), // components/plonk.h:232 +PolyExtStep::Add(9644, 9578), // components/plonk.h:232 +PolyExtStep::Add(9646, 9587), // components/plonk.h:232 +PolyExtStep::Add(9647, 9581), // components/plonk.h:232 +PolyExtStep::Add(9525, 9654), // components/plonk.h:232 +PolyExtStep::Add(9529, 9655), // components/plonk.h:232 +PolyExtStep::Add(9533, 9656), // components/plonk.h:232 +PolyExtStep::Add(9537, 9657), // components/plonk.h:232 +PolyExtStep::Add(9541, 9658), // components/plonk.h:232 +PolyExtStep::Add(9545, 9659), // components/plonk.h:232 +PolyExtStep::Mul(9678, 9460), // components/plonk.h:232 +PolyExtStep::Mul(9679, 9460), // components/plonk.h:232 +PolyExtStep::Mul(9680, 9462), // components/plonk.h:232 +PolyExtStep::Mul(9681, 9462), // components/plonk.h:232 +PolyExtStep::Mul(9682, 9458), // components/plonk.h:232 +PolyExtStep::Mul(9683, 9458), // components/plonk.h:232 +PolyExtStep::Mul(9684, 9464), // components/plonk.h:232 +PolyExtStep::Mul(9685, 9464), // components/plonk.h:232 +PolyExtStep::Mul(9686, 9466), // components/plonk.h:232 +PolyExtStep::Mul(9687, 9466), // components/plonk.h:232 +PolyExtStep::Mul(9688, 9456), // components/plonk.h:232 +PolyExtStep::Mul(9689, 9456), // components/plonk.h:232 +PolyExtStep::Mul(9690, 9436), // components/plonk.h:232 +PolyExtStep::Mul(9690, 9448), // components/plonk.h:232 +PolyExtStep::Mul(9690, 9460), // components/plonk.h:232 +PolyExtStep::Mul(9690, 9364), // components/plonk.h:232 +PolyExtStep::Mul(9691, 9438), // components/plonk.h:232 +PolyExtStep::Mul(9691, 9450), // components/plonk.h:232 +PolyExtStep::Mul(9691, 9462), // components/plonk.h:232 +PolyExtStep::Mul(9691, 9366), // components/plonk.h:232 +PolyExtStep::Mul(9692, 9434), // components/plonk.h:232 +PolyExtStep::Mul(9692, 9446), // components/plonk.h:232 +PolyExtStep::Mul(9692, 9458), // components/plonk.h:232 +PolyExtStep::Mul(9692, 9362), // components/plonk.h:232 +PolyExtStep::Mul(9693, 9440), // components/plonk.h:232 +PolyExtStep::Mul(9693, 9452), // components/plonk.h:232 +PolyExtStep::Mul(9693, 9464), // components/plonk.h:232 +PolyExtStep::Mul(9693, 9368), // components/plonk.h:232 +PolyExtStep::Mul(9694, 9442), // components/plonk.h:232 +PolyExtStep::Mul(9694, 9454), // components/plonk.h:232 +PolyExtStep::Mul(9694, 9466), // components/plonk.h:232 +PolyExtStep::Mul(9694, 9370), // components/plonk.h:232 +PolyExtStep::Mul(9695, 9432), // components/plonk.h:232 +PolyExtStep::Mul(9695, 9444), // components/plonk.h:232 +PolyExtStep::Mul(9695, 9456), // components/plonk.h:232 +PolyExtStep::Mul(9695, 9360), // components/plonk.h:232 +PolyExtStep::Mul(9678, 9436), // components/plonk.h:232 +PolyExtStep::Mul(9678, 9448), // components/plonk.h:232 +PolyExtStep::Mul(9678, 9364), // components/plonk.h:232 +PolyExtStep::Mul(9679, 9436), // components/plonk.h:232 +PolyExtStep::Mul(9679, 9448), // components/plonk.h:232 +PolyExtStep::Mul(9679, 9364), // components/plonk.h:232 +PolyExtStep::Mul(9680, 9438), // components/plonk.h:232 +PolyExtStep::Mul(9680, 9450), // components/plonk.h:232 +PolyExtStep::Mul(9680, 9366), // components/plonk.h:232 +PolyExtStep::Mul(9681, 9438), // components/plonk.h:232 +PolyExtStep::Mul(9681, 9450), // components/plonk.h:232 +PolyExtStep::Mul(9681, 9366), // components/plonk.h:232 +PolyExtStep::Mul(9682, 9434), // components/plonk.h:232 +PolyExtStep::Mul(9682, 9446), // components/plonk.h:232 +PolyExtStep::Mul(9682, 9362), // components/plonk.h:232 +PolyExtStep::Mul(9683, 9434), // components/plonk.h:232 +PolyExtStep::Mul(9683, 9446), // components/plonk.h:232 +PolyExtStep::Mul(9683, 9362), // components/plonk.h:232 +PolyExtStep::Mul(9684, 9440), // components/plonk.h:232 +PolyExtStep::Mul(9684, 9452), // components/plonk.h:232 +PolyExtStep::Mul(9684, 9368), // components/plonk.h:232 +PolyExtStep::Mul(9685, 9440), // components/plonk.h:232 +PolyExtStep::Mul(9685, 9452), // components/plonk.h:232 +PolyExtStep::Mul(9685, 9368), // components/plonk.h:232 +PolyExtStep::Mul(9686, 9442), // components/plonk.h:232 +PolyExtStep::Mul(9686, 9454), // components/plonk.h:232 +PolyExtStep::Mul(9686, 9370), // components/plonk.h:232 +PolyExtStep::Mul(9687, 9442), // components/plonk.h:232 +PolyExtStep::Mul(9687, 9454), // components/plonk.h:232 +PolyExtStep::Mul(9687, 9370), // components/plonk.h:232 +PolyExtStep::Mul(9688, 9432), // components/plonk.h:232 +PolyExtStep::Mul(9688, 9444), // components/plonk.h:232 +PolyExtStep::Mul(9688, 9360), // components/plonk.h:232 +PolyExtStep::Mul(9689, 9432), // components/plonk.h:232 +PolyExtStep::Mul(9689, 9444), // components/plonk.h:232 +PolyExtStep::Mul(9689, 9360), // components/plonk.h:232 +PolyExtStep::Mul(9697, 11), // components/plonk.h:232 +PolyExtStep::Mul(9699, 11), // components/plonk.h:232 +PolyExtStep::Mul(9701, 11), // components/plonk.h:232 +PolyExtStep::Mul(9703, 11), // components/plonk.h:232 +PolyExtStep::Mul(9705, 11), // components/plonk.h:232 +PolyExtStep::Mul(9707, 11), // components/plonk.h:232 +PolyExtStep::Add(9696, 9736), // components/plonk.h:232 +PolyExtStep::Add(9698, 9742), // components/plonk.h:232 +PolyExtStep::Add(9700, 9748), // components/plonk.h:232 +PolyExtStep::Add(9702, 9754), // components/plonk.h:232 +PolyExtStep::Add(9704, 9760), // components/plonk.h:232 +PolyExtStep::Add(9706, 9766), // components/plonk.h:232 +PolyExtStep::Add(9648, 9733), // components/plonk.h:232 +PolyExtStep::Add(9649, 9739), // components/plonk.h:232 +PolyExtStep::Add(9650, 9745), // components/plonk.h:232 +PolyExtStep::Add(9651, 9751), // components/plonk.h:232 +PolyExtStep::Add(9652, 9757), // components/plonk.h:232 +PolyExtStep::Add(9653, 9763), // components/plonk.h:232 +PolyExtStep::Add(9708, 9662), // components/plonk.h:232 +PolyExtStep::Add(9709, 9660), // components/plonk.h:232 +PolyExtStep::Add(9710, 9661), // components/plonk.h:232 +PolyExtStep::Add(9712, 9665), // components/plonk.h:232 +PolyExtStep::Add(9713, 9663), // components/plonk.h:232 +PolyExtStep::Add(9714, 9664), // components/plonk.h:232 +PolyExtStep::Add(9716, 9668), // components/plonk.h:232 +PolyExtStep::Add(9717, 9666), // components/plonk.h:232 +PolyExtStep::Add(9718, 9667), // components/plonk.h:232 +PolyExtStep::Add(9720, 9671), // components/plonk.h:232 +PolyExtStep::Add(9721, 9669), // components/plonk.h:232 +PolyExtStep::Add(9722, 9670), // components/plonk.h:232 +PolyExtStep::Add(9724, 9674), // components/plonk.h:232 +PolyExtStep::Add(9725, 9672), // components/plonk.h:232 +PolyExtStep::Add(9726, 9673), // components/plonk.h:232 +PolyExtStep::Add(9728, 9677), // components/plonk.h:232 +PolyExtStep::Add(9729, 9675), // components/plonk.h:232 +PolyExtStep::Add(9730, 9676), // components/plonk.h:232 +PolyExtStep::Mul(9774, 11), // components/plonk.h:232 +PolyExtStep::Mul(9775, 11), // components/plonk.h:232 +PolyExtStep::Mul(9776, 11), // components/plonk.h:232 +PolyExtStep::Mul(9777, 11), // components/plonk.h:232 +PolyExtStep::Mul(9778, 11), // components/plonk.h:232 +PolyExtStep::Mul(9779, 11), // components/plonk.h:232 +PolyExtStep::Add(9780, 9735), // components/plonk.h:232 +PolyExtStep::Add(9781, 9741), // components/plonk.h:232 +PolyExtStep::Add(9782, 9747), // components/plonk.h:232 +PolyExtStep::Add(9783, 9753), // components/plonk.h:232 +PolyExtStep::Add(9784, 9759), // components/plonk.h:232 +PolyExtStep::Add(9785, 9765), // components/plonk.h:232 +PolyExtStep::Add(9787, 9734), // components/plonk.h:232 +PolyExtStep::Add(9788, 9732), // components/plonk.h:232 +PolyExtStep::Add(9790, 9740), // components/plonk.h:232 +PolyExtStep::Add(9791, 9738), // components/plonk.h:232 +PolyExtStep::Add(9793, 9746), // components/plonk.h:232 +PolyExtStep::Add(9794, 9744), // components/plonk.h:232 +PolyExtStep::Add(9796, 9752), // components/plonk.h:232 +PolyExtStep::Add(9797, 9750), // components/plonk.h:232 +PolyExtStep::Add(9799, 9758), // components/plonk.h:232 +PolyExtStep::Add(9800, 9756), // components/plonk.h:232 +PolyExtStep::Add(9802, 9764), // components/plonk.h:232 +PolyExtStep::Add(9803, 9762), // components/plonk.h:232 +PolyExtStep::Add(9786, 9804), // components/plonk.h:232 +PolyExtStep::Add(9789, 9805), // components/plonk.h:232 +PolyExtStep::Add(9792, 9806), // components/plonk.h:232 +PolyExtStep::Add(9816, 9768), // components/plonk.h:232 +PolyExtStep::Add(9817, 9737), // components/plonk.h:232 +PolyExtStep::Add(9818, 9769), // components/plonk.h:232 +PolyExtStep::Add(9819, 9743), // components/plonk.h:232 +PolyExtStep::Add(9820, 9770), // components/plonk.h:232 +PolyExtStep::Add(9821, 9749), // components/plonk.h:232 +PolyExtStep::Add(9822, 9771), // components/plonk.h:232 +PolyExtStep::Add(9823, 9755), // components/plonk.h:232 +PolyExtStep::Add(9824, 9772), // components/plonk.h:232 +PolyExtStep::Add(9825, 9761), // components/plonk.h:232 +PolyExtStep::Add(9826, 9773), // components/plonk.h:232 +PolyExtStep::Add(9827, 9767), // components/plonk.h:232 +PolyExtStep::Add(9795, 9807), // components/plonk.h:232 +PolyExtStep::Add(9798, 9808), // components/plonk.h:232 +PolyExtStep::Add(9801, 9809), // components/plonk.h:232 +PolyExtStep::Mul(9810, 11), // components/plonk.h:232 +PolyExtStep::Mul(9811, 11), // components/plonk.h:232 +PolyExtStep::Mul(9812, 11), // components/plonk.h:232 +PolyExtStep::Mul(9813, 11), // components/plonk.h:232 +PolyExtStep::Mul(9814, 11), // components/plonk.h:232 +PolyExtStep::Mul(9815, 11), // components/plonk.h:232 +PolyExtStep::Add(9711, 9846), // components/plonk.h:232 +PolyExtStep::Add(9715, 9847), // components/plonk.h:232 +PolyExtStep::Add(9719, 9848), // components/plonk.h:232 +PolyExtStep::Add(9723, 9849), // components/plonk.h:232 +PolyExtStep::Add(9727, 9850), // components/plonk.h:232 +PolyExtStep::Add(9731, 9851), // components/plonk.h:232 +PolyExtStep::Get(8), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/wom_body(recursion::WomBody)/plonk_body(PlonkBody)/FpExtReg/elem[0](Reg)(components/plonk.h:298) +PolyExtStep::Get(9), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/wom_body(recursion::WomBody)/plonk_body(PlonkBody)/FpExtReg/elem[1](Reg)(components/plonk.h:298) +PolyExtStep::Get(10), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/wom_body(recursion::WomBody)/plonk_body(PlonkBody)/FpExtReg/elem[2](Reg)(components/plonk.h:298) +PolyExtStep::Get(11), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/wom_body(recursion::WomBody)/plonk_body(PlonkBody)/FpExtReg/elem[3](Reg)(components/plonk.h:298) +PolyExtStep::Get(1), // top(recursion::Top)/recursion::WomHeader/accum(FpExtReg)/elem[0](Reg)(components/plonk.h:296) +PolyExtStep::Get(3), // top(recursion::Top)/recursion::WomHeader/accum(FpExtReg)/elem[1](Reg)(components/plonk.h:296) +PolyExtStep::Get(5), // top(recursion::Top)/recursion::WomHeader/accum(FpExtReg)/elem[2](Reg)(components/plonk.h:296) +PolyExtStep::Get(7), // top(recursion::Top)/recursion::WomHeader/accum(FpExtReg)/elem[3](Reg)(components/plonk.h:296) +PolyExtStep::Mul(9858, 9837), // components/plonk.h:299 +PolyExtStep::Mul(9858, 9838), // components/plonk.h:299 +PolyExtStep::Mul(9858, 9843), // components/plonk.h:299 +PolyExtStep::Mul(9858, 9855), // components/plonk.h:299 +PolyExtStep::Mul(9859, 9838), // components/plonk.h:299 +PolyExtStep::Mul(9860, 9838), // components/plonk.h:299 +PolyExtStep::Mul(9861, 9838), // components/plonk.h:299 +PolyExtStep::Mul(9862, 9830), // components/plonk.h:299 +PolyExtStep::Mul(9862, 9854), // components/plonk.h:299 +PolyExtStep::Mul(9862, 9835), // components/plonk.h:299 +PolyExtStep::Mul(9862, 9836), // components/plonk.h:299 +PolyExtStep::Mul(9863, 9836), // components/plonk.h:299 +PolyExtStep::Mul(9864, 9836), // components/plonk.h:299 +PolyExtStep::Mul(9865, 9836), // components/plonk.h:299 +PolyExtStep::Mul(9859, 9837), // components/plonk.h:299 +PolyExtStep::Mul(9859, 9843), // components/plonk.h:299 +PolyExtStep::Mul(9859, 9855), // components/plonk.h:299 +PolyExtStep::Mul(9860, 9837), // components/plonk.h:299 +PolyExtStep::Mul(9860, 9843), // components/plonk.h:299 +PolyExtStep::Mul(9860, 9855), // components/plonk.h:299 +PolyExtStep::Mul(9861, 9837), // components/plonk.h:299 +PolyExtStep::Mul(9861, 9843), // components/plonk.h:299 +PolyExtStep::Mul(9861, 9855), // components/plonk.h:299 +PolyExtStep::Mul(9863, 9830), // components/plonk.h:299 +PolyExtStep::Mul(9863, 9854), // components/plonk.h:299 +PolyExtStep::Mul(9863, 9835), // components/plonk.h:299 +PolyExtStep::Mul(9864, 9830), // components/plonk.h:299 +PolyExtStep::Mul(9864, 9854), // components/plonk.h:299 +PolyExtStep::Mul(9864, 9835), // components/plonk.h:299 +PolyExtStep::Mul(9865, 9830), // components/plonk.h:299 +PolyExtStep::Mul(9865, 9854), // components/plonk.h:299 +PolyExtStep::Mul(9865, 9835), // components/plonk.h:299 +PolyExtStep::Mul(9872, 11), // components/plonk.h:299 +PolyExtStep::Mul(9879, 11), // components/plonk.h:299 +PolyExtStep::Add(9866, 9881), // components/plonk.h:299 +PolyExtStep::Add(9867, 9880), // components/plonk.h:299 +PolyExtStep::Add(9868, 9882), // components/plonk.h:299 +PolyExtStep::Add(9870, 9883), // components/plonk.h:299 +PolyExtStep::Add(9871, 9886), // components/plonk.h:299 +PolyExtStep::Add(9873, 9890), // components/plonk.h:299 +PolyExtStep::Add(9875, 9889), // components/plonk.h:299 +PolyExtStep::Add(9876, 9891), // components/plonk.h:299 +PolyExtStep::Add(9877, 9894), // components/plonk.h:299 +PolyExtStep::Add(9878, 9897), // components/plonk.h:299 +PolyExtStep::Mul(9904, 11), // components/plonk.h:299 +PolyExtStep::Mul(9909, 11), // components/plonk.h:299 +PolyExtStep::Add(9900, 9885), // components/plonk.h:299 +PolyExtStep::Add(9901, 9884), // components/plonk.h:299 +PolyExtStep::Add(9903, 9887), // components/plonk.h:299 +PolyExtStep::Add(9905, 9911), // components/plonk.h:299 +PolyExtStep::Add(9906, 9893), // components/plonk.h:299 +PolyExtStep::Add(9907, 9892), // components/plonk.h:299 +PolyExtStep::Add(9908, 9895), // components/plonk.h:299 +PolyExtStep::Add(9912, 9898), // components/plonk.h:299 +PolyExtStep::Add(9913, 9888), // components/plonk.h:299 +PolyExtStep::Add(9902, 9910), // components/plonk.h:299 +PolyExtStep::Mul(9914, 11), // components/plonk.h:299 +PolyExtStep::Mul(9918, 11), // components/plonk.h:299 +PolyExtStep::Add(9916, 9899), // components/plonk.h:299 +PolyExtStep::Add(9917, 9896), // components/plonk.h:299 +PolyExtStep::Add(9874, 9923), // components/plonk.h:299 +PolyExtStep::Add(9869, 9922), // components/plonk.h:299 +PolyExtStep::Sub(9926, 9927), // components/plonk.h:299 +PolyExtStep::AndEqz(0, 9928), // components/plonk.h:299 +PolyExtStep::Sub(9915, 9921), // components/plonk.h:299 +PolyExtStep::AndEqz(943, 9929), // components/plonk.h:299 +PolyExtStep::Sub(9924, 9919), // components/plonk.h:299 +PolyExtStep::AndEqz(944, 9930), // components/plonk.h:299 +PolyExtStep::Sub(9925, 9920), // components/plonk.h:299 +PolyExtStep::AndEqz(945, 9931), // components/plonk.h:299 +PolyExtStep::Mul(9858, 9828), // components/plonk.h:299 +PolyExtStep::Mul(9858, 9852), // components/plonk.h:299 +PolyExtStep::Mul(9858, 9831), // components/plonk.h:299 +PolyExtStep::Mul(9858, 9832), // components/plonk.h:299 +PolyExtStep::Mul(9859, 9832), // components/plonk.h:299 +PolyExtStep::Mul(9860, 9832), // components/plonk.h:299 +PolyExtStep::Mul(9861, 9832), // components/plonk.h:299 +PolyExtStep::Mul(9859, 9828), // components/plonk.h:299 +PolyExtStep::Mul(9859, 9852), // components/plonk.h:299 +PolyExtStep::Mul(9859, 9831), // components/plonk.h:299 +PolyExtStep::Mul(9860, 9828), // components/plonk.h:299 +PolyExtStep::Mul(9860, 9852), // components/plonk.h:299 +PolyExtStep::Mul(9860, 9831), // components/plonk.h:299 +PolyExtStep::Mul(9861, 9828), // components/plonk.h:299 +PolyExtStep::Mul(9861, 9852), // components/plonk.h:299 +PolyExtStep::Mul(9861, 9831), // components/plonk.h:299 +PolyExtStep::Mul(9938, 11), // components/plonk.h:299 +PolyExtStep::Add(9932, 9940), // components/plonk.h:299 +PolyExtStep::Add(9934, 9939), // components/plonk.h:299 +PolyExtStep::Add(9935, 9941), // components/plonk.h:299 +PolyExtStep::Add(9936, 9944), // components/plonk.h:299 +PolyExtStep::Add(9937, 9947), // components/plonk.h:299 +PolyExtStep::Get(14), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/wom_body(recursion::WomBody)/plonk_body(PlonkBody)/FpExtReg/elem[2](Reg)(components/plonk.h:298) +PolyExtStep::Get(15), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/wom_body(recursion::WomBody)/plonk_body(PlonkBody)/FpExtReg/elem[3](Reg)(components/plonk.h:298) +PolyExtStep::Get(12), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/wom_body(recursion::WomBody)/plonk_body(PlonkBody)/FpExtReg/elem[0](Reg)(components/plonk.h:298) +PolyExtStep::Get(13), // top(recursion::Top)/mux(Mux)/micro_ops(recursion::MicroOps)/wom_body(recursion::WomBody)/plonk_body(PlonkBody)/FpExtReg/elem[1](Reg)(components/plonk.h:298) +PolyExtStep::Mul(9954, 9840), // components/plonk.h:299 +PolyExtStep::Mul(9955, 9840), // components/plonk.h:299 +PolyExtStep::Mul(9956, 9839), // components/plonk.h:299 +PolyExtStep::Mul(9956, 9840), // components/plonk.h:299 +PolyExtStep::Mul(9956, 9844), // components/plonk.h:299 +PolyExtStep::Mul(9956, 9856), // components/plonk.h:299 +PolyExtStep::Mul(9957, 9840), // components/plonk.h:299 +PolyExtStep::Mul(9953, 11), // components/plonk.h:299 +PolyExtStep::Mul(9954, 9839), // components/plonk.h:299 +PolyExtStep::Mul(9954, 9844), // components/plonk.h:299 +PolyExtStep::Mul(9954, 9856), // components/plonk.h:299 +PolyExtStep::Mul(9955, 9839), // components/plonk.h:299 +PolyExtStep::Mul(9955, 9844), // components/plonk.h:299 +PolyExtStep::Mul(9955, 9856), // components/plonk.h:299 +PolyExtStep::Mul(9957, 9839), // components/plonk.h:299 +PolyExtStep::Mul(9957, 9844), // components/plonk.h:299 +PolyExtStep::Mul(9957, 9856), // components/plonk.h:299 +PolyExtStep::Mul(9959, 11), // components/plonk.h:299 +PolyExtStep::Add(9949, 9965), // components/plonk.h:299 +PolyExtStep::Add(9950, 9943), // components/plonk.h:299 +PolyExtStep::Add(9951, 9942), // components/plonk.h:299 +PolyExtStep::Add(9952, 9945), // components/plonk.h:299 +PolyExtStep::Add(9958, 9969), // components/plonk.h:299 +PolyExtStep::Add(9960, 9973), // components/plonk.h:299 +PolyExtStep::Add(9961, 9972), // components/plonk.h:299 +PolyExtStep::Add(9962, 9974), // components/plonk.h:299 +PolyExtStep::Add(9964, 9966), // components/plonk.h:299 +PolyExtStep::Mul(9979, 11), // components/plonk.h:299 +PolyExtStep::Mul(9980, 11), // components/plonk.h:299 +PolyExtStep::Add(9977, 9948), // components/plonk.h:299 +PolyExtStep::Add(9978, 9946), // components/plonk.h:299 +PolyExtStep::Add(9981, 9968), // components/plonk.h:299 +PolyExtStep::Add(9982, 9967), // components/plonk.h:299 +PolyExtStep::Add(9984, 9970), // components/plonk.h:299 +PolyExtStep::Add(9933, 9985), // components/plonk.h:299 +PolyExtStep::Add(9989, 9975), // components/plonk.h:299 +PolyExtStep::Add(9990, 9971), // components/plonk.h:299 +PolyExtStep::Add(9983, 9986), // components/plonk.h:299 +PolyExtStep::Mul(9991, 11), // components/plonk.h:299 +PolyExtStep::Add(9963, 9996), // components/plonk.h:299 +PolyExtStep::Sub(9992, 9997), // components/plonk.h:299 +PolyExtStep::AndEqz(946, 9998), // components/plonk.h:299 +PolyExtStep::Sub(9976, 9995), // components/plonk.h:299 +PolyExtStep::AndEqz(947, 9999), // components/plonk.h:299 +PolyExtStep::Sub(9987, 9993), // components/plonk.h:299 +PolyExtStep::AndEqz(948, 10000), // components/plonk.h:299 +PolyExtStep::Sub(9988, 9994), // components/plonk.h:299 +PolyExtStep::AndEqz(949, 10001), // components/plonk.h:299 +PolyExtStep::Mul(9954, 9834), // components/plonk.h:299 +PolyExtStep::Mul(9955, 9834), // components/plonk.h:299 +PolyExtStep::Mul(9956, 9829), // components/plonk.h:299 +PolyExtStep::Mul(9956, 9853), // components/plonk.h:299 +PolyExtStep::Mul(9956, 9833), // components/plonk.h:299 +PolyExtStep::Mul(9956, 9834), // components/plonk.h:299 +PolyExtStep::Mul(9957, 9834), // components/plonk.h:299 +PolyExtStep::Mul(9954, 9829), // components/plonk.h:299 +PolyExtStep::Mul(9954, 9853), // components/plonk.h:299 +PolyExtStep::Mul(9954, 9833), // components/plonk.h:299 +PolyExtStep::Mul(9955, 9829), // components/plonk.h:299 +PolyExtStep::Mul(9955, 9853), // components/plonk.h:299 +PolyExtStep::Mul(9955, 9833), // components/plonk.h:299 +PolyExtStep::Mul(9957, 9829), // components/plonk.h:299 +PolyExtStep::Mul(9957, 9853), // components/plonk.h:299 +PolyExtStep::Mul(9957, 9833), // components/plonk.h:299 +PolyExtStep::Mul(10003, 11), // components/plonk.h:299 +PolyExtStep::Add(10002, 10014), // components/plonk.h:299 +PolyExtStep::Add(10004, 10016), // components/plonk.h:299 +PolyExtStep::Add(10006, 10015), // components/plonk.h:299 +PolyExtStep::Add(10007, 10017), // components/plonk.h:299 +PolyExtStep::Add(10008, 10011), // components/plonk.h:299 +PolyExtStep::Get(0), // top(recursion::Top)/recursion::WomHeader/accum(FpExtReg)/elem[0](Reg)(components/plonk.h:298) +PolyExtStep::Get(2), // top(recursion::Top)/recursion::WomHeader/accum(FpExtReg)/elem[1](Reg)(components/plonk.h:298) +PolyExtStep::Get(4), // top(recursion::Top)/recursion::WomHeader/accum(FpExtReg)/elem[2](Reg)(components/plonk.h:298) +PolyExtStep::Get(6), // top(recursion::Top)/recursion::WomHeader/accum(FpExtReg)/elem[3](Reg)(components/plonk.h:298) +PolyExtStep::Mul(10024, 9841), // components/plonk.h:299 +PolyExtStep::Mul(10024, 9842), // components/plonk.h:299 +PolyExtStep::Mul(10024, 9845), // components/plonk.h:299 +PolyExtStep::Mul(10024, 9857), // components/plonk.h:299 +PolyExtStep::Mul(10025, 9842), // components/plonk.h:299 +PolyExtStep::Mul(10026, 9842), // components/plonk.h:299 +PolyExtStep::Mul(10027, 9842), // components/plonk.h:299 +PolyExtStep::Mul(10019, 11), // components/plonk.h:299 +PolyExtStep::Mul(10025, 9841), // components/plonk.h:299 +PolyExtStep::Mul(10025, 9845), // components/plonk.h:299 +PolyExtStep::Mul(10025, 9857), // components/plonk.h:299 +PolyExtStep::Mul(10026, 9841), // components/plonk.h:299 +PolyExtStep::Mul(10026, 9845), // components/plonk.h:299 +PolyExtStep::Mul(10026, 9857), // components/plonk.h:299 +PolyExtStep::Mul(10027, 9841), // components/plonk.h:299 +PolyExtStep::Mul(10027, 9845), // components/plonk.h:299 +PolyExtStep::Mul(10027, 9857), // components/plonk.h:299 +PolyExtStep::Mul(10034, 11), // components/plonk.h:299 +PolyExtStep::Add(10020, 10035), // components/plonk.h:299 +PolyExtStep::Add(10021, 10010), // components/plonk.h:299 +PolyExtStep::Add(10022, 10009), // components/plonk.h:299 +PolyExtStep::Add(10023, 10012), // components/plonk.h:299 +PolyExtStep::Add(10028, 10037), // components/plonk.h:299 +PolyExtStep::Add(10029, 10036), // components/plonk.h:299 +PolyExtStep::Add(10030, 10038), // components/plonk.h:299 +PolyExtStep::Add(10032, 10039), // components/plonk.h:299 +PolyExtStep::Add(10033, 10042), // components/plonk.h:299 +PolyExtStep::Mul(10049, 11), // components/plonk.h:299 +PolyExtStep::Mul(10054, 11), // components/plonk.h:299 +PolyExtStep::Add(10047, 10018), // components/plonk.h:299 +PolyExtStep::Add(10048, 10013), // components/plonk.h:299 +PolyExtStep::Add(10050, 10041), // components/plonk.h:299 +PolyExtStep::Add(10051, 10040), // components/plonk.h:299 +PolyExtStep::Add(10053, 10043), // components/plonk.h:299 +PolyExtStep::Add(10005, 10055), // components/plonk.h:299 +PolyExtStep::Add(10059, 10045), // components/plonk.h:299 +PolyExtStep::Add(10060, 10044), // components/plonk.h:299 +PolyExtStep::Add(10052, 10056), // components/plonk.h:299 +PolyExtStep::Mul(10061, 11), // components/plonk.h:299 +PolyExtStep::Add(10031, 10066), // components/plonk.h:299 +PolyExtStep::Sub(10062, 10067), // components/plonk.h:299 +PolyExtStep::AndEqz(950, 10068), // components/plonk.h:299 +PolyExtStep::Sub(10046, 10065), // components/plonk.h:299 +PolyExtStep::AndEqz(951, 10069), // components/plonk.h:299 +PolyExtStep::Sub(10057, 10063), // components/plonk.h:299 +PolyExtStep::AndEqz(952, 10070), // components/plonk.h:299 +PolyExtStep::Sub(10058, 10064), // components/plonk.h:299 +PolyExtStep::AndEqz(953, 10071), // components/plonk.h:299 +PolyExtStep::AndCond(942, 284, 954), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Sub(10024, 1), // zirgen/components/fpext.cpp:38 +PolyExtStep::AndEqz(0, 10072), // zirgen/components/fpext.cpp:38 +PolyExtStep::AndEqz(956, 10025), // zirgen/components/fpext.cpp:38 +PolyExtStep::AndEqz(957, 10026), // zirgen/components/fpext.cpp:38 +PolyExtStep::AndEqz(958, 10027), // zirgen/components/fpext.cpp:38 +PolyExtStep::AndCond(0, 317, 959), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Sub(9862, 1), // components/plonk.h:134 +PolyExtStep::AndEqz(0, 10073), // components/plonk.h:134 +PolyExtStep::AndEqz(961, 9863), // components/plonk.h:134 +PolyExtStep::AndEqz(962, 9864), // components/plonk.h:134 +PolyExtStep::AndEqz(963, 9865), // components/plonk.h:134 +PolyExtStep::AndCond(960, 319, 964), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Mul(8800, 326), // components/plonk.h:230 +PolyExtStep::Mul(8800, 332), // components/plonk.h:230 +PolyExtStep::Mul(8800, 510), // components/plonk.h:230 +PolyExtStep::Mul(8800, 515), // components/plonk.h:230 +PolyExtStep::Mul(8800, 521), // components/plonk.h:230 +PolyExtStep::Mul(8801, 326), // components/plonk.h:230 +PolyExtStep::Mul(8801, 332), // components/plonk.h:230 +PolyExtStep::Mul(8801, 510), // components/plonk.h:230 +PolyExtStep::Mul(8801, 515), // components/plonk.h:230 +PolyExtStep::Mul(8801, 521), // components/plonk.h:230 +PolyExtStep::Mul(8802, 328), // components/plonk.h:230 +PolyExtStep::Mul(8802, 336), // components/plonk.h:230 +PolyExtStep::Mul(8802, 512), // components/plonk.h:230 +PolyExtStep::Mul(8802, 517), // components/plonk.h:230 +PolyExtStep::Mul(8802, 525), // components/plonk.h:230 +PolyExtStep::Mul(8803, 328), // components/plonk.h:230 +PolyExtStep::Mul(8803, 336), // components/plonk.h:230 +PolyExtStep::Mul(8803, 512), // components/plonk.h:230 +PolyExtStep::Mul(8803, 517), // components/plonk.h:230 +PolyExtStep::Mul(8803, 525), // components/plonk.h:230 +PolyExtStep::Mul(8805, 329), // components/plonk.h:230 +PolyExtStep::Mul(8805, 338), // components/plonk.h:230 +PolyExtStep::Mul(8805, 513), // components/plonk.h:230 +PolyExtStep::Mul(8805, 518), // components/plonk.h:230 +PolyExtStep::Mul(8805, 527), // components/plonk.h:230 +PolyExtStep::Mul(8806, 329), // components/plonk.h:230 +PolyExtStep::Mul(8806, 338), // components/plonk.h:230 +PolyExtStep::Mul(8806, 513), // components/plonk.h:230 +PolyExtStep::Mul(8806, 518), // components/plonk.h:230 +PolyExtStep::Mul(8806, 527), // components/plonk.h:230 +PolyExtStep::Mul(8807, 329), // components/plonk.h:230 +PolyExtStep::Mul(8807, 338), // components/plonk.h:230 +PolyExtStep::Mul(8807, 513), // components/plonk.h:230 +PolyExtStep::Mul(8807, 518), // components/plonk.h:230 +PolyExtStep::Mul(8807, 527), // components/plonk.h:230 +PolyExtStep::Mul(8809, 330), // components/plonk.h:230 +PolyExtStep::Mul(8809, 509), // components/plonk.h:230 +PolyExtStep::Mul(8809, 514), // components/plonk.h:230 +PolyExtStep::Mul(8809, 519), // components/plonk.h:230 +PolyExtStep::Mul(8809, 698), // components/plonk.h:230 +PolyExtStep::Mul(8810, 330), // components/plonk.h:230 +PolyExtStep::Mul(8810, 509), // components/plonk.h:230 +PolyExtStep::Mul(8810, 514), // components/plonk.h:230 +PolyExtStep::Mul(8810, 519), // components/plonk.h:230 +PolyExtStep::Mul(8810, 698), // components/plonk.h:230 +PolyExtStep::Mul(8811, 330), // components/plonk.h:230 +PolyExtStep::Mul(8811, 509), // components/plonk.h:230 +PolyExtStep::Mul(8811, 514), // components/plonk.h:230 +PolyExtStep::Mul(8811, 519), // components/plonk.h:230 +PolyExtStep::Mul(8811, 698), // components/plonk.h:230 +PolyExtStep::Mul(8812, 326), // components/plonk.h:230 +PolyExtStep::Mul(8812, 332), // components/plonk.h:230 +PolyExtStep::Mul(8812, 510), // components/plonk.h:230 +PolyExtStep::Mul(8812, 515), // components/plonk.h:230 +PolyExtStep::Mul(8812, 521), // components/plonk.h:230 +PolyExtStep::Mul(8813, 326), // components/plonk.h:230 +PolyExtStep::Mul(8813, 332), // components/plonk.h:230 +PolyExtStep::Mul(8813, 510), // components/plonk.h:230 +PolyExtStep::Mul(8813, 515), // components/plonk.h:230 +PolyExtStep::Mul(8813, 521), // components/plonk.h:230 +PolyExtStep::Mul(8815, 327), // components/plonk.h:230 +PolyExtStep::Mul(8815, 334), // components/plonk.h:230 +PolyExtStep::Mul(8815, 511), // components/plonk.h:230 +PolyExtStep::Mul(8815, 516), // components/plonk.h:230 +PolyExtStep::Mul(8815, 523), // components/plonk.h:230 +PolyExtStep::Mul(8816, 327), // components/plonk.h:230 +PolyExtStep::Mul(8816, 334), // components/plonk.h:230 +PolyExtStep::Mul(8816, 511), // components/plonk.h:230 +PolyExtStep::Mul(8816, 516), // components/plonk.h:230 +PolyExtStep::Mul(8816, 523), // components/plonk.h:230 +PolyExtStep::Mul(8817, 327), // components/plonk.h:230 +PolyExtStep::Mul(8817, 334), // components/plonk.h:230 +PolyExtStep::Mul(8817, 511), // components/plonk.h:230 +PolyExtStep::Mul(8817, 516), // components/plonk.h:230 +PolyExtStep::Mul(8817, 523), // components/plonk.h:230 +PolyExtStep::Mul(8819, 328), // components/plonk.h:230 +PolyExtStep::Mul(8819, 336), // components/plonk.h:230 +PolyExtStep::Mul(8819, 512), // components/plonk.h:230 +PolyExtStep::Mul(8819, 517), // components/plonk.h:230 +PolyExtStep::Mul(8819, 525), // components/plonk.h:230 +PolyExtStep::Mul(8804, 329), // components/plonk.h:230 +PolyExtStep::Mul(8804, 338), // components/plonk.h:230 +PolyExtStep::Mul(8804, 513), // components/plonk.h:230 +PolyExtStep::Mul(8804, 518), // components/plonk.h:230 +PolyExtStep::Mul(8804, 527), // components/plonk.h:230 +PolyExtStep::Mul(8808, 330), // components/plonk.h:230 +PolyExtStep::Mul(8808, 509), // components/plonk.h:230 +PolyExtStep::Mul(8808, 514), // components/plonk.h:230 +PolyExtStep::Mul(8808, 519), // components/plonk.h:230 +PolyExtStep::Mul(8808, 698), // components/plonk.h:230 +PolyExtStep::Mul(8814, 327), // components/plonk.h:230 +PolyExtStep::Mul(8814, 334), // components/plonk.h:230 +PolyExtStep::Mul(8814, 511), // components/plonk.h:230 +PolyExtStep::Mul(8814, 516), // components/plonk.h:230 +PolyExtStep::Mul(8814, 523), // components/plonk.h:230 +PolyExtStep::Mul(8818, 328), // components/plonk.h:230 +PolyExtStep::Mul(8818, 336), // components/plonk.h:230 +PolyExtStep::Mul(8818, 512), // components/plonk.h:230 +PolyExtStep::Mul(8818, 517), // components/plonk.h:230 +PolyExtStep::Mul(8818, 525), // components/plonk.h:230 +PolyExtStep::Add(10074, 1), // components/plonk.h:230 +PolyExtStep::Add(10075, 1), // components/plonk.h:230 +PolyExtStep::Add(10076, 1), // components/plonk.h:230 +PolyExtStep::Add(10077, 1), // components/plonk.h:230 +PolyExtStep::Add(10078, 1), // components/plonk.h:230 +PolyExtStep::Add(10174, 10164), // components/plonk.h:230 +PolyExtStep::Add(10175, 10165), // components/plonk.h:230 +PolyExtStep::Add(10176, 10166), // components/plonk.h:230 +PolyExtStep::Add(10177, 10167), // components/plonk.h:230 +PolyExtStep::Add(10178, 10168), // components/plonk.h:230 +PolyExtStep::Add(10179, 10169), // components/plonk.h:230 +PolyExtStep::Add(10180, 10170), // components/plonk.h:230 +PolyExtStep::Add(10181, 10171), // components/plonk.h:230 +PolyExtStep::Add(10182, 10172), // components/plonk.h:230 +PolyExtStep::Add(10183, 10173), // components/plonk.h:230 +PolyExtStep::Add(10079, 10134), // components/plonk.h:230 +PolyExtStep::Add(10080, 10135), // components/plonk.h:230 +PolyExtStep::Add(10081, 10136), // components/plonk.h:230 +PolyExtStep::Add(10082, 10137), // components/plonk.h:230 +PolyExtStep::Add(10083, 10138), // components/plonk.h:230 +PolyExtStep::Add(10124, 10139), // components/plonk.h:230 +PolyExtStep::Add(10125, 10140), // components/plonk.h:230 +PolyExtStep::Add(10126, 10141), // components/plonk.h:230 +PolyExtStep::Add(10127, 10142), // components/plonk.h:230 +PolyExtStep::Add(10128, 10143), // components/plonk.h:230 +PolyExtStep::Add(10129, 10144), // components/plonk.h:230 +PolyExtStep::Add(10130, 10145), // components/plonk.h:230 +PolyExtStep::Add(10131, 10146), // components/plonk.h:230 +PolyExtStep::Add(10132, 10147), // components/plonk.h:230 +PolyExtStep::Add(10133, 10148), // components/plonk.h:230 +PolyExtStep::Add(10184, 10154), // components/plonk.h:230 +PolyExtStep::Add(10185, 10155), // components/plonk.h:230 +PolyExtStep::Add(10186, 10156), // components/plonk.h:230 +PolyExtStep::Add(10187, 10157), // components/plonk.h:230 +PolyExtStep::Add(10188, 10158), // components/plonk.h:230 +PolyExtStep::Add(10189, 10149), // components/plonk.h:230 +PolyExtStep::Add(10190, 10150), // components/plonk.h:230 +PolyExtStep::Add(10191, 10151), // components/plonk.h:230 +PolyExtStep::Add(10192, 10152), // components/plonk.h:230 +PolyExtStep::Add(10193, 10153), // components/plonk.h:230 +PolyExtStep::Add(10194, 10084), // components/plonk.h:230 +PolyExtStep::Add(10195, 10085), // components/plonk.h:230 +PolyExtStep::Add(10196, 10086), // components/plonk.h:230 +PolyExtStep::Add(10197, 10087), // components/plonk.h:230 +PolyExtStep::Add(10198, 10088), // components/plonk.h:230 +PolyExtStep::Add(10199, 10089), // components/plonk.h:230 +PolyExtStep::Add(10200, 10090), // components/plonk.h:230 +PolyExtStep::Add(10201, 10091), // components/plonk.h:230 +PolyExtStep::Add(10202, 10092), // components/plonk.h:230 +PolyExtStep::Add(10203, 10093), // components/plonk.h:230 +PolyExtStep::Add(10205, 10160), // components/plonk.h:230 +PolyExtStep::Add(10208, 10163), // components/plonk.h:230 +PolyExtStep::Add(10204, 10159), // components/plonk.h:230 +PolyExtStep::Add(10206, 10161), // components/plonk.h:230 +PolyExtStep::Add(10207, 10162), // components/plonk.h:230 +PolyExtStep::Add(10209, 10094), // components/plonk.h:230 +PolyExtStep::Add(10210, 10095), // components/plonk.h:230 +PolyExtStep::Add(10211, 10096), // components/plonk.h:230 +PolyExtStep::Add(10212, 10097), // components/plonk.h:230 +PolyExtStep::Add(10213, 10098), // components/plonk.h:230 +PolyExtStep::Add(10214, 10099), // components/plonk.h:230 +PolyExtStep::Add(10215, 10100), // components/plonk.h:230 +PolyExtStep::Add(10216, 10101), // components/plonk.h:230 +PolyExtStep::Add(10217, 10102), // components/plonk.h:230 +PolyExtStep::Add(10218, 10103), // components/plonk.h:230 +PolyExtStep::Add(10219, 10104), // components/plonk.h:230 +PolyExtStep::Add(10220, 10105), // components/plonk.h:230 +PolyExtStep::Add(10221, 10106), // components/plonk.h:230 +PolyExtStep::Add(10222, 10107), // components/plonk.h:230 +PolyExtStep::Add(10223, 10108), // components/plonk.h:230 +PolyExtStep::Add(10230, 10110), // components/plonk.h:230 +PolyExtStep::Add(10233, 10113), // components/plonk.h:230 +PolyExtStep::Add(10235, 10115), // components/plonk.h:230 +PolyExtStep::Add(10238, 10118), // components/plonk.h:230 +PolyExtStep::Add(10240, 10120), // components/plonk.h:230 +PolyExtStep::Add(10243, 10123), // components/plonk.h:230 +PolyExtStep::Add(10229, 10109), // components/plonk.h:230 +PolyExtStep::Add(10231, 10111), // components/plonk.h:230 +PolyExtStep::Add(10232, 10112), // components/plonk.h:230 +PolyExtStep::Add(10234, 10114), // components/plonk.h:230 +PolyExtStep::Add(10236, 10116), // components/plonk.h:230 +PolyExtStep::Add(10237, 10117), // components/plonk.h:230 +PolyExtStep::Add(10239, 10119), // components/plonk.h:230 +PolyExtStep::Add(10241, 10121), // components/plonk.h:230 +PolyExtStep::Add(10242, 10122), // components/plonk.h:230 +PolyExtStep::Mul(10250, 10248), // components/plonk.h:232 +PolyExtStep::Mul(10252, 10249), // components/plonk.h:232 +PolyExtStep::Mul(10250, 10244), // components/plonk.h:232 +PolyExtStep::Mul(10250, 10246), // components/plonk.h:232 +PolyExtStep::Mul(10250, 10224), // components/plonk.h:232 +PolyExtStep::Mul(10252, 10245), // components/plonk.h:232 +PolyExtStep::Mul(10252, 10247), // components/plonk.h:232 +PolyExtStep::Mul(10252, 10225), // components/plonk.h:232 +PolyExtStep::Mul(10253, 10248), // components/plonk.h:232 +PolyExtStep::Mul(10255, 10249), // components/plonk.h:232 +PolyExtStep::Mul(10256, 10248), // components/plonk.h:232 +PolyExtStep::Mul(10258, 10249), // components/plonk.h:232 +PolyExtStep::Mul(10226, 10244), // components/plonk.h:232 +PolyExtStep::Mul(10226, 10246), // components/plonk.h:232 +PolyExtStep::Mul(10226, 10248), // components/plonk.h:232 +PolyExtStep::Mul(10226, 10224), // components/plonk.h:232 +PolyExtStep::Mul(10228, 10245), // components/plonk.h:232 +PolyExtStep::Mul(10228, 10247), // components/plonk.h:232 +PolyExtStep::Mul(10228, 10249), // components/plonk.h:232 +PolyExtStep::Mul(10228, 10225), // components/plonk.h:232 +PolyExtStep::Mul(10253, 10244), // components/plonk.h:232 +PolyExtStep::Mul(10253, 10246), // components/plonk.h:232 +PolyExtStep::Mul(10253, 10224), // components/plonk.h:232 +PolyExtStep::Mul(10255, 10245), // components/plonk.h:232 +PolyExtStep::Mul(10255, 10247), // components/plonk.h:232 +PolyExtStep::Mul(10255, 10225), // components/plonk.h:232 +PolyExtStep::Mul(10256, 10244), // components/plonk.h:232 +PolyExtStep::Mul(10256, 10246), // components/plonk.h:232 +PolyExtStep::Mul(10256, 10224), // components/plonk.h:232 +PolyExtStep::Mul(10258, 10245), // components/plonk.h:232 +PolyExtStep::Mul(10258, 10247), // components/plonk.h:232 +PolyExtStep::Mul(10258, 10225), // components/plonk.h:232 +PolyExtStep::Mul(10269, 11), // components/plonk.h:232 +PolyExtStep::Mul(10270, 11), // components/plonk.h:232 +PolyExtStep::Add(10267, 10286), // components/plonk.h:232 +PolyExtStep::Add(10268, 10289), // components/plonk.h:232 +PolyExtStep::Add(10259, 10280), // components/plonk.h:232 +PolyExtStep::Add(10260, 10283), // components/plonk.h:232 +PolyExtStep::Add(10271, 10263), // components/plonk.h:232 +PolyExtStep::Add(10272, 10261), // components/plonk.h:232 +PolyExtStep::Add(10273, 10262), // components/plonk.h:232 +PolyExtStep::Add(10275, 10266), // components/plonk.h:232 +PolyExtStep::Add(10276, 10264), // components/plonk.h:232 +PolyExtStep::Add(10277, 10265), // components/plonk.h:232 +PolyExtStep::Mul(10293, 11), // components/plonk.h:232 +PolyExtStep::Mul(10294, 11), // components/plonk.h:232 +PolyExtStep::Add(10295, 10285), // components/plonk.h:232 +PolyExtStep::Add(10296, 10288), // components/plonk.h:232 +PolyExtStep::Add(10298, 10281), // components/plonk.h:232 +PolyExtStep::Add(10299, 10279), // components/plonk.h:232 +PolyExtStep::Add(10301, 10284), // components/plonk.h:232 +PolyExtStep::Add(10302, 10282), // components/plonk.h:232 +PolyExtStep::Add(10297, 10303), // components/plonk.h:232 +PolyExtStep::Add(10307, 10291), // components/plonk.h:232 +PolyExtStep::Add(10308, 10287), // components/plonk.h:232 +PolyExtStep::Add(10309, 10292), // components/plonk.h:232 +PolyExtStep::Add(10310, 10290), // components/plonk.h:232 +PolyExtStep::Add(10300, 10304), // components/plonk.h:232 +PolyExtStep::Mul(10305, 11), // components/plonk.h:232 +PolyExtStep::Mul(10306, 11), // components/plonk.h:232 +PolyExtStep::Add(10274, 10317), // components/plonk.h:232 +PolyExtStep::Add(10278, 10318), // components/plonk.h:232 +PolyExtStep::Mul(9858, 10314), // components/plonk.h:299 +PolyExtStep::Mul(9858, 10315), // components/plonk.h:299 +PolyExtStep::Mul(9858, 10316), // components/plonk.h:299 +PolyExtStep::Mul(9858, 10320), // components/plonk.h:299 +PolyExtStep::Mul(9859, 10315), // components/plonk.h:299 +PolyExtStep::Mul(9860, 10315), // components/plonk.h:299 +PolyExtStep::Mul(9861, 10315), // components/plonk.h:299 +PolyExtStep::Mul(9862, 10311), // components/plonk.h:299 +PolyExtStep::Mul(9862, 10319), // components/plonk.h:299 +PolyExtStep::Mul(9862, 10312), // components/plonk.h:299 +PolyExtStep::Mul(9862, 10313), // components/plonk.h:299 +PolyExtStep::Mul(9863, 10313), // components/plonk.h:299 +PolyExtStep::Mul(9864, 10313), // components/plonk.h:299 +PolyExtStep::Mul(9865, 10313), // components/plonk.h:299 +PolyExtStep::Mul(9859, 10314), // components/plonk.h:299 +PolyExtStep::Mul(9859, 10316), // components/plonk.h:299 +PolyExtStep::Mul(9859, 10320), // components/plonk.h:299 +PolyExtStep::Mul(9860, 10314), // components/plonk.h:299 +PolyExtStep::Mul(9860, 10316), // components/plonk.h:299 +PolyExtStep::Mul(9860, 10320), // components/plonk.h:299 +PolyExtStep::Mul(9861, 10314), // components/plonk.h:299 +PolyExtStep::Mul(9861, 10316), // components/plonk.h:299 +PolyExtStep::Mul(9861, 10320), // components/plonk.h:299 +PolyExtStep::Mul(9863, 10311), // components/plonk.h:299 +PolyExtStep::Mul(9863, 10319), // components/plonk.h:299 +PolyExtStep::Mul(9863, 10312), // components/plonk.h:299 +PolyExtStep::Mul(9864, 10311), // components/plonk.h:299 +PolyExtStep::Mul(9864, 10319), // components/plonk.h:299 +PolyExtStep::Mul(9864, 10312), // components/plonk.h:299 +PolyExtStep::Mul(9865, 10311), // components/plonk.h:299 +PolyExtStep::Mul(9865, 10319), // components/plonk.h:299 +PolyExtStep::Mul(9865, 10312), // components/plonk.h:299 +PolyExtStep::Mul(10327, 11), // components/plonk.h:299 +PolyExtStep::Mul(10334, 11), // components/plonk.h:299 +PolyExtStep::Add(10321, 10336), // components/plonk.h:299 +PolyExtStep::Add(10322, 10335), // components/plonk.h:299 +PolyExtStep::Add(10323, 10337), // components/plonk.h:299 +PolyExtStep::Add(10325, 10338), // components/plonk.h:299 +PolyExtStep::Add(10326, 10341), // components/plonk.h:299 +PolyExtStep::Add(10328, 10345), // components/plonk.h:299 +PolyExtStep::Add(10330, 10344), // components/plonk.h:299 +PolyExtStep::Add(10331, 10346), // components/plonk.h:299 +PolyExtStep::Add(10332, 10349), // components/plonk.h:299 +PolyExtStep::Add(10333, 10352), // components/plonk.h:299 +PolyExtStep::Mul(10359, 11), // components/plonk.h:299 +PolyExtStep::Mul(10364, 11), // components/plonk.h:299 +PolyExtStep::Add(10355, 10340), // components/plonk.h:299 +PolyExtStep::Add(10356, 10339), // components/plonk.h:299 +PolyExtStep::Add(10358, 10342), // components/plonk.h:299 +PolyExtStep::Add(10360, 10366), // components/plonk.h:299 +PolyExtStep::Add(10361, 10348), // components/plonk.h:299 +PolyExtStep::Add(10362, 10347), // components/plonk.h:299 +PolyExtStep::Add(10363, 10350), // components/plonk.h:299 +PolyExtStep::Add(10367, 10353), // components/plonk.h:299 +PolyExtStep::Add(10368, 10343), // components/plonk.h:299 +PolyExtStep::Add(10357, 10365), // components/plonk.h:299 +PolyExtStep::Mul(10369, 11), // components/plonk.h:299 +PolyExtStep::Mul(10373, 11), // components/plonk.h:299 +PolyExtStep::Add(10371, 10354), // components/plonk.h:299 +PolyExtStep::Add(10372, 10351), // components/plonk.h:299 +PolyExtStep::Add(10329, 10378), // components/plonk.h:299 +PolyExtStep::Add(10324, 10377), // components/plonk.h:299 +PolyExtStep::Sub(10381, 10382), // components/plonk.h:299 +PolyExtStep::AndEqz(0, 10383), // components/plonk.h:299 +PolyExtStep::Sub(10370, 10376), // components/plonk.h:299 +PolyExtStep::AndEqz(966, 10384), // components/plonk.h:299 +PolyExtStep::Sub(10379, 10374), // components/plonk.h:299 +PolyExtStep::AndEqz(967, 10385), // components/plonk.h:299 +PolyExtStep::Sub(10380, 10375), // components/plonk.h:299 +PolyExtStep::AndEqz(968, 10386), // components/plonk.h:299 +PolyExtStep::Mul(9858, 10251), // components/plonk.h:299 +PolyExtStep::Mul(9858, 10227), // components/plonk.h:299 +PolyExtStep::Mul(9858, 10254), // components/plonk.h:299 +PolyExtStep::Mul(9858, 10257), // components/plonk.h:299 +PolyExtStep::Mul(9859, 10257), // components/plonk.h:299 +PolyExtStep::Mul(9860, 10257), // components/plonk.h:299 +PolyExtStep::Mul(9861, 10257), // components/plonk.h:299 +PolyExtStep::Mul(9859, 10251), // components/plonk.h:299 +PolyExtStep::Mul(9859, 10227), // components/plonk.h:299 +PolyExtStep::Mul(9859, 10254), // components/plonk.h:299 +PolyExtStep::Mul(9860, 10251), // components/plonk.h:299 +PolyExtStep::Mul(9860, 10227), // components/plonk.h:299 +PolyExtStep::Mul(9860, 10254), // components/plonk.h:299 +PolyExtStep::Mul(9861, 10251), // components/plonk.h:299 +PolyExtStep::Mul(9861, 10227), // components/plonk.h:299 +PolyExtStep::Mul(9861, 10254), // components/plonk.h:299 +PolyExtStep::Mul(10393, 11), // components/plonk.h:299 +PolyExtStep::Add(10387, 10395), // components/plonk.h:299 +PolyExtStep::Add(10389, 10394), // components/plonk.h:299 +PolyExtStep::Add(10390, 10396), // components/plonk.h:299 +PolyExtStep::Add(10391, 10399), // components/plonk.h:299 +PolyExtStep::Add(10392, 10402), // components/plonk.h:299 +PolyExtStep::Mul(10024, 9444), // components/plonk.h:299 +PolyExtStep::Mul(10024, 9456), // components/plonk.h:299 +PolyExtStep::Mul(10024, 9432), // components/plonk.h:299 +PolyExtStep::Mul(10024, 9360), // components/plonk.h:299 +PolyExtStep::Mul(10025, 9456), // components/plonk.h:299 +PolyExtStep::Mul(10026, 9456), // components/plonk.h:299 +PolyExtStep::Mul(10027, 9456), // components/plonk.h:299 +PolyExtStep::Mul(10408, 11), // components/plonk.h:299 +PolyExtStep::Mul(10025, 9444), // components/plonk.h:299 +PolyExtStep::Mul(10025, 9432), // components/plonk.h:299 +PolyExtStep::Mul(10025, 9360), // components/plonk.h:299 +PolyExtStep::Mul(10026, 9444), // components/plonk.h:299 +PolyExtStep::Mul(10026, 9432), // components/plonk.h:299 +PolyExtStep::Mul(10026, 9360), // components/plonk.h:299 +PolyExtStep::Mul(10027, 9444), // components/plonk.h:299 +PolyExtStep::Mul(10027, 9432), // components/plonk.h:299 +PolyExtStep::Mul(10027, 9360), // components/plonk.h:299 +PolyExtStep::Mul(10415, 11), // components/plonk.h:299 +PolyExtStep::Add(10404, 10416), // components/plonk.h:299 +PolyExtStep::Add(10405, 10398), // components/plonk.h:299 +PolyExtStep::Add(10406, 10397), // components/plonk.h:299 +PolyExtStep::Add(10407, 10400), // components/plonk.h:299 +PolyExtStep::Add(10409, 10418), // components/plonk.h:299 +PolyExtStep::Add(10410, 10417), // components/plonk.h:299 +PolyExtStep::Add(10411, 10419), // components/plonk.h:299 +PolyExtStep::Add(10413, 10420), // components/plonk.h:299 +PolyExtStep::Add(10414, 10423), // components/plonk.h:299 +PolyExtStep::Mul(10430, 11), // components/plonk.h:299 +PolyExtStep::Mul(10435, 11), // components/plonk.h:299 +PolyExtStep::Add(10428, 10403), // components/plonk.h:299 +PolyExtStep::Add(10429, 10401), // components/plonk.h:299 +PolyExtStep::Add(10431, 10422), // components/plonk.h:299 +PolyExtStep::Add(10432, 10421), // components/plonk.h:299 +PolyExtStep::Add(10434, 10424), // components/plonk.h:299 +PolyExtStep::Add(10388, 10436), // components/plonk.h:299 +PolyExtStep::Add(10440, 10426), // components/plonk.h:299 +PolyExtStep::Add(10441, 10425), // components/plonk.h:299 +PolyExtStep::Add(10433, 10437), // components/plonk.h:299 +PolyExtStep::Mul(10442, 11), // components/plonk.h:299 +PolyExtStep::Add(10412, 10447), // components/plonk.h:299 +PolyExtStep::Sub(10443, 10448), // components/plonk.h:299 +PolyExtStep::AndEqz(969, 10449), // components/plonk.h:299 +PolyExtStep::Sub(10427, 10446), // components/plonk.h:299 +PolyExtStep::AndEqz(970, 10450), // components/plonk.h:299 +PolyExtStep::Sub(10438, 10444), // components/plonk.h:299 +PolyExtStep::AndEqz(971, 10451), // components/plonk.h:299 +PolyExtStep::Sub(10439, 10445), // components/plonk.h:299 +PolyExtStep::AndEqz(972, 10452), // components/plonk.h:299 +PolyExtStep::AndCond(965, 318, 973), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(974, 475, 973), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Mul(10251, 9456), // components/plonk.h:232 +PolyExtStep::Mul(10251, 9432), // components/plonk.h:232 +PolyExtStep::Mul(10251, 9444), // components/plonk.h:232 +PolyExtStep::Mul(10251, 9360), // components/plonk.h:232 +PolyExtStep::Mul(10254, 9456), // components/plonk.h:232 +PolyExtStep::Mul(10257, 9456), // components/plonk.h:232 +PolyExtStep::Mul(10227, 9432), // components/plonk.h:232 +PolyExtStep::Mul(10227, 9444), // components/plonk.h:232 +PolyExtStep::Mul(10227, 9456), // components/plonk.h:232 +PolyExtStep::Mul(10227, 9360), // components/plonk.h:232 +PolyExtStep::Mul(10254, 9432), // components/plonk.h:232 +PolyExtStep::Mul(10254, 9444), // components/plonk.h:232 +PolyExtStep::Mul(10254, 9360), // components/plonk.h:232 +PolyExtStep::Mul(10257, 9432), // components/plonk.h:232 +PolyExtStep::Mul(10257, 9444), // components/plonk.h:232 +PolyExtStep::Mul(10257, 9360), // components/plonk.h:232 +PolyExtStep::Mul(10458, 11), // components/plonk.h:232 +PolyExtStep::Add(10457, 10467), // components/plonk.h:232 +PolyExtStep::Add(10453, 10464), // components/plonk.h:232 +PolyExtStep::Add(10459, 10456), // components/plonk.h:232 +PolyExtStep::Add(10460, 10454), // components/plonk.h:232 +PolyExtStep::Add(10461, 10455), // components/plonk.h:232 +PolyExtStep::Mul(10470, 11), // components/plonk.h:232 +PolyExtStep::Add(10471, 10466), // components/plonk.h:232 +PolyExtStep::Add(10473, 10465), // components/plonk.h:232 +PolyExtStep::Add(10474, 10463), // components/plonk.h:232 +PolyExtStep::Add(10477, 10469), // components/plonk.h:232 +PolyExtStep::Add(10478, 10468), // components/plonk.h:232 +PolyExtStep::Add(10472, 10475), // components/plonk.h:232 +PolyExtStep::Mul(10476, 11), // components/plonk.h:232 +PolyExtStep::Add(10462, 10482), // components/plonk.h:232 +PolyExtStep::Mul(10024, 10479), // components/plonk.h:299 +PolyExtStep::Mul(10024, 10480), // components/plonk.h:299 +PolyExtStep::Mul(10024, 10481), // components/plonk.h:299 +PolyExtStep::Mul(10024, 10483), // components/plonk.h:299 +PolyExtStep::Mul(10025, 10480), // components/plonk.h:299 +PolyExtStep::Mul(10026, 10480), // components/plonk.h:299 +PolyExtStep::Mul(10027, 10480), // components/plonk.h:299 +PolyExtStep::Mul(10025, 10479), // components/plonk.h:299 +PolyExtStep::Mul(10025, 10481), // components/plonk.h:299 +PolyExtStep::Mul(10025, 10483), // components/plonk.h:299 +PolyExtStep::Mul(10026, 10479), // components/plonk.h:299 +PolyExtStep::Mul(10026, 10481), // components/plonk.h:299 +PolyExtStep::Mul(10026, 10483), // components/plonk.h:299 +PolyExtStep::Mul(10027, 10479), // components/plonk.h:299 +PolyExtStep::Mul(10027, 10481), // components/plonk.h:299 +PolyExtStep::Mul(10027, 10483), // components/plonk.h:299 +PolyExtStep::Mul(10490, 11), // components/plonk.h:299 +PolyExtStep::Add(10484, 10492), // components/plonk.h:299 +PolyExtStep::Add(10485, 10491), // components/plonk.h:299 +PolyExtStep::Add(10486, 10493), // components/plonk.h:299 +PolyExtStep::Add(10488, 10494), // components/plonk.h:299 +PolyExtStep::Add(10489, 10497), // components/plonk.h:299 +PolyExtStep::Mul(10505, 11), // components/plonk.h:299 +PolyExtStep::Add(10501, 10496), // components/plonk.h:299 +PolyExtStep::Add(10502, 10495), // components/plonk.h:299 +PolyExtStep::Add(10504, 10498), // components/plonk.h:299 +PolyExtStep::Add(10507, 10500), // components/plonk.h:299 +PolyExtStep::Add(10508, 10499), // components/plonk.h:299 +PolyExtStep::Add(10503, 10506), // components/plonk.h:299 +PolyExtStep::Mul(10509, 11), // components/plonk.h:299 +PolyExtStep::Add(10487, 10513), // components/plonk.h:299 +PolyExtStep::Sub(10381, 10514), // components/plonk.h:299 +PolyExtStep::AndEqz(0, 10515), // components/plonk.h:299 +PolyExtStep::Sub(10370, 10512), // components/plonk.h:299 +PolyExtStep::AndEqz(976, 10516), // components/plonk.h:299 +PolyExtStep::Sub(10379, 10510), // components/plonk.h:299 +PolyExtStep::AndEqz(977, 10517), // components/plonk.h:299 +PolyExtStep::Sub(10380, 10511), // components/plonk.h:299 +PolyExtStep::AndEqz(978, 10518), // components/plonk.h:299 +PolyExtStep::AndCond(975, 506, 979), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(980, 508, 979), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(981, 507, 979), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(982, 664, 979), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Mul(9434, 9480), // components/plonk.h:232 +PolyExtStep::Mul(9435, 9460), // components/plonk.h:232 +PolyExtStep::Mul(9438, 9456), // components/plonk.h:232 +PolyExtStep::Mul(9434, 9468), // components/plonk.h:232 +PolyExtStep::Mul(9434, 9474), // components/plonk.h:232 +PolyExtStep::Mul(9434, 9372), // components/plonk.h:232 +PolyExtStep::Mul(9435, 9436), // components/plonk.h:232 +PolyExtStep::Mul(9435, 9448), // components/plonk.h:232 +PolyExtStep::Mul(9435, 9364), // components/plonk.h:232 +PolyExtStep::Mul(9438, 9432), // components/plonk.h:232 +PolyExtStep::Mul(9438, 9444), // components/plonk.h:232 +PolyExtStep::Mul(9438, 9360), // components/plonk.h:232 +PolyExtStep::Mul(9446, 9480), // components/plonk.h:232 +PolyExtStep::Mul(9447, 9460), // components/plonk.h:232 +PolyExtStep::Mul(9450, 9456), // components/plonk.h:232 +PolyExtStep::Mul(9458, 9480), // components/plonk.h:232 +PolyExtStep::Mul(9459, 9460), // components/plonk.h:232 +PolyExtStep::Mul(9462, 9456), // components/plonk.h:232 +PolyExtStep::Mul(9362, 9468), // components/plonk.h:232 +PolyExtStep::Mul(9362, 9474), // components/plonk.h:232 +PolyExtStep::Mul(9362, 9480), // components/plonk.h:232 +PolyExtStep::Mul(9362, 9372), // components/plonk.h:232 +PolyExtStep::Mul(9363, 9436), // components/plonk.h:232 +PolyExtStep::Mul(9363, 9448), // components/plonk.h:232 +PolyExtStep::Mul(9363, 9460), // components/plonk.h:232 +PolyExtStep::Mul(9363, 9364), // components/plonk.h:232 +PolyExtStep::Mul(9366, 9432), // components/plonk.h:232 +PolyExtStep::Mul(9366, 9444), // components/plonk.h:232 +PolyExtStep::Mul(9366, 9456), // components/plonk.h:232 +PolyExtStep::Mul(9366, 9360), // components/plonk.h:232 +PolyExtStep::Mul(9446, 9468), // components/plonk.h:232 +PolyExtStep::Mul(9446, 9474), // components/plonk.h:232 +PolyExtStep::Mul(9446, 9372), // components/plonk.h:232 +PolyExtStep::Mul(9447, 9436), // components/plonk.h:232 +PolyExtStep::Mul(9447, 9448), // components/plonk.h:232 +PolyExtStep::Mul(9447, 9364), // components/plonk.h:232 +PolyExtStep::Mul(9450, 9432), // components/plonk.h:232 +PolyExtStep::Mul(9450, 9444), // components/plonk.h:232 +PolyExtStep::Mul(9450, 9360), // components/plonk.h:232 +PolyExtStep::Mul(9458, 9468), // components/plonk.h:232 +PolyExtStep::Mul(9458, 9474), // components/plonk.h:232 +PolyExtStep::Mul(9458, 9372), // components/plonk.h:232 +PolyExtStep::Mul(9459, 9436), // components/plonk.h:232 +PolyExtStep::Mul(9459, 9448), // components/plonk.h:232 +PolyExtStep::Mul(9459, 9364), // components/plonk.h:232 +PolyExtStep::Mul(9462, 9432), // components/plonk.h:232 +PolyExtStep::Mul(9462, 9444), // components/plonk.h:232 +PolyExtStep::Mul(9462, 9360), // components/plonk.h:232 +PolyExtStep::Mul(10534, 11), // components/plonk.h:232 +PolyExtStep::Mul(10535, 11), // components/plonk.h:232 +PolyExtStep::Mul(10536, 11), // components/plonk.h:232 +PolyExtStep::Add(10531, 10559), // components/plonk.h:232 +PolyExtStep::Add(10532, 10562), // components/plonk.h:232 +PolyExtStep::Add(10533, 10565), // components/plonk.h:232 +PolyExtStep::Add(10519, 10550), // components/plonk.h:232 +PolyExtStep::Add(10520, 10553), // components/plonk.h:232 +PolyExtStep::Add(10521, 10556), // components/plonk.h:232 +PolyExtStep::Add(10537, 10524), // components/plonk.h:232 +PolyExtStep::Add(10538, 10522), // components/plonk.h:232 +PolyExtStep::Add(10539, 10523), // components/plonk.h:232 +PolyExtStep::Add(10541, 10527), // components/plonk.h:232 +PolyExtStep::Add(10542, 10525), // components/plonk.h:232 +PolyExtStep::Add(10543, 10526), // components/plonk.h:232 +PolyExtStep::Add(10545, 10530), // components/plonk.h:232 +PolyExtStep::Add(10546, 10528), // components/plonk.h:232 +PolyExtStep::Add(10547, 10529), // components/plonk.h:232 +PolyExtStep::Mul(10570, 11), // components/plonk.h:232 +PolyExtStep::Mul(10571, 11), // components/plonk.h:232 +PolyExtStep::Mul(10572, 11), // components/plonk.h:232 +PolyExtStep::Add(10573, 10558), // components/plonk.h:232 +PolyExtStep::Add(10574, 10561), // components/plonk.h:232 +PolyExtStep::Add(10575, 10564), // components/plonk.h:232 +PolyExtStep::Add(10577, 10551), // components/plonk.h:232 +PolyExtStep::Add(10578, 10549), // components/plonk.h:232 +PolyExtStep::Add(10580, 10554), // components/plonk.h:232 +PolyExtStep::Add(10581, 10552), // components/plonk.h:232 +PolyExtStep::Add(10583, 10557), // components/plonk.h:232 +PolyExtStep::Add(10584, 10555), // components/plonk.h:232 +PolyExtStep::Add(10576, 10585), // components/plonk.h:232 +PolyExtStep::Add(10579, 10586), // components/plonk.h:232 +PolyExtStep::Add(10591, 10567), // components/plonk.h:232 +PolyExtStep::Add(10592, 10560), // components/plonk.h:232 +PolyExtStep::Add(10593, 10568), // components/plonk.h:232 +PolyExtStep::Add(10594, 10563), // components/plonk.h:232 +PolyExtStep::Add(10595, 10569), // components/plonk.h:232 +PolyExtStep::Add(10596, 10566), // components/plonk.h:232 +PolyExtStep::Add(10582, 10587), // components/plonk.h:232 +PolyExtStep::Mul(10588, 11), // components/plonk.h:232 +PolyExtStep::Mul(10589, 11), // components/plonk.h:232 +PolyExtStep::Mul(10590, 11), // components/plonk.h:232 +PolyExtStep::Add(10540, 10606), // components/plonk.h:232 +PolyExtStep::Add(10544, 10607), // components/plonk.h:232 +PolyExtStep::Add(10548, 10608), // components/plonk.h:232 +PolyExtStep::Mul(9858, 9680), // components/plonk.h:299 +PolyExtStep::Mul(9858, 9681), // components/plonk.h:299 +PolyExtStep::Mul(9858, 9633), // components/plonk.h:299 +PolyExtStep::Mul(9858, 9691), // components/plonk.h:299 +PolyExtStep::Mul(9859, 9681), // components/plonk.h:299 +PolyExtStep::Mul(9860, 9681), // components/plonk.h:299 +PolyExtStep::Mul(9861, 9681), // components/plonk.h:299 +PolyExtStep::Mul(9862, 10597), // components/plonk.h:299 +PolyExtStep::Mul(9862, 10609), // components/plonk.h:299 +PolyExtStep::Mul(9862, 10599), // components/plonk.h:299 +PolyExtStep::Mul(9862, 10600), // components/plonk.h:299 +PolyExtStep::Mul(9863, 10600), // components/plonk.h:299 +PolyExtStep::Mul(9864, 10600), // components/plonk.h:299 +PolyExtStep::Mul(9865, 10600), // components/plonk.h:299 +PolyExtStep::Mul(9859, 9680), // components/plonk.h:299 +PolyExtStep::Mul(9859, 9633), // components/plonk.h:299 +PolyExtStep::Mul(9859, 9691), // components/plonk.h:299 +PolyExtStep::Mul(9860, 9680), // components/plonk.h:299 +PolyExtStep::Mul(9860, 9633), // components/plonk.h:299 +PolyExtStep::Mul(9860, 9691), // components/plonk.h:299 +PolyExtStep::Mul(9861, 9680), // components/plonk.h:299 +PolyExtStep::Mul(9861, 9633), // components/plonk.h:299 +PolyExtStep::Mul(9861, 9691), // components/plonk.h:299 +PolyExtStep::Mul(9863, 10597), // components/plonk.h:299 +PolyExtStep::Mul(9863, 10609), // components/plonk.h:299 +PolyExtStep::Mul(9863, 10599), // components/plonk.h:299 +PolyExtStep::Mul(9864, 10597), // components/plonk.h:299 +PolyExtStep::Mul(9864, 10609), // components/plonk.h:299 +PolyExtStep::Mul(9864, 10599), // components/plonk.h:299 +PolyExtStep::Mul(9865, 10597), // components/plonk.h:299 +PolyExtStep::Mul(9865, 10609), // components/plonk.h:299 +PolyExtStep::Mul(9865, 10599), // components/plonk.h:299 +PolyExtStep::Mul(10618, 11), // components/plonk.h:299 +PolyExtStep::Mul(10625, 11), // components/plonk.h:299 +PolyExtStep::Add(10612, 10627), // components/plonk.h:299 +PolyExtStep::Add(10613, 10626), // components/plonk.h:299 +PolyExtStep::Add(10614, 10628), // components/plonk.h:299 +PolyExtStep::Add(10616, 10629), // components/plonk.h:299 +PolyExtStep::Add(10617, 10632), // components/plonk.h:299 +PolyExtStep::Add(10619, 10636), // components/plonk.h:299 +PolyExtStep::Add(10621, 10635), // components/plonk.h:299 +PolyExtStep::Add(10622, 10637), // components/plonk.h:299 +PolyExtStep::Add(10623, 10640), // components/plonk.h:299 +PolyExtStep::Add(10624, 10643), // components/plonk.h:299 +PolyExtStep::Mul(10650, 11), // components/plonk.h:299 +PolyExtStep::Mul(10655, 11), // components/plonk.h:299 +PolyExtStep::Add(10646, 10631), // components/plonk.h:299 +PolyExtStep::Add(10647, 10630), // components/plonk.h:299 +PolyExtStep::Add(10649, 10633), // components/plonk.h:299 +PolyExtStep::Add(10651, 10657), // components/plonk.h:299 +PolyExtStep::Add(10652, 10639), // components/plonk.h:299 +PolyExtStep::Add(10653, 10638), // components/plonk.h:299 +PolyExtStep::Add(10654, 10641), // components/plonk.h:299 +PolyExtStep::Add(10658, 10644), // components/plonk.h:299 +PolyExtStep::Add(10659, 10634), // components/plonk.h:299 +PolyExtStep::Add(10648, 10656), // components/plonk.h:299 +PolyExtStep::Mul(10660, 11), // components/plonk.h:299 +PolyExtStep::Mul(10664, 11), // components/plonk.h:299 +PolyExtStep::Add(10662, 10645), // components/plonk.h:299 +PolyExtStep::Add(10663, 10642), // components/plonk.h:299 +PolyExtStep::Add(10620, 10669), // components/plonk.h:299 +PolyExtStep::Add(10615, 10668), // components/plonk.h:299 +PolyExtStep::Sub(10672, 10673), // components/plonk.h:299 +PolyExtStep::AndEqz(0, 10674), // components/plonk.h:299 +PolyExtStep::Sub(10661, 10667), // components/plonk.h:299 +PolyExtStep::AndEqz(984, 10675), // components/plonk.h:299 +PolyExtStep::Sub(10670, 10665), // components/plonk.h:299 +PolyExtStep::AndEqz(985, 10676), // components/plonk.h:299 +PolyExtStep::Sub(10671, 10666), // components/plonk.h:299 +PolyExtStep::AndEqz(986, 10677), // components/plonk.h:299 +PolyExtStep::Mul(9858, 10598), // components/plonk.h:299 +PolyExtStep::Mul(9858, 10610), // components/plonk.h:299 +PolyExtStep::Mul(9858, 10601), // components/plonk.h:299 +PolyExtStep::Mul(9858, 10602), // components/plonk.h:299 +PolyExtStep::Mul(9859, 10602), // components/plonk.h:299 +PolyExtStep::Mul(9860, 10602), // components/plonk.h:299 +PolyExtStep::Mul(9861, 10602), // components/plonk.h:299 +PolyExtStep::Mul(9859, 10598), // components/plonk.h:299 +PolyExtStep::Mul(9859, 10610), // components/plonk.h:299 +PolyExtStep::Mul(9859, 10601), // components/plonk.h:299 +PolyExtStep::Mul(9860, 10598), // components/plonk.h:299 +PolyExtStep::Mul(9860, 10610), // components/plonk.h:299 +PolyExtStep::Mul(9860, 10601), // components/plonk.h:299 +PolyExtStep::Mul(9861, 10598), // components/plonk.h:299 +PolyExtStep::Mul(9861, 10610), // components/plonk.h:299 +PolyExtStep::Mul(9861, 10601), // components/plonk.h:299 +PolyExtStep::Mul(10684, 11), // components/plonk.h:299 +PolyExtStep::Add(10678, 10686), // components/plonk.h:299 +PolyExtStep::Add(10680, 10685), // components/plonk.h:299 +PolyExtStep::Add(10681, 10687), // components/plonk.h:299 +PolyExtStep::Add(10682, 10690), // components/plonk.h:299 +PolyExtStep::Add(10683, 10693), // components/plonk.h:299 +PolyExtStep::Mul(10024, 10603), // components/plonk.h:299 +PolyExtStep::Mul(10024, 10604), // components/plonk.h:299 +PolyExtStep::Mul(10024, 10605), // components/plonk.h:299 +PolyExtStep::Mul(10024, 10611), // components/plonk.h:299 +PolyExtStep::Mul(10025, 10604), // components/plonk.h:299 +PolyExtStep::Mul(10026, 10604), // components/plonk.h:299 +PolyExtStep::Mul(10027, 10604), // components/plonk.h:299 +PolyExtStep::Mul(10699, 11), // components/plonk.h:299 +PolyExtStep::Mul(10025, 10603), // components/plonk.h:299 +PolyExtStep::Mul(10025, 10605), // components/plonk.h:299 +PolyExtStep::Mul(10025, 10611), // components/plonk.h:299 +PolyExtStep::Mul(10026, 10603), // components/plonk.h:299 +PolyExtStep::Mul(10026, 10605), // components/plonk.h:299 +PolyExtStep::Mul(10026, 10611), // components/plonk.h:299 +PolyExtStep::Mul(10027, 10603), // components/plonk.h:299 +PolyExtStep::Mul(10027, 10605), // components/plonk.h:299 +PolyExtStep::Mul(10027, 10611), // components/plonk.h:299 +PolyExtStep::Mul(10706, 11), // components/plonk.h:299 +PolyExtStep::Add(10695, 10707), // components/plonk.h:299 +PolyExtStep::Add(10696, 10689), // components/plonk.h:299 +PolyExtStep::Add(10697, 10688), // components/plonk.h:299 +PolyExtStep::Add(10698, 10691), // components/plonk.h:299 +PolyExtStep::Add(10700, 10709), // components/plonk.h:299 +PolyExtStep::Add(10701, 10708), // components/plonk.h:299 +PolyExtStep::Add(10702, 10710), // components/plonk.h:299 +PolyExtStep::Add(10704, 10711), // components/plonk.h:299 +PolyExtStep::Add(10705, 10714), // components/plonk.h:299 +PolyExtStep::Mul(10721, 11), // components/plonk.h:299 +PolyExtStep::Mul(10726, 11), // components/plonk.h:299 +PolyExtStep::Add(10719, 10694), // components/plonk.h:299 +PolyExtStep::Add(10720, 10692), // components/plonk.h:299 +PolyExtStep::Add(10722, 10713), // components/plonk.h:299 +PolyExtStep::Add(10723, 10712), // components/plonk.h:299 +PolyExtStep::Add(10725, 10715), // components/plonk.h:299 +PolyExtStep::Add(10679, 10727), // components/plonk.h:299 +PolyExtStep::Add(10731, 10717), // components/plonk.h:299 +PolyExtStep::Add(10732, 10716), // components/plonk.h:299 +PolyExtStep::Add(10724, 10728), // components/plonk.h:299 +PolyExtStep::Mul(10733, 11), // components/plonk.h:299 +PolyExtStep::Add(10703, 10738), // components/plonk.h:299 +PolyExtStep::Sub(10734, 10739), // components/plonk.h:299 +PolyExtStep::AndEqz(987, 10740), // components/plonk.h:299 +PolyExtStep::Sub(10718, 10737), // components/plonk.h:299 +PolyExtStep::AndEqz(988, 10741), // components/plonk.h:299 +PolyExtStep::Sub(10729, 10735), // components/plonk.h:299 +PolyExtStep::AndEqz(989, 10742), // components/plonk.h:299 +PolyExtStep::Sub(10730, 10736), // components/plonk.h:299 +PolyExtStep::AndEqz(990, 10743), // components/plonk.h:299 +PolyExtStep::AndCond(983, 695, 991), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(955, 852, 992), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(993, 4415, 954), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Sub(10024, 9862), // components/plonk.h:113 +PolyExtStep::AndEqz(0, 10744), // components/plonk.h:113 +PolyExtStep::Sub(10025, 9863), // components/plonk.h:113 +PolyExtStep::AndEqz(995, 10745), // components/plonk.h:113 +PolyExtStep::Sub(10026, 9864), // components/plonk.h:113 +PolyExtStep::AndEqz(996, 10746), // components/plonk.h:113 +PolyExtStep::Sub(10027, 9865), // components/plonk.h:113 +PolyExtStep::AndEqz(997, 10747), // components/plonk.h:113 +PolyExtStep::AndCond(994, 4796, 998), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(999, 5627, 998), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(1000, 7315, 954), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Mul(9434, 9456), // components/plonk.h:232 +PolyExtStep::Mul(9434, 9432), // components/plonk.h:232 +PolyExtStep::Mul(9434, 9444), // components/plonk.h:232 +PolyExtStep::Mul(9434, 9360), // components/plonk.h:232 +PolyExtStep::Mul(9446, 9456), // components/plonk.h:232 +PolyExtStep::Mul(9458, 9456), // components/plonk.h:232 +PolyExtStep::Mul(9362, 9432), // components/plonk.h:232 +PolyExtStep::Mul(9362, 9444), // components/plonk.h:232 +PolyExtStep::Mul(9362, 9456), // components/plonk.h:232 +PolyExtStep::Mul(9362, 9360), // components/plonk.h:232 +PolyExtStep::Mul(9446, 9432), // components/plonk.h:232 +PolyExtStep::Mul(9446, 9444), // components/plonk.h:232 +PolyExtStep::Mul(9446, 9360), // components/plonk.h:232 +PolyExtStep::Mul(9458, 9432), // components/plonk.h:232 +PolyExtStep::Mul(9458, 9444), // components/plonk.h:232 +PolyExtStep::Mul(9458, 9360), // components/plonk.h:232 +PolyExtStep::Mul(10753, 11), // components/plonk.h:232 +PolyExtStep::Add(10752, 10762), // components/plonk.h:232 +PolyExtStep::Add(10748, 10759), // components/plonk.h:232 +PolyExtStep::Add(10754, 10751), // components/plonk.h:232 +PolyExtStep::Add(10755, 10749), // components/plonk.h:232 +PolyExtStep::Add(10756, 10750), // components/plonk.h:232 +PolyExtStep::Mul(10765, 11), // components/plonk.h:232 +PolyExtStep::Add(10766, 10761), // components/plonk.h:232 +PolyExtStep::Add(10768, 10760), // components/plonk.h:232 +PolyExtStep::Add(10769, 10758), // components/plonk.h:232 +PolyExtStep::Add(10772, 10764), // components/plonk.h:232 +PolyExtStep::Add(10773, 10763), // components/plonk.h:232 +PolyExtStep::Add(10767, 10770), // components/plonk.h:232 +PolyExtStep::Mul(10771, 11), // components/plonk.h:232 +PolyExtStep::Add(10757, 10777), // components/plonk.h:232 +PolyExtStep::Mul(10024, 10774), // components/plonk.h:299 +PolyExtStep::Mul(10024, 10775), // components/plonk.h:299 +PolyExtStep::Mul(10024, 10776), // components/plonk.h:299 +PolyExtStep::Mul(10024, 10778), // components/plonk.h:299 +PolyExtStep::Mul(10025, 10775), // components/plonk.h:299 +PolyExtStep::Mul(10026, 10775), // components/plonk.h:299 +PolyExtStep::Mul(10027, 10775), // components/plonk.h:299 +PolyExtStep::Mul(9862, 9636), // components/plonk.h:299 +PolyExtStep::Mul(9862, 9692), // components/plonk.h:299 +PolyExtStep::Mul(9862, 9682), // components/plonk.h:299 +PolyExtStep::Mul(9862, 9683), // components/plonk.h:299 +PolyExtStep::Mul(9863, 9683), // components/plonk.h:299 +PolyExtStep::Mul(9864, 9683), // components/plonk.h:299 +PolyExtStep::Mul(9865, 9683), // components/plonk.h:299 +PolyExtStep::Mul(10025, 10774), // components/plonk.h:299 +PolyExtStep::Mul(10025, 10776), // components/plonk.h:299 +PolyExtStep::Mul(10025, 10778), // components/plonk.h:299 +PolyExtStep::Mul(10026, 10774), // components/plonk.h:299 +PolyExtStep::Mul(10026, 10776), // components/plonk.h:299 +PolyExtStep::Mul(10026, 10778), // components/plonk.h:299 +PolyExtStep::Mul(10027, 10774), // components/plonk.h:299 +PolyExtStep::Mul(10027, 10776), // components/plonk.h:299 +PolyExtStep::Mul(10027, 10778), // components/plonk.h:299 +PolyExtStep::Mul(9863, 9636), // components/plonk.h:299 +PolyExtStep::Mul(9863, 9692), // components/plonk.h:299 +PolyExtStep::Mul(9863, 9682), // components/plonk.h:299 +PolyExtStep::Mul(9864, 9636), // components/plonk.h:299 +PolyExtStep::Mul(9864, 9692), // components/plonk.h:299 +PolyExtStep::Mul(9864, 9682), // components/plonk.h:299 +PolyExtStep::Mul(9865, 9636), // components/plonk.h:299 +PolyExtStep::Mul(9865, 9692), // components/plonk.h:299 +PolyExtStep::Mul(9865, 9682), // components/plonk.h:299 +PolyExtStep::Mul(10785, 11), // components/plonk.h:299 +PolyExtStep::Mul(10792, 11), // components/plonk.h:299 +PolyExtStep::Add(10779, 10794), // components/plonk.h:299 +PolyExtStep::Add(10780, 10793), // components/plonk.h:299 +PolyExtStep::Add(10781, 10795), // components/plonk.h:299 +PolyExtStep::Add(10783, 10796), // components/plonk.h:299 +PolyExtStep::Add(10784, 10799), // components/plonk.h:299 +PolyExtStep::Add(10786, 10803), // components/plonk.h:299 +PolyExtStep::Add(10788, 10802), // components/plonk.h:299 +PolyExtStep::Add(10789, 10804), // components/plonk.h:299 +PolyExtStep::Add(10790, 10807), // components/plonk.h:299 +PolyExtStep::Add(10791, 10810), // components/plonk.h:299 +PolyExtStep::Mul(10817, 11), // components/plonk.h:299 +PolyExtStep::Mul(10822, 11), // components/plonk.h:299 +PolyExtStep::Add(10813, 10798), // components/plonk.h:299 +PolyExtStep::Add(10814, 10797), // components/plonk.h:299 +PolyExtStep::Add(10816, 10800), // components/plonk.h:299 +PolyExtStep::Add(10818, 10824), // components/plonk.h:299 +PolyExtStep::Add(10819, 10806), // components/plonk.h:299 +PolyExtStep::Add(10820, 10805), // components/plonk.h:299 +PolyExtStep::Add(10821, 10808), // components/plonk.h:299 +PolyExtStep::Add(10825, 10811), // components/plonk.h:299 +PolyExtStep::Add(10826, 10801), // components/plonk.h:299 +PolyExtStep::Add(10815, 10823), // components/plonk.h:299 +PolyExtStep::Mul(10827, 11), // components/plonk.h:299 +PolyExtStep::Mul(10831, 11), // components/plonk.h:299 +PolyExtStep::Add(10829, 10812), // components/plonk.h:299 +PolyExtStep::Add(10830, 10809), // components/plonk.h:299 +PolyExtStep::Add(10787, 10836), // components/plonk.h:299 +PolyExtStep::Add(10782, 10835), // components/plonk.h:299 +PolyExtStep::Sub(10839, 10840), // components/plonk.h:299 +PolyExtStep::AndEqz(0, 10841), // components/plonk.h:299 +PolyExtStep::Sub(10828, 10834), // components/plonk.h:299 +PolyExtStep::AndEqz(1002, 10842), // components/plonk.h:299 +PolyExtStep::Sub(10837, 10832), // components/plonk.h:299 +PolyExtStep::AndEqz(1003, 10843), // components/plonk.h:299 +PolyExtStep::Sub(10838, 10833), // components/plonk.h:299 +PolyExtStep::AndEqz(1004, 10844), // components/plonk.h:299 +PolyExtStep::AndCond(1001, 7411, 1005), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Sub(1, 475), // components/onehot.h:38 +PolyExtStep::Mul(475, 10845), // components/onehot.h:38 +PolyExtStep::AndEqz(0, 10846), // components/onehot.h:38 +PolyExtStep::Sub(1, 506), // components/onehot.h:38 +PolyExtStep::Mul(506, 10847), // components/onehot.h:38 +PolyExtStep::AndEqz(1007, 10848), // components/onehot.h:38 +PolyExtStep::Add(475, 506), // components/onehot.h:39 +PolyExtStep::Mul(508, 617), // components/onehot.h:38 +PolyExtStep::AndEqz(1008, 10850), // components/onehot.h:38 +PolyExtStep::Add(10849, 508), // components/onehot.h:39 +PolyExtStep::Sub(10851, 1), // components/onehot.h:41 +PolyExtStep::AndEqz(1009, 10852), // components/onehot.h:41 +PolyExtStep::AndCond(1006, 4415, 1010), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(1011, 7315, 1010), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Sub(1, 316), // components/onehot.h:38 +PolyExtStep::Mul(316, 10853), // components/onehot.h:38 +PolyExtStep::AndEqz(0, 10854), // components/onehot.h:38 +PolyExtStep::Sub(1, 288), // components/onehot.h:38 +PolyExtStep::Mul(288, 10855), // components/onehot.h:38 +PolyExtStep::AndEqz(1013, 10856), // components/onehot.h:38 +PolyExtStep::Sub(1, 289), // components/onehot.h:38 +PolyExtStep::Add(316, 288), // components/onehot.h:39 +PolyExtStep::Mul(289, 10857), // components/onehot.h:38 +PolyExtStep::AndEqz(1014, 10859), // components/onehot.h:38 +PolyExtStep::Sub(1, 290), // components/onehot.h:38 +PolyExtStep::Add(10858, 289), // components/onehot.h:39 +PolyExtStep::Mul(290, 10860), // components/onehot.h:38 +PolyExtStep::AndEqz(1015, 10862), // components/onehot.h:38 +PolyExtStep::Sub(1, 291), // components/onehot.h:38 +PolyExtStep::Add(10861, 290), // components/onehot.h:39 +PolyExtStep::Mul(291, 10863), // components/onehot.h:38 +PolyExtStep::AndEqz(1016, 10865), // components/onehot.h:38 +PolyExtStep::Sub(1, 292), // components/onehot.h:38 +PolyExtStep::Add(10864, 291), // components/onehot.h:39 +PolyExtStep::Mul(292, 10866), // components/onehot.h:38 +PolyExtStep::AndEqz(1017, 10868), // components/onehot.h:38 +PolyExtStep::Sub(1, 293), // components/onehot.h:38 +PolyExtStep::Add(10867, 292), // components/onehot.h:39 +PolyExtStep::Mul(293, 10869), // components/onehot.h:38 +PolyExtStep::AndEqz(1018, 10871), // components/onehot.h:38 +PolyExtStep::Sub(1, 294), // components/onehot.h:38 +PolyExtStep::Add(10870, 293), // components/onehot.h:39 +PolyExtStep::Mul(294, 10872), // components/onehot.h:38 +PolyExtStep::AndEqz(1019, 10874), // components/onehot.h:38 +PolyExtStep::Sub(1, 295), // components/onehot.h:38 +PolyExtStep::Add(10873, 294), // components/onehot.h:39 +PolyExtStep::Mul(295, 10875), // components/onehot.h:38 +PolyExtStep::AndEqz(1020, 10877), // components/onehot.h:38 +PolyExtStep::Sub(1, 296), // components/onehot.h:38 +PolyExtStep::Add(10876, 295), // components/onehot.h:39 +PolyExtStep::Mul(296, 10878), // components/onehot.h:38 +PolyExtStep::AndEqz(1021, 10880), // components/onehot.h:38 +PolyExtStep::Sub(1, 287), // components/onehot.h:38 +PolyExtStep::Add(10879, 296), // components/onehot.h:39 +PolyExtStep::Mul(287, 10881), // components/onehot.h:38 +PolyExtStep::AndEqz(1022, 10883), // components/onehot.h:38 +PolyExtStep::Add(10882, 287), // components/onehot.h:39 +PolyExtStep::Sub(10884, 1), // components/onehot.h:41 +PolyExtStep::AndEqz(1023, 10885), // components/onehot.h:41 +PolyExtStep::Sub(1, 505), // components/onehot.h:38 +PolyExtStep::Mul(505, 10886), // components/onehot.h:38 +PolyExtStep::AndEqz(1024, 10887), // components/onehot.h:38 +PolyExtStep::Sub(1, 476), // components/onehot.h:38 +PolyExtStep::Mul(476, 10888), // components/onehot.h:38 +PolyExtStep::AndEqz(1025, 10889), // components/onehot.h:38 +PolyExtStep::Sub(1, 477), // components/onehot.h:38 +PolyExtStep::Add(505, 476), // components/onehot.h:39 +PolyExtStep::Mul(477, 10890), // components/onehot.h:38 +PolyExtStep::AndEqz(1026, 10892), // components/onehot.h:38 +PolyExtStep::Sub(1, 478), // components/onehot.h:38 +PolyExtStep::Add(10891, 477), // components/onehot.h:39 +PolyExtStep::Mul(478, 10893), // components/onehot.h:38 +PolyExtStep::AndEqz(1027, 10895), // components/onehot.h:38 +PolyExtStep::Sub(1, 479), // components/onehot.h:38 +PolyExtStep::Add(10894, 478), // components/onehot.h:39 +PolyExtStep::Mul(479, 10896), // components/onehot.h:38 +PolyExtStep::AndEqz(1028, 10898), // components/onehot.h:38 +PolyExtStep::Sub(1, 480), // components/onehot.h:38 +PolyExtStep::Add(10897, 479), // components/onehot.h:39 +PolyExtStep::Mul(480, 10899), // components/onehot.h:38 +PolyExtStep::AndEqz(1029, 10901), // components/onehot.h:38 +PolyExtStep::Sub(1, 481), // components/onehot.h:38 +PolyExtStep::Add(10900, 480), // components/onehot.h:39 +PolyExtStep::Mul(481, 10902), // components/onehot.h:38 +PolyExtStep::AndEqz(1030, 10904), // components/onehot.h:38 +PolyExtStep::Sub(1, 482), // components/onehot.h:38 +PolyExtStep::Add(10903, 481), // components/onehot.h:39 +PolyExtStep::Mul(482, 10905), // components/onehot.h:38 +PolyExtStep::AndEqz(1031, 10907), // components/onehot.h:38 +PolyExtStep::Sub(1, 483), // components/onehot.h:38 +PolyExtStep::Add(10906, 482), // components/onehot.h:39 +PolyExtStep::Mul(483, 10908), // components/onehot.h:38 +PolyExtStep::AndEqz(1032, 10910), // components/onehot.h:38 +PolyExtStep::Sub(1, 484), // components/onehot.h:38 +PolyExtStep::Add(10909, 483), // components/onehot.h:39 +PolyExtStep::Mul(484, 10911), // components/onehot.h:38 +PolyExtStep::AndEqz(1033, 10913), // components/onehot.h:38 +PolyExtStep::Sub(1, 485), // components/onehot.h:38 +PolyExtStep::Add(10912, 484), // components/onehot.h:39 +PolyExtStep::Mul(485, 10914), // components/onehot.h:38 +PolyExtStep::AndEqz(1034, 10916), // components/onehot.h:38 +PolyExtStep::Add(10915, 485), // components/onehot.h:39 +PolyExtStep::Sub(10917, 1), // components/onehot.h:41 +PolyExtStep::AndEqz(1035, 10918), // components/onehot.h:41 +PolyExtStep::Sub(1, 694), // components/onehot.h:38 +PolyExtStep::Mul(694, 10919), // components/onehot.h:38 +PolyExtStep::AndEqz(1036, 10920), // components/onehot.h:38 +PolyExtStep::Sub(1, 665), // components/onehot.h:38 +PolyExtStep::Mul(665, 10921), // components/onehot.h:38 +PolyExtStep::AndEqz(1037, 10922), // components/onehot.h:38 +PolyExtStep::Sub(1, 666), // components/onehot.h:38 +PolyExtStep::Add(694, 665), // components/onehot.h:39 +PolyExtStep::Mul(666, 10923), // components/onehot.h:38 +PolyExtStep::AndEqz(1038, 10925), // components/onehot.h:38 +PolyExtStep::Sub(1, 667), // components/onehot.h:38 +PolyExtStep::Add(10924, 666), // components/onehot.h:39 +PolyExtStep::Mul(667, 10926), // components/onehot.h:38 +PolyExtStep::AndEqz(1039, 10928), // components/onehot.h:38 +PolyExtStep::Sub(1, 668), // components/onehot.h:38 +PolyExtStep::Add(10927, 667), // components/onehot.h:39 +PolyExtStep::Mul(668, 10929), // components/onehot.h:38 +PolyExtStep::AndEqz(1040, 10931), // components/onehot.h:38 +PolyExtStep::Sub(1, 669), // components/onehot.h:38 +PolyExtStep::Add(10930, 668), // components/onehot.h:39 +PolyExtStep::Mul(669, 10932), // components/onehot.h:38 +PolyExtStep::AndEqz(1041, 10934), // components/onehot.h:38 +PolyExtStep::Sub(1, 670), // components/onehot.h:38 +PolyExtStep::Add(10933, 669), // components/onehot.h:39 +PolyExtStep::Mul(670, 10935), // components/onehot.h:38 +PolyExtStep::AndEqz(1042, 10937), // components/onehot.h:38 +PolyExtStep::Sub(1, 671), // components/onehot.h:38 +PolyExtStep::Add(10936, 670), // components/onehot.h:39 +PolyExtStep::Mul(671, 10938), // components/onehot.h:38 +PolyExtStep::AndEqz(1043, 10940), // components/onehot.h:38 +PolyExtStep::Sub(1, 672), // components/onehot.h:38 +PolyExtStep::Add(10939, 671), // components/onehot.h:39 +PolyExtStep::Mul(672, 10941), // components/onehot.h:38 +PolyExtStep::AndEqz(1044, 10943), // components/onehot.h:38 +PolyExtStep::Sub(1, 673), // components/onehot.h:38 +PolyExtStep::Add(10942, 672), // components/onehot.h:39 +PolyExtStep::Mul(673, 10944), // components/onehot.h:38 +PolyExtStep::AndEqz(1045, 10946), // components/onehot.h:38 +PolyExtStep::Sub(1, 674), // components/onehot.h:38 +PolyExtStep::Add(10945, 673), // components/onehot.h:39 +PolyExtStep::Mul(674, 10947), // components/onehot.h:38 +PolyExtStep::AndEqz(1046, 10949), // components/onehot.h:38 +PolyExtStep::Add(10948, 674), // components/onehot.h:39 +PolyExtStep::Sub(10950, 1), // components/onehot.h:41 +PolyExtStep::AndEqz(1047, 10951), // components/onehot.h:41 +PolyExtStep::AndCond(1012, 284, 1048), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Sub(1, 320), // components/bits.h:65 +PolyExtStep::Sub(2, 320), // components/bits.h:65 +PolyExtStep::Sub(3, 320), // components/bits.h:65 +PolyExtStep::Mul(320, 10952), // components/bits.h:65 +PolyExtStep::Mul(10955, 10953), // components/bits.h:65 +PolyExtStep::Mul(10956, 10954), // components/bits.h:65 +PolyExtStep::AndEqz(0, 10957), // components/bits.h:65 +PolyExtStep::Sub(1, 321), // components/bits.h:65 +PolyExtStep::Sub(2, 321), // components/bits.h:65 +PolyExtStep::Sub(3, 321), // components/bits.h:65 +PolyExtStep::Mul(321, 10958), // components/bits.h:65 +PolyExtStep::Mul(10961, 10959), // components/bits.h:65 +PolyExtStep::Mul(10962, 10960), // components/bits.h:65 +PolyExtStep::AndEqz(1050, 10963), // components/bits.h:65 +PolyExtStep::Sub(1, 322), // components/bits.h:65 +PolyExtStep::Sub(2, 322), // components/bits.h:65 +PolyExtStep::Sub(3, 322), // components/bits.h:65 +PolyExtStep::Mul(322, 10964), // components/bits.h:65 +PolyExtStep::Mul(10967, 10965), // components/bits.h:65 +PolyExtStep::Mul(10968, 10966), // components/bits.h:65 +PolyExtStep::AndEqz(1051, 10969), // components/bits.h:65 +PolyExtStep::Sub(1, 323), // components/bits.h:65 +PolyExtStep::Sub(2, 323), // components/bits.h:65 +PolyExtStep::Sub(3, 323), // components/bits.h:65 +PolyExtStep::Mul(323, 10970), // components/bits.h:65 +PolyExtStep::Mul(10973, 10971), // components/bits.h:65 +PolyExtStep::Mul(10974, 10972), // components/bits.h:65 +PolyExtStep::AndEqz(1052, 10975), // components/bits.h:65 +PolyExtStep::Sub(1, 324), // components/bits.h:65 +PolyExtStep::Sub(2, 324), // components/bits.h:65 +PolyExtStep::Sub(3, 324), // components/bits.h:65 +PolyExtStep::Mul(324, 10976), // components/bits.h:65 +PolyExtStep::Mul(10979, 10977), // components/bits.h:65 +PolyExtStep::Mul(10980, 10978), // components/bits.h:65 +PolyExtStep::AndEqz(1053, 10981), // components/bits.h:65 +PolyExtStep::Sub(1, 325), // components/bits.h:65 +PolyExtStep::Sub(2, 325), // components/bits.h:65 +PolyExtStep::Sub(3, 325), // components/bits.h:65 +PolyExtStep::Mul(325, 10982), // components/bits.h:65 +PolyExtStep::Mul(10985, 10983), // components/bits.h:65 +PolyExtStep::Mul(10986, 10984), // components/bits.h:65 +PolyExtStep::AndEqz(1054, 10987), // components/bits.h:65 +PolyExtStep::Sub(1, 699), // components/bits.h:34 +PolyExtStep::Mul(699, 10988), // components/bits.h:34 +PolyExtStep::AndEqz(0, 10989), // components/bits.h:34 +PolyExtStep::Sub(1, 700), // components/bits.h:34 +PolyExtStep::Mul(700, 10990), // components/bits.h:34 +PolyExtStep::AndEqz(1056, 10991), // components/bits.h:34 +PolyExtStep::Sub(1, 701), // components/bits.h:34 +PolyExtStep::Mul(701, 10992), // components/bits.h:34 +PolyExtStep::AndEqz(1057, 10993), // components/bits.h:34 +PolyExtStep::Sub(1, 702), // components/bits.h:34 +PolyExtStep::Mul(702, 10994), // components/bits.h:34 +PolyExtStep::AndEqz(1058, 10995), // components/bits.h:34 +PolyExtStep::Sub(1, 703), // components/bits.h:34 +PolyExtStep::Mul(703, 10996), // components/bits.h:34 +PolyExtStep::AndEqz(1059, 10997), // components/bits.h:34 +PolyExtStep::Sub(1, 704), // components/bits.h:34 +PolyExtStep::Mul(704, 10998), // components/bits.h:34 +PolyExtStep::AndEqz(1060, 10999), // components/bits.h:34 +PolyExtStep::Sub(1, 705), // components/bits.h:34 +PolyExtStep::Mul(705, 11000), // components/bits.h:34 +PolyExtStep::AndEqz(1061, 11001), // components/bits.h:34 +PolyExtStep::Sub(1, 706), // components/bits.h:34 +PolyExtStep::Mul(706, 11002), // components/bits.h:34 +PolyExtStep::AndEqz(1062, 11003), // components/bits.h:34 +PolyExtStep::Sub(1, 707), // components/bits.h:34 +PolyExtStep::Mul(707, 11004), // components/bits.h:34 +PolyExtStep::AndEqz(1063, 11005), // components/bits.h:34 +PolyExtStep::Sub(1, 708), // components/bits.h:34 +PolyExtStep::Mul(708, 11006), // components/bits.h:34 +PolyExtStep::AndEqz(1064, 11007), // components/bits.h:34 +PolyExtStep::AndEqz(1065, 810), // components/bits.h:34 +PolyExtStep::Sub(1, 712), // components/bits.h:34 +PolyExtStep::Mul(712, 11008), // components/bits.h:34 +PolyExtStep::AndEqz(1066, 11009), // components/bits.h:34 +PolyExtStep::Sub(1, 714), // components/bits.h:34 +PolyExtStep::Mul(714, 11010), // components/bits.h:34 +PolyExtStep::AndEqz(1067, 11011), // components/bits.h:34 +PolyExtStep::Sub(1, 716), // components/bits.h:34 +PolyExtStep::Mul(716, 11012), // components/bits.h:34 +PolyExtStep::AndEqz(1068, 11013), // components/bits.h:34 +PolyExtStep::Sub(1, 899), // components/bits.h:34 +PolyExtStep::Mul(899, 11014), // components/bits.h:34 +PolyExtStep::AndEqz(1069, 11015), // components/bits.h:34 +PolyExtStep::Sub(1, 900), // components/bits.h:34 +PolyExtStep::Mul(900, 11016), // components/bits.h:34 +PolyExtStep::AndEqz(1070, 11017), // components/bits.h:34 +PolyExtStep::Sub(1, 908), // components/bits.h:34 +PolyExtStep::Mul(908, 11018), // components/bits.h:34 +PolyExtStep::AndEqz(1071, 11019), // components/bits.h:34 +PolyExtStep::Sub(1, 909), // components/bits.h:34 +PolyExtStep::Mul(909, 11020), // components/bits.h:34 +PolyExtStep::AndEqz(1072, 11021), // components/bits.h:34 +PolyExtStep::Sub(1, 917), // components/bits.h:34 +PolyExtStep::Mul(917, 11022), // components/bits.h:34 +PolyExtStep::AndEqz(1073, 11023), // components/bits.h:34 +PolyExtStep::Sub(1, 918), // components/bits.h:34 +PolyExtStep::Mul(918, 11024), // components/bits.h:34 +PolyExtStep::AndEqz(1074, 11025), // components/bits.h:34 +PolyExtStep::Sub(1, 926), // components/bits.h:34 +PolyExtStep::Mul(926, 11026), // components/bits.h:34 +PolyExtStep::AndEqz(1075, 11027), // components/bits.h:34 +PolyExtStep::Sub(1, 927), // components/bits.h:34 +PolyExtStep::Mul(927, 11028), // components/bits.h:34 +PolyExtStep::AndEqz(1076, 11029), // components/bits.h:34 +PolyExtStep::Sub(1, 935), // components/bits.h:34 +PolyExtStep::Mul(935, 11030), // components/bits.h:34 +PolyExtStep::AndEqz(1077, 11031), // components/bits.h:34 +PolyExtStep::Sub(1, 936), // components/bits.h:34 +PolyExtStep::Mul(936, 11032), // components/bits.h:34 +PolyExtStep::AndEqz(1078, 11033), // components/bits.h:34 +PolyExtStep::Sub(1, 944), // components/bits.h:34 +PolyExtStep::Mul(944, 11034), // components/bits.h:34 +PolyExtStep::AndEqz(1079, 11035), // components/bits.h:34 +PolyExtStep::Sub(1, 945), // components/bits.h:34 +PolyExtStep::Mul(945, 11036), // components/bits.h:34 +PolyExtStep::AndEqz(1080, 11037), // components/bits.h:34 +PolyExtStep::Sub(1, 953), // components/bits.h:34 +PolyExtStep::Mul(953, 11038), // components/bits.h:34 +PolyExtStep::AndEqz(1081, 11039), // components/bits.h:34 +PolyExtStep::Sub(1, 954), // components/bits.h:34 +PolyExtStep::Mul(954, 11040), // components/bits.h:34 +PolyExtStep::AndEqz(1082, 11041), // components/bits.h:34 +PolyExtStep::Sub(1, 962), // components/bits.h:34 +PolyExtStep::Mul(962, 11042), // components/bits.h:34 +PolyExtStep::AndEqz(1083, 11043), // components/bits.h:34 +PolyExtStep::Sub(1, 963), // components/bits.h:34 +PolyExtStep::Mul(963, 11044), // components/bits.h:34 +PolyExtStep::AndEqz(1084, 11045), // components/bits.h:34 +PolyExtStep::Sub(1, 971), // components/bits.h:34 +PolyExtStep::Mul(971, 11046), // components/bits.h:34 +PolyExtStep::AndEqz(1085, 11047), // components/bits.h:34 +PolyExtStep::Sub(1, 972), // components/bits.h:34 +PolyExtStep::Mul(972, 11048), // components/bits.h:34 +PolyExtStep::AndEqz(1086, 11049), // components/bits.h:34 +PolyExtStep::Sub(1, 980), // components/bits.h:34 +PolyExtStep::Mul(980, 11050), // components/bits.h:34 +PolyExtStep::AndEqz(1087, 11051), // components/bits.h:34 +PolyExtStep::Sub(1, 981), // components/bits.h:34 +PolyExtStep::Mul(981, 11052), // components/bits.h:34 +PolyExtStep::AndEqz(1088, 11053), // components/bits.h:34 +PolyExtStep::Sub(1, 989), // components/bits.h:34 +PolyExtStep::Mul(989, 11054), // components/bits.h:34 +PolyExtStep::AndEqz(1089, 11055), // components/bits.h:34 +PolyExtStep::Sub(1, 990), // components/bits.h:34 +PolyExtStep::Mul(990, 11056), // components/bits.h:34 +PolyExtStep::AndEqz(1090, 11057), // components/bits.h:34 +PolyExtStep::Sub(1, 998), // components/bits.h:34 +PolyExtStep::Mul(998, 11058), // components/bits.h:34 +PolyExtStep::AndEqz(1091, 11059), // components/bits.h:34 +PolyExtStep::Sub(1, 999), // components/bits.h:34 +PolyExtStep::Mul(999, 11060), // components/bits.h:34 +PolyExtStep::AndEqz(1092, 11061), // components/bits.h:34 +PolyExtStep::Sub(1, 1007), // components/bits.h:34 +PolyExtStep::Mul(1007, 11062), // components/bits.h:34 +PolyExtStep::AndEqz(1093, 11063), // components/bits.h:34 +PolyExtStep::Sub(1, 1008), // components/bits.h:34 +PolyExtStep::Mul(1008, 11064), // components/bits.h:34 +PolyExtStep::AndEqz(1094, 11065), // components/bits.h:34 +PolyExtStep::Sub(1, 1016), // components/bits.h:34 +PolyExtStep::Mul(1016, 11066), // components/bits.h:34 +PolyExtStep::AndEqz(1095, 11067), // components/bits.h:34 +PolyExtStep::Sub(1, 1017), // components/bits.h:34 +PolyExtStep::Mul(1017, 11068), // components/bits.h:34 +PolyExtStep::AndEqz(1096, 11069), // components/bits.h:34 +PolyExtStep::Sub(1, 1025), // components/bits.h:34 +PolyExtStep::Mul(1025, 11070), // components/bits.h:34 +PolyExtStep::AndEqz(1097, 11071), // components/bits.h:34 +PolyExtStep::Sub(1, 1026), // components/bits.h:34 +PolyExtStep::Mul(1026, 11072), // components/bits.h:34 +PolyExtStep::AndEqz(1098, 11073), // components/bits.h:34 +PolyExtStep::Sub(1, 1034), // components/bits.h:34 +PolyExtStep::Mul(1034, 11074), // components/bits.h:34 +PolyExtStep::AndEqz(1099, 11075), // components/bits.h:34 +PolyExtStep::Sub(1, 1035), // components/bits.h:34 +PolyExtStep::Mul(1035, 11076), // components/bits.h:34 +PolyExtStep::AndEqz(1100, 11077), // components/bits.h:34 +PolyExtStep::Sub(1, 1043), // components/bits.h:34 +PolyExtStep::Mul(1043, 11078), // components/bits.h:34 +PolyExtStep::AndEqz(1101, 11079), // components/bits.h:34 +PolyExtStep::Sub(1, 1044), // components/bits.h:34 +PolyExtStep::Mul(1044, 11080), // components/bits.h:34 +PolyExtStep::AndEqz(1102, 11081), // components/bits.h:34 +PolyExtStep::Sub(1, 1052), // components/bits.h:34 +PolyExtStep::Mul(1052, 11082), // components/bits.h:34 +PolyExtStep::AndEqz(1103, 11083), // components/bits.h:34 +PolyExtStep::Sub(1, 1053), // components/bits.h:34 +PolyExtStep::Mul(1053, 11084), // components/bits.h:34 +PolyExtStep::AndEqz(1104, 11085), // components/bits.h:34 +PolyExtStep::Sub(1, 1061), // components/bits.h:34 +PolyExtStep::Mul(1061, 11086), // components/bits.h:34 +PolyExtStep::AndEqz(1105, 11087), // components/bits.h:34 +PolyExtStep::Sub(1, 1062), // components/bits.h:34 +PolyExtStep::Mul(1062, 11088), // components/bits.h:34 +PolyExtStep::AndEqz(1106, 11089), // components/bits.h:34 +PolyExtStep::Sub(1, 1070), // components/bits.h:34 +PolyExtStep::Mul(1070, 11090), // components/bits.h:34 +PolyExtStep::AndEqz(1107, 11091), // components/bits.h:34 +PolyExtStep::Sub(1, 1071), // components/bits.h:34 +PolyExtStep::Mul(1071, 11092), // components/bits.h:34 +PolyExtStep::AndEqz(1108, 11093), // components/bits.h:34 +PolyExtStep::AndEqz(1109, 10854), // components/bits.h:34 +PolyExtStep::AndEqz(1110, 10856), // components/bits.h:34 +PolyExtStep::AndEqz(1111, 10859), // components/bits.h:34 +PolyExtStep::AndEqz(1112, 10862), // components/bits.h:34 +PolyExtStep::AndEqz(1113, 10865), // components/bits.h:34 +PolyExtStep::AndEqz(1114, 10868), // components/bits.h:34 +PolyExtStep::AndEqz(1115, 10871), // components/bits.h:34 +PolyExtStep::AndEqz(1116, 10874), // components/bits.h:34 +PolyExtStep::AndCond(1055, 318, 1117), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndEqz(1117, 10877), // components/bits.h:34 +PolyExtStep::AndEqz(1119, 10880), // components/bits.h:34 +PolyExtStep::AndCond(1118, 475, 1120), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Sub(1, 515), // components/bits.h:34 +PolyExtStep::Mul(515, 11094), // components/bits.h:34 +PolyExtStep::AndEqz(0, 11095), // components/bits.h:34 +PolyExtStep::Sub(1, 516), // components/bits.h:34 +PolyExtStep::Mul(516, 11096), // components/bits.h:34 +PolyExtStep::AndEqz(1122, 11097), // components/bits.h:34 +PolyExtStep::Sub(1, 517), // components/bits.h:34 +PolyExtStep::Mul(517, 11098), // components/bits.h:34 +PolyExtStep::AndEqz(1123, 11099), // components/bits.h:34 +PolyExtStep::Sub(1, 518), // components/bits.h:34 +PolyExtStep::Mul(518, 11100), // components/bits.h:34 +PolyExtStep::AndEqz(1124, 11101), // components/bits.h:34 +PolyExtStep::Sub(1, 519), // components/bits.h:34 +PolyExtStep::Mul(519, 11102), // components/bits.h:34 +PolyExtStep::AndEqz(1125, 11103), // components/bits.h:34 +PolyExtStep::AndEqz(1126, 621), // components/bits.h:34 +PolyExtStep::Sub(1, 523), // components/bits.h:34 +PolyExtStep::Mul(523, 11104), // components/bits.h:34 +PolyExtStep::AndEqz(1127, 11105), // components/bits.h:34 +PolyExtStep::Sub(1, 525), // components/bits.h:34 +PolyExtStep::Mul(525, 11106), // components/bits.h:34 +PolyExtStep::AndEqz(1128, 11107), // components/bits.h:34 +PolyExtStep::Sub(1, 527), // components/bits.h:34 +PolyExtStep::Mul(527, 11108), // components/bits.h:34 +PolyExtStep::AndEqz(1129, 11109), // components/bits.h:34 +PolyExtStep::Sub(1, 698), // components/bits.h:34 +PolyExtStep::Mul(698, 11110), // components/bits.h:34 +PolyExtStep::AndEqz(1130, 11111), // components/bits.h:34 +PolyExtStep::AndEqz(1131, 10989), // components/bits.h:34 +PolyExtStep::AndEqz(1132, 10991), // components/bits.h:34 +PolyExtStep::AndEqz(1133, 10993), // components/bits.h:34 +PolyExtStep::AndEqz(1134, 10995), // components/bits.h:34 +PolyExtStep::AndEqz(1135, 10997), // components/bits.h:34 +PolyExtStep::AndEqz(1136, 10999), // components/bits.h:34 +PolyExtStep::AndEqz(1137, 11001), // components/bits.h:34 +PolyExtStep::AndEqz(1138, 11003), // components/bits.h:34 +PolyExtStep::AndEqz(1139, 11005), // components/bits.h:34 +PolyExtStep::AndEqz(1140, 11007), // components/bits.h:34 +PolyExtStep::AndEqz(1141, 810), // components/bits.h:34 +PolyExtStep::AndEqz(1142, 11009), // components/bits.h:34 +PolyExtStep::AndEqz(1143, 11011), // components/bits.h:34 +PolyExtStep::AndEqz(1144, 11013), // components/bits.h:34 +PolyExtStep::AndEqz(1145, 11015), // components/bits.h:34 +PolyExtStep::AndEqz(1146, 11017), // components/bits.h:34 +PolyExtStep::AndEqz(1147, 11019), // components/bits.h:34 +PolyExtStep::AndEqz(1148, 11021), // components/bits.h:34 +PolyExtStep::AndEqz(1149, 11023), // components/bits.h:34 +PolyExtStep::AndEqz(1150, 11025), // components/bits.h:34 +PolyExtStep::AndEqz(1151, 11027), // components/bits.h:34 +PolyExtStep::AndEqz(1152, 11029), // components/bits.h:34 +PolyExtStep::AndEqz(1153, 11035), // components/bits.h:34 +PolyExtStep::AndEqz(1154, 11037), // components/bits.h:34 +PolyExtStep::AndEqz(1155, 11039), // components/bits.h:34 +PolyExtStep::AndEqz(1156, 11041), // components/bits.h:34 +PolyExtStep::AndEqz(1157, 11043), // components/bits.h:34 +PolyExtStep::AndEqz(1158, 11045), // components/bits.h:34 +PolyExtStep::AndEqz(1159, 11047), // components/bits.h:34 +PolyExtStep::AndEqz(1160, 11049), // components/bits.h:34 +PolyExtStep::AndEqz(1161, 11051), // components/bits.h:34 +PolyExtStep::AndEqz(1162, 11053), // components/bits.h:34 +PolyExtStep::AndEqz(1163, 11055), // components/bits.h:34 +PolyExtStep::AndEqz(1164, 11057), // components/bits.h:34 +PolyExtStep::AndEqz(1165, 11059), // components/bits.h:34 +PolyExtStep::AndEqz(1166, 11061), // components/bits.h:34 +PolyExtStep::AndEqz(1167, 11063), // components/bits.h:34 +PolyExtStep::AndEqz(1168, 11065), // components/bits.h:34 +PolyExtStep::AndEqz(1169, 11067), // components/bits.h:34 +PolyExtStep::AndEqz(1170, 11069), // components/bits.h:34 +PolyExtStep::AndEqz(1171, 11071), // components/bits.h:34 +PolyExtStep::AndEqz(1172, 11073), // components/bits.h:34 +PolyExtStep::AndEqz(1173, 11075), // components/bits.h:34 +PolyExtStep::AndEqz(1174, 11077), // components/bits.h:34 +PolyExtStep::AndEqz(1175, 11079), // components/bits.h:34 +PolyExtStep::AndEqz(1176, 11081), // components/bits.h:34 +PolyExtStep::AndEqz(1177, 11083), // components/bits.h:34 +PolyExtStep::AndEqz(1178, 11085), // components/bits.h:34 +PolyExtStep::AndEqz(1179, 11087), // components/bits.h:34 +PolyExtStep::AndEqz(1180, 11089), // components/bits.h:34 +PolyExtStep::AndEqz(1181, 11091), // components/bits.h:34 +PolyExtStep::AndEqz(1182, 11093), // components/bits.h:34 +PolyExtStep::AndEqz(1183, 10854), // components/bits.h:34 +PolyExtStep::AndEqz(1184, 10856), // components/bits.h:34 +PolyExtStep::AndEqz(1185, 10865), // components/bits.h:34 +PolyExtStep::AndEqz(1186, 10868), // components/bits.h:34 +PolyExtStep::AndEqz(1187, 10871), // components/bits.h:34 +PolyExtStep::AndEqz(1188, 10874), // components/bits.h:34 +PolyExtStep::AndEqz(1189, 10877), // components/bits.h:34 +PolyExtStep::AndEqz(1190, 10880), // components/bits.h:34 +PolyExtStep::AndEqz(1191, 10883), // components/bits.h:34 +PolyExtStep::Sub(1, 430), // components/bits.h:34 +PolyExtStep::Mul(430, 11112), // components/bits.h:34 +PolyExtStep::AndEqz(1192, 11113), // components/bits.h:34 +PolyExtStep::AndEqz(1193, 10887), // components/bits.h:34 +PolyExtStep::AndEqz(1194, 10889), // components/bits.h:34 +PolyExtStep::AndEqz(1195, 10892), // components/bits.h:34 +PolyExtStep::AndEqz(1196, 10895), // components/bits.h:34 +PolyExtStep::AndEqz(1197, 10898), // components/bits.h:34 +PolyExtStep::AndEqz(1198, 10901), // components/bits.h:34 +PolyExtStep::AndEqz(1199, 10904), // components/bits.h:34 +PolyExtStep::AndEqz(1200, 10907), // components/bits.h:34 +PolyExtStep::AndEqz(1201, 10910), // components/bits.h:34 +PolyExtStep::AndEqz(1202, 10913), // components/bits.h:34 +PolyExtStep::AndEqz(1203, 10916), // components/bits.h:34 +PolyExtStep::Sub(1, 619), // components/bits.h:34 +PolyExtStep::Mul(619, 11114), // components/bits.h:34 +PolyExtStep::AndEqz(1204, 11115), // components/bits.h:34 +PolyExtStep::AndEqz(1205, 10920), // components/bits.h:34 +PolyExtStep::AndEqz(1206, 10922), // components/bits.h:34 +PolyExtStep::AndEqz(1207, 10925), // components/bits.h:34 +PolyExtStep::AndEqz(1208, 10928), // components/bits.h:34 +PolyExtStep::AndEqz(1209, 10931), // components/bits.h:34 +PolyExtStep::AndEqz(1210, 10934), // components/bits.h:34 +PolyExtStep::AndEqz(1211, 10937), // components/bits.h:34 +PolyExtStep::AndEqz(1212, 10940), // components/bits.h:34 +PolyExtStep::AndEqz(1213, 10943), // components/bits.h:34 +PolyExtStep::AndEqz(1214, 10946), // components/bits.h:34 +PolyExtStep::AndEqz(1215, 10949), // components/bits.h:34 +PolyExtStep::Sub(1, 808), // components/bits.h:34 +PolyExtStep::Mul(808, 11116), // components/bits.h:34 +PolyExtStep::AndEqz(1216, 11117), // components/bits.h:34 +PolyExtStep::AndCond(1121, 506, 1217), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(1218, 508, 1217), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(1219, 507, 1217), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(1220, 664, 1217), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::Sub(1, 326), // components/onehot.h:38 +PolyExtStep::Mul(326, 11118), // components/onehot.h:38 +PolyExtStep::AndEqz(0, 11119), // components/onehot.h:38 +PolyExtStep::Sub(1, 327), // components/onehot.h:38 +PolyExtStep::Mul(327, 11120), // components/onehot.h:38 +PolyExtStep::AndEqz(1222, 11121), // components/onehot.h:38 +PolyExtStep::Sub(1, 328), // components/onehot.h:38 +PolyExtStep::Add(326, 327), // components/onehot.h:39 +PolyExtStep::Mul(328, 11122), // components/onehot.h:38 +PolyExtStep::AndEqz(1223, 11124), // components/onehot.h:38 +PolyExtStep::Sub(1, 329), // components/onehot.h:38 +PolyExtStep::Add(11123, 328), // components/onehot.h:39 +PolyExtStep::Mul(329, 11125), // components/onehot.h:38 +PolyExtStep::AndEqz(1224, 11127), // components/onehot.h:38 +PolyExtStep::Add(11126, 329), // components/onehot.h:39 +PolyExtStep::Sub(11128, 1), // components/onehot.h:41 +PolyExtStep::AndEqz(1225, 11129), // components/onehot.h:41 +PolyExtStep::AndCond(1221, 695, 1226), // zirgen/compiler/edsl/component.cpp:49 +PolyExtStep::AndCond(1049, 852, 1227), // zirgen/compiler/edsl/component.cpp:49 +], + ret: 1228, +}; + +impl PolyExt for CircuitImpl { + fn poly_ext( + &self, + mix: &BabyBearExtElem, + u: &[BabyBearExtElem], + args: &[&[BabyBearElem]], + ) -> MixState { + DEF.step::(mix, u, args) + } +} diff --git a/src/circuit/v3_0/recursive/taps.rs b/src/circuit/v3_0/recursive/taps.rs new file mode 100644 index 0000000..e395d4f --- /dev/null +++ b/src/circuit/v3_0/recursive/taps.rs @@ -0,0 +1,4536 @@ +// Copyright Copyright 2024, Horizen Labs, Inc. +// Copyright Copyright 2025 RISC Zero, Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +use risc0_zkp_v3::taps::{TapData, TapSet}; + +#[allow(missing_docs)] +pub const TAPSET: &TapSet = &TapSet::<'static> { + taps: &[ + TapData { + offset: 0, + back: 0, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 0, + back: 1, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 1, + back: 0, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 1, + back: 1, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 2, + back: 0, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 2, + back: 1, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 3, + back: 0, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 3, + back: 1, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 4, + back: 0, + group: 0, + combo: 0, + skip: 1, + }, + TapData { + offset: 5, + back: 0, + group: 0, + combo: 0, + skip: 1, + }, + TapData { + offset: 6, + back: 0, + group: 0, + combo: 0, + skip: 1, + }, + TapData { + offset: 7, + back: 0, + group: 0, + combo: 0, + skip: 1, + }, + TapData { + offset: 8, + back: 0, + group: 0, + combo: 0, + skip: 1, + }, + TapData { + offset: 9, + back: 0, + group: 0, + combo: 0, + skip: 1, + }, + TapData { + offset: 10, + back: 0, + group: 0, + combo: 0, + skip: 1, + }, + TapData { + offset: 11, + back: 0, + group: 0, + combo: 0, + skip: 1, + }, + TapData { + offset: 0, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 1, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 2, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 3, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 4, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 5, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 6, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 7, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 8, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 9, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 10, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 11, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 12, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 13, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 14, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 15, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 16, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 17, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 18, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 19, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 20, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 21, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 22, + back: 0, + group: 1, + combo: 0, + skip: 1, + }, + TapData { + offset: 0, + back: 0, + group: 2, + combo: 1, + skip: 2, + }, + TapData { + offset: 0, + back: 1, + group: 2, + combo: 1, + skip: 2, + }, + TapData { + offset: 1, + back: 0, + group: 2, + combo: 1, + skip: 2, + }, + TapData { + offset: 1, + back: 1, + group: 2, + combo: 1, + skip: 2, + }, + TapData { + offset: 2, + back: 0, + group: 2, + combo: 1, + skip: 2, + }, + TapData { + offset: 2, + back: 1, + group: 2, + combo: 1, + skip: 2, + }, + TapData { + offset: 3, + back: 0, + group: 2, + combo: 1, + skip: 2, + }, + TapData { + offset: 3, + back: 1, + group: 2, + combo: 1, + skip: 2, + }, + TapData { + offset: 4, + back: 0, + group: 2, + combo: 1, + skip: 2, + }, + TapData { + offset: 4, + back: 1, + group: 2, + combo: 1, + skip: 2, + }, + TapData { + offset: 5, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 6, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 7, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 8, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 9, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 10, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 11, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 12, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 13, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 14, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 15, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 16, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 17, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 18, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 19, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 20, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 21, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 22, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 23, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 24, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 25, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 26, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 26, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 26, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 26, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 26, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 26, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 27, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 27, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 27, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 27, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 27, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 27, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 28, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 28, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 28, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 28, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 28, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 28, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 29, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 29, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 29, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 29, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 29, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 29, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 30, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 30, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 30, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 30, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 30, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 30, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 31, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 31, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 31, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 31, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 31, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 31, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 32, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 32, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 32, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 32, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 32, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 32, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 33, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 33, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 33, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 33, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 33, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 33, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 34, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 34, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 34, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 34, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 34, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 34, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 35, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 35, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 35, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 35, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 35, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 35, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 36, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 36, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 36, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 36, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 36, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 36, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 37, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 37, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 37, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 37, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 37, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 37, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 38, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 38, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 38, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 38, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 38, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 38, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 39, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 39, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 39, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 39, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 39, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 39, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 40, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 40, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 40, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 40, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 40, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 40, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 41, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 41, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 41, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 41, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 41, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 41, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 42, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 42, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 42, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 42, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 42, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 42, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 43, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 43, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 43, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 43, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 43, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 43, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 44, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 44, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 44, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 44, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 44, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 44, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 45, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 45, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 45, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 45, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 45, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 45, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 46, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 46, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 46, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 46, + back: 3, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 46, + back: 4, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 46, + back: 68, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 47, + back: 0, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 47, + back: 1, + group: 2, + combo: 2, + skip: 6, + }, + TapData { + offset: 47, + back: 2, + group: 2, + combo: 2, + skip: 6, + }, + TapData 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{ + offset: 93, + back: 0, + group: 2, + combo: 1, + skip: 2, + }, + TapData { + offset: 93, + back: 1, + group: 2, + combo: 1, + skip: 2, + }, + TapData { + offset: 94, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 94, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 94, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 94, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 94, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 94, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 95, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 95, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 95, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 95, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 95, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 95, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 96, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 96, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 96, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 96, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 96, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 96, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 97, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 97, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 97, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 97, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 97, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 97, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 98, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 98, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 98, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 98, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 98, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 98, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 99, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 99, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 99, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 99, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 99, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 99, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 100, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 100, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 100, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 100, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 100, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 100, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 101, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 101, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 101, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 101, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 101, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 101, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 102, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 102, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 102, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 102, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 102, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 102, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 103, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 103, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 103, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 103, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 103, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 103, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 104, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 104, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 104, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 104, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 104, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 104, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 105, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 105, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 105, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 105, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 105, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 105, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 106, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 106, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 106, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 106, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 106, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 106, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 107, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 107, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 107, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 107, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 107, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 107, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 108, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 108, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 108, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 108, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 108, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 108, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 109, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 109, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 109, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 109, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 109, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 109, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 110, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 110, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 110, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 110, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 110, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 110, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 111, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 111, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 111, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 111, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 111, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 111, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 112, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 112, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 112, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 112, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 112, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 112, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 113, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 113, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 113, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 113, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 113, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 113, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 114, + back: 0, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 114, + back: 2, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 114, + back: 7, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 114, + back: 15, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 114, + back: 16, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 115, + back: 0, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 115, + back: 2, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 115, + back: 7, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 115, + back: 15, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 115, + back: 16, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 116, + back: 0, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 116, + back: 2, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 116, + back: 7, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 116, + back: 15, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 116, + back: 16, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 117, + back: 0, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 117, + back: 2, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 117, + back: 7, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 117, + back: 15, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 117, + back: 16, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 118, + back: 0, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 118, + back: 2, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 118, + back: 7, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 118, + back: 15, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 118, + back: 16, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 119, + back: 0, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 119, + back: 2, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 119, + back: 7, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 119, + back: 15, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 119, + back: 16, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 120, + back: 0, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 120, + back: 2, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 120, + back: 7, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 120, + back: 15, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 120, + back: 16, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 121, + back: 0, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 121, + back: 2, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 121, + back: 7, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 121, + back: 15, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 121, + back: 16, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 122, + back: 0, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 122, + back: 2, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 122, + back: 7, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 122, + back: 15, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 122, + back: 16, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 123, + back: 0, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 123, + back: 2, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 123, + back: 7, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 123, + back: 15, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 123, + back: 16, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 124, + back: 0, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 124, + back: 2, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 124, + back: 7, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 124, + back: 15, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 124, + back: 16, + group: 2, + combo: 4, + skip: 5, + }, + TapData { + offset: 125, + back: 0, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 125, + back: 1, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 125, + back: 2, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 125, + back: 7, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 125, + back: 15, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 125, + back: 16, + group: 2, + combo: 3, + skip: 6, + }, + TapData { + offset: 126, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 127, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + ], + combo_taps: &[ + 0, 0, 1, 0, 1, 2, 3, 4, 68, 0, 1, 2, 7, 15, 16, 0, 2, 7, 15, 16, + ], + combo_begin: &[0, 1, 3, 9, 15, 20], + group_begin: &[0, 16, 39, 643], + combos_count: 5, + reg_count: 163, + tot_combo_backs: 20, + // TODO: Generate these instead of hardcoding: + group_names: &["accum", "code", "data"], +}; diff --git a/src/circuit/v3_0/taps.rs b/src/circuit/v3_0/taps.rs new file mode 100644 index 0000000..62f8618 --- /dev/null +++ b/src/circuit/v3_0/taps.rs @@ -0,0 +1,5563 @@ +// Copyright Copyright 2024, Horizen Labs, Inc. +// Copyright Copyright 2025 RISC Zero, Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +use risc0_zkp_v3::taps::{TapData, TapSet}; + +#[allow(missing_docs)] +pub const TAPSET: &TapSet = &TapSet::<'static> { + taps: &[ + TapData { + offset: 0, + back: 0, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 0, + back: 1, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 1, + back: 0, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 1, + back: 1, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 2, + back: 0, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 2, + back: 1, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 3, + back: 0, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 3, + back: 1, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 4, + back: 0, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 4, + back: 1, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 5, + back: 0, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 5, + back: 1, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 6, + back: 0, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 6, + back: 1, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 7, + back: 0, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 7, + back: 1, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 8, + back: 0, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 8, + back: 1, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 9, + back: 0, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 9, + back: 1, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 10, + back: 0, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 10, + back: 1, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 11, + back: 0, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 11, + back: 1, + group: 0, + combo: 1, + skip: 2, + }, + TapData { + offset: 12, + back: 0, + group: 0, + combo: 0, + skip: 1, + }, + TapData { + offset: 13, + back: 0, + group: 0, + combo: 0, + skip: 1, + }, + TapData { + offset: 14, + back: 0, + group: 0, + combo: 0, + skip: 1, + }, + TapData { + offset: 15, + back: 0, + group: 0, + combo: 0, + skip: 1, + }, + TapData { + offset: 16, + back: 0, + group: 0, + combo: 0, + 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back: 16, + group: 2, + combo: 3, + skip: 5, + }, + TapData { + offset: 130, + back: 0, + group: 2, + combo: 3, + skip: 5, + }, + TapData { + offset: 130, + back: 2, + group: 2, + combo: 3, + skip: 5, + }, + TapData { + offset: 130, + back: 7, + group: 2, + combo: 3, + skip: 5, + }, + TapData { + offset: 130, + back: 15, + group: 2, + combo: 3, + skip: 5, + }, + TapData { + offset: 130, + back: 16, + group: 2, + combo: 3, + skip: 5, + }, + TapData { + offset: 131, + back: 0, + group: 2, + combo: 3, + skip: 5, + }, + TapData { + offset: 131, + back: 2, + group: 2, + combo: 3, + skip: 5, + }, + TapData { + offset: 131, + back: 7, + group: 2, + combo: 3, + skip: 5, + }, + TapData { + offset: 131, + back: 15, + group: 2, + combo: 3, + skip: 5, + }, + TapData { + offset: 131, + back: 16, + group: 2, + combo: 3, + skip: 5, + }, + TapData { + offset: 132, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 133, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 134, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 135, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 136, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 137, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 138, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 139, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 140, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 141, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 142, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 143, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 144, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 145, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 146, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 147, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 148, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 149, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 150, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 151, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 152, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 153, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 154, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 155, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 156, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 157, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 158, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 159, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 160, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 161, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 162, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 163, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 164, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 165, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 166, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 167, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 168, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 169, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 170, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 171, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 172, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 173, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 174, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 175, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 176, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 177, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 178, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 179, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 180, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 181, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 182, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 183, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 184, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 185, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 186, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 187, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 188, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 189, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 190, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 191, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 192, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 193, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 194, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 195, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 196, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 197, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 198, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 199, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 200, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 201, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 202, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 203, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 204, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 205, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 206, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 207, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 208, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 209, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + TapData { + offset: 210, + back: 0, + group: 2, + combo: 0, + skip: 1, + }, + ], + combo_taps: &[0, 0, 1, 0, 1, 2, 3, 4, 68, 0, 2, 7, 15, 16], + combo_begin: &[0, 1, 3, 9, 14], + group_begin: &[0, 119, 120, 790], + combos_count: 4, + reg_count: 315, + tot_combo_backs: 14, + // TODO: Generate these instead of hardcoding: + group_names: &["accum", "code", "data"], +}; diff --git a/src/context.rs b/src/context.rs index 2a67c3a..e1a7e0c 100644 --- a/src/context.rs +++ b/src/context.rs @@ -26,6 +26,7 @@ use risc0_zkp_v1::{adapter::ProtocolInfo, core::digest::Digest, verify::Verifica pub mod v1; pub mod v2; +pub mod v3; pub struct VerifierParameters { /// Parameters for verification of [SuccinctReceipt]. diff --git a/src/context/v2.rs b/src/context/v2.rs index 4483020..cef61a1 100644 --- a/src/context/v2.rs +++ b/src/context/v2.rs @@ -32,6 +32,7 @@ use risc0_zkp_v1::{ core::digest::Digest, verify::VerificationError, }; +use risc0_zkp_v2::adapter::CircuitInfo; impl VerifierContext for V2 { type HashSuite = HashSuiteV2; @@ -70,11 +71,11 @@ impl VerifierContext for V2 } fn segment_circuit_info(&self) -> ProtocolInfo { - ProtocolInfo(*b"RV32IM:v2_______") + circuit::v2_0::CircuitImpl::CIRCUIT_INFO.translate() } fn succinct_circuit_info(&self) -> ProtocolInfo { - ProtocolInfo(*b"RECURSION:rev1v1") + circuit::v2_0::recursive::CircuitImpl::CIRCUIT_INFO.translate() } fn succinct_output_size(&self) -> usize { @@ -352,13 +353,13 @@ impl V2 { ]) } - /// Return [V1] with the given map of hash suites. + /// Return [V2] with the given map of hash suites. pub fn with_suites(mut self, suites: BTreeMap) -> Self { self.verifier_parameters.suites = suites; self } - /// Return [V1] with the given [SegmentReceiptVerifierParameters] set. + /// Return [V2] with the given [SegmentReceiptVerifierParameters] set. pub fn with_segment_verifier_parameters( mut self, params: SegmentReceiptVerifierParameters, @@ -367,7 +368,7 @@ impl V2 { self } - /// Return [V1] with the given [SuccinctReceiptVerifierParameters] set. + /// Return [V2] with the given [SuccinctReceiptVerifierParameters] set. pub fn with_succinct_verifier_parameters( mut self, params: SuccinctReceiptVerifierParameters, diff --git a/src/context/v3.rs b/src/context/v3.rs new file mode 100644 index 0000000..2301a5f --- /dev/null +++ b/src/context/v3.rs @@ -0,0 +1,389 @@ +// Copyright Copyright 2024, Horizen Labs, Inc. +// +// SPDX-License-Identifier: Apache-2.0 +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// + +use super::{BoxedVC, VerifierContext, VerifierParameters}; +use crate::receipt_claim::MaybePruned; +use crate::{ + circuit, circuit::CircuitCoreDefV3, poseidon2_injection::Poseidon2Mix, + receipt::merkle::MerkleProof, receipt::succinct::SuccinctReceiptVerifierParameters, + receipt_claim::ReceiptClaim, segment::SegmentReceiptVerifierParameters, translate::Translate, + Proof, +}; +use alloc::{boxed::Box, collections::BTreeMap, string::String}; +use risc0_binfmt_v1::{ExitCode, SystemState}; +use risc0_circuit_rv32im_v4::RV32IM_SEAL_VERSION; +use risc0_core_v1::field::baby_bear::BabyBear; +use risc0_zkp_v1::{ + adapter::{ProtocolInfo, PROOF_SYSTEM_INFO}, + core::digest::Digest, + verify::VerificationError, +}; +use risc0_zkp_v3::adapter::CircuitInfo; + +impl VerifierContext for V3 { + type HashSuite = HashSuiteV3; + type Segment = SegmentV3; + type Succinct = SuccinctV3; + fn verifier_parameters(&self) -> &VerifierParametersV3 { + &self.verifier_parameters + } + + fn mut_verifier_parameters( + &mut self, + ) -> &mut VerifierParameters { + &mut self.verifier_parameters + } + + fn boxed_clone(&self) -> BoxedVC { + let cloned = Self { + verifier_parameters: self.verifier_parameters.clone(), + circuit: self.circuit, + recursive_circuit: self.recursive_circuit, + }; + Box::new(cloned) + } + + fn boxed_succinct_verifier_with_control_root(&self, control_root: Digest) -> BoxedVC { + Box::new( + V3::empty(&circuit::v3_0::CIRCUIT, &circuit::v3_0::recursive::CIRCUIT) + .with_suites(self.verifier_parameters.suites.clone()) + .with_succinct_verifier_parameters(SuccinctReceiptVerifierParameters { + control_root, + inner_control_root: None, + proof_system_info: PROOF_SYSTEM_INFO, + circuit_info: self.succinct_circuit_info(), + }), + ) + } + + fn segment_circuit_info(&self) -> ProtocolInfo { + circuit::v3_0::CircuitImpl::CIRCUIT_INFO.translate() + } + + fn succinct_circuit_info(&self) -> ProtocolInfo { + circuit::v3_0::recursive::CircuitImpl::CIRCUIT_INFO.translate() + } + + fn succinct_output_size(&self) -> usize { + 32 + } + + fn decode_from_seal(&self, seal: &[u32]) -> Result { + decode_from_seal(seal, None) + } + + fn verify_segment( + &self, + hashfn: &str, + seal: &[u32], + _params: &SegmentReceiptVerifierParameters, + ) -> Result<(), VerificationError> { + let suite = self + .verifier_parameters() + .suite(hashfn) + .ok_or(VerificationError::InvalidHashSuite)?; + + // We don't have a `code' buffer to verify. + let check_code_fn = |_: u32, _: &risc0_zkp_v3::core::digest::Digest| Ok(()); + + if seal[0] != RV32IM_SEAL_VERSION { + return Err(VerificationError::ReceiptFormatError); + } + + let seal = &seal[1..]; + + risc0_zkp_v3::verify::verify(self.circuit, suite, seal, check_code_fn) + .map_err(Translate::translate) + } + + fn verify_succinct( + &self, + hashfn: &str, + seal: &[u32], + control_inclusion_proof: &MerkleProof, + params: &SuccinctReceiptVerifierParameters, + ) -> Result<(), VerificationError> { + let suite = self + .verifier_parameters() + .suite(hashfn) + .ok_or(VerificationError::InvalidHashSuite)?; + + let check_code = |_, + control_id: &risc0_zkp_v3::core::digest::Digest| + -> Result<(), risc0_zkp_v3::verify::VerificationError> { + let control_id_v1 = bytemuck::checked::cast_ref(control_id); + control_inclusion_proof + .verify(control_id_v1, ¶ms.control_root, &HashFnWrapper { inner: suite.hashfn.as_ref() }) + .map_err(|_| { + log::debug!( + "failed to verify control inclusion proof for {control_id} against root {} with {}", + params.control_root, + suite.name, + ); + risc0_zkp_v3::verify::VerificationError::ControlVerificationError { + control_id: *control_id, + } + }) + }; + + // Verify the receipt itself is correct, and therefore the encoded globals are + // reliable. + risc0_zkp_v3::verify::verify(self.recursive_circuit, suite, seal, check_code) + .map_err(Translate::translate) + } + + fn is_valid_receipt(&self, proof: &Proof) -> bool { + if let Ok(c) = proof.inner.composite() { + // V3 proof with `sha-256` segment are not admitted because misleading: they use + // poseidon2 even if in the segment `hashfn` is "sha-256" as reported in + // https://github.com/risc0/risc0/issues/3063 + if c.segments.iter().any(|s| s.hashfn == "sha-256") { + return false; + } + } + true + } + + fn segment_seal_offset(&self) -> usize { + 1 + } + + fn set_poseidon2_mix_impl(&mut self, poseidon2: Box) { + self.mut_verifier_parameters() + .suites + .entry("poseidon2".into()) + .and_modify(|s| { + s.hashfn = + alloc::rc::Rc::new(crate::poseidon2_injection::Poseidon2Impl::new(poseidon2)) + }); + } +} + +fn decode_from_seal(seal: &[u32], _po2: Option) -> Result { + let claim = risc0_circuit_rv32im_v4::Rv32imV2Claim::decode(seal) + .map_err(|_e| VerificationError::InvalidProof)?; + log::debug!("claim: {claim:#?}"); + + let exit_code = exit_code_from_rv32im_v4_claim(&claim)?; + let post_state = match exit_code { + ExitCode::Halted(_) => Digest::ZERO, + _ => claim.post_state.translate(), + }; + + Ok(ReceiptClaim { + pre: MaybePruned::Value(SystemState { + pc: 0, + merkle_root: claim.pre_state.translate(), + }), + post: MaybePruned::Value(SystemState { + pc: 0, + merkle_root: post_state, + }), + exit_code, + input: MaybePruned::Pruned(claim.input.translate()), + output: MaybePruned::Pruned(claim.output.unwrap_or_default().translate()), + }) +} + +#[allow(unused)] +pub mod halt { + pub const TERMINATE: u32 = 0; + pub const PAUSE: u32 = 1; + pub const SPLIT: u32 = 2; +} + +fn exit_code_from_rv32im_v4_claim( + claim: &risc0_circuit_rv32im_v4::Rv32imV2Claim, +) -> Result { + let exit_code = if let Some(term) = claim.terminate_state { + let risc0_circuit_rv32im_v4::HighLowU16(user_exit, halt_type) = term.a0; + match halt_type as u32 { + halt::TERMINATE => ExitCode::Halted(user_exit as u32), + halt::PAUSE => ExitCode::Paused(user_exit as u32), + _ => panic!("Illegal halt type: {halt_type}"), + } + } else { + ExitCode::SystemSplit + }; + Ok(exit_code) +} + +#[derive(Default, Clone, Copy)] +pub struct SegmentV3; + +impl crate::context::CircuitInfo for SegmentV3 { + fn protocol(&self) -> ProtocolInfo { + ::CIRCUIT_INFO.translate() + } + fn size(&self) -> usize { + ::OUTPUT_SIZE + } +} + +#[derive(Default, Clone, Copy)] +pub struct SuccinctV3; + +impl crate::context::CircuitInfo for SuccinctV3 { + fn protocol(&self) -> ProtocolInfo { + ::CIRCUIT_INFO + .translate() + } + fn size(&self) -> usize { + ::OUTPUT_SIZE + } +} + +pub type VerifierParametersV3 = VerifierParameters; +pub type HashSuiteV3 = + risc0_zkp_v3::core::hash::HashSuite; +pub type HashFnV3 = dyn risc0_zkp_v3::core::hash::HashFn; + +pub struct V3 { + verifier_parameters: VerifierParametersV3, + + circuit: &'static SC, + + recursive_circuit: &'static RC, +} + +impl Default for VerifierParametersV3 { + fn default() -> Self { + Self { + succinct_verifier_parameters: None, + suites: BTreeMap::new(), + segment_verifier_parameters: None, + segment: SegmentV3, + succinct: SuccinctV3, + } + } +} + +impl Clone for VerifierParametersV3 { + fn clone(&self) -> Self { + Self { + suites: self + .suites + .iter() + .map(|(k, v)| { + ( + k.clone(), + HashSuiteV3 { + name: v.name.clone(), + hashfn: v.hashfn.clone(), + rng: v.rng.clone(), + }, + ) + }) + .collect(), + segment_verifier_parameters: self.segment_verifier_parameters.clone(), + succinct_verifier_parameters: self.succinct_verifier_parameters.clone(), + segment: self.segment, + succinct: self.succinct, + } + } +} + +pub struct HashFnWrapper<'a> { + inner: &'a HashFnV3, +} + +impl risc0_zkp_v1::core::hash::HashFn for HashFnWrapper<'_> { + fn hash_pair(&self, a: &Digest, b: &Digest) -> Box { + let a = bytemuck::checked::cast_ref(a); + let b = bytemuck::checked::cast_ref(b); + (*self.inner.hash_pair(a, b)).translate().into() + } + + fn hash_elem_slice( + &self, + slice: &[::Elem], + ) -> Box { + let slice = bytemuck::checked::cast_slice(slice); + (*self.inner.hash_elem_slice(slice)).translate().into() + } + + fn hash_ext_elem_slice( + &self, + slice: &[::ExtElem], + ) -> Box { + let slice = bytemuck::checked::cast_slice(slice); + (*self.inner.hash_ext_elem_slice(slice)).translate().into() + } +} + +impl V3 { + /// Create an empty [V3]. + pub fn empty(circuit: &'static SC, recursive_circuit: &'static RC) -> Self { + Self { + verifier_parameters: Default::default(), + circuit, + recursive_circuit, + } + } + + /// Return the mapping of hash suites used in the default [V3]. + pub fn default_hash_suites() -> BTreeMap { + BTreeMap::from([ + ( + "blake2b".into(), + risc0_zkp_v3::core::hash::blake2b::Blake2bCpuHashSuite::new_suite(), + ), + ( + "poseidon2".into(), + risc0_zkp_v3::core::hash::poseidon2::Poseidon2HashSuite::new_suite(), + ), + ( + "sha-256".into(), + risc0_zkp_v3::core::hash::sha::Sha256HashSuite::new_suite(), + ), + ]) + } + + /// Return [V3] with the given map of hash suites. + pub fn with_suites(mut self, suites: BTreeMap) -> Self { + self.verifier_parameters.suites = suites; + self + } + + /// Return [V3] with the given [SegmentReceiptVerifierParameters] set. + pub fn with_segment_verifier_parameters( + mut self, + params: SegmentReceiptVerifierParameters, + ) -> Self { + self.verifier_parameters.segment_verifier_parameters = Some(params); + self + } + + /// Return [V3] with the given [SuccinctReceiptVerifierParameters] set. + pub fn with_succinct_verifier_parameters( + mut self, + params: SuccinctReceiptVerifierParameters, + ) -> Self { + self.verifier_parameters.succinct_verifier_parameters = Some(params); + self + } +} + +impl V3 { + /// Create an empty [V3] for any risc0 proof generate for any `3.0.x` vm version. + pub fn v3_0() -> Self { + Self::empty(&circuit::v3_0::CIRCUIT, &circuit::v3_0::recursive::CIRCUIT) + .with_suites(Self::default_hash_suites()) + .with_segment_verifier_parameters(SegmentReceiptVerifierParameters::v3_0()) + .with_succinct_verifier_parameters(SuccinctReceiptVerifierParameters::v3_0()) + } +} diff --git a/src/lib.rs b/src/lib.rs index dc8f395..e9238ee 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -93,3 +93,8 @@ pub fn v2_2() -> impl Verifier { pub fn v2_3() -> impl Verifier { context::v2::V2::v2_3() } + +/// Returns a `Verifier` for the specified RISC Zero prover 3.0 version. +pub fn v3_0() -> impl Verifier { + context::v3::V3::v3_0() +} diff --git a/src/poseidon2_injection.rs b/src/poseidon2_injection.rs index 337cdde..fe35783 100644 --- a/src/poseidon2_injection.rs +++ b/src/poseidon2_injection.rs @@ -220,25 +220,60 @@ mod v2 { let d = *>::hash_pair(self, a, b); - d.translate().into() + Translate::::translate(d).into() } fn hash_elem_slice(&self, slice: &[::Elem]) -> Box { let slice = bytemuck::checked::cast_slice(slice); - (*>::hash_elem_slice(self, slice); + Translate::::translate(d).into() + } + + fn hash_ext_elem_slice(&self, slice: &[::ExtElem]) -> Box { + let slice = bytemuck::checked::cast_slice(slice); + let d = *>::hash_ext_elem_slice(self, slice); + Translate::::translate(d).into() + } + } +} + +mod v3 { + use crate::poseidon2_injection::{Poseidon2Impl, Poseidon2Mix}; + use crate::translate::Translate; + use alloc::boxed::Box; + use risc0_core_v3::field::{baby_bear::BabyBear, Field}; + use risc0_zkp_v3::core::digest::Digest; + + impl risc0_zkp_v3::core::hash::HashFn + for Poseidon2Impl + { + fn hash_pair(&self, a: &Digest, b: &Digest) -> Box { + let a = bytemuck::checked::cast_ref(a); + let b = bytemuck::checked::cast_ref(b); + let d = *>::hash_elem_slice(self, slice)) - .translate() - .into() + >>::hash_pair(self, a, b); + Translate::::translate(d).into() + } + + fn hash_elem_slice(&self, slice: &[::Elem]) -> Box { + let slice = bytemuck::checked::cast_slice(slice); + let d = *>::hash_elem_slice(self, slice); + Translate::::translate(d).into() } fn hash_ext_elem_slice(&self, slice: &[::ExtElem]) -> Box { let slice = bytemuck::checked::cast_slice(slice); - (*>::hash_ext_elem_slice(self, slice)) - .translate() - .into() + >>::hash_ext_elem_slice(self, slice); + Translate::::translate(d).into() } } } diff --git a/src/receipt/succinct.rs b/src/receipt/succinct.rs index 62b0fe5..468762f 100644 --- a/src/receipt/succinct.rs +++ b/src/receipt/succinct.rs @@ -313,6 +313,20 @@ impl SuccinctReceiptVerifierParameters { .translate(), } } + + /// v3_0 set of parameters used to verify a [SuccinctReceipt]. + pub fn v3_0() -> Self { + use crate::circuit::v3_0::recursive as circuit; + + Self { + control_root: circuit::control_id::ALLOWED_CONTROL_ROOT.translate(), + inner_control_root: None, + proof_system_info: PROOF_SYSTEM_INFO, + circuit_info: + ::CIRCUIT_INFO + .translate(), + } + } } #[cfg(test)] diff --git a/src/segment.rs b/src/segment.rs index 9322bd4..ecb8b98 100644 --- a/src/segment.rs +++ b/src/segment.rs @@ -197,6 +197,24 @@ impl SegmentReceiptVerifierParameters { Self::v2_x::(Default::default()) } + fn v3_x(_circuit_info: PhantomData) -> Self { + let p_info = ProtocolInfo(PROOF_SYSTEM_INFO.0); + fn fake_control_id(_hash_name: &str, _po2: usize) -> Option { + None + } + Self::from_max_po2( + &fake_control_id, + DEFAULT_MAX_PO2, + p_info, + ProtocolInfo(C::CIRCUIT_INFO.0), + ) + } + + /// v3.0 set of parameters used to verify a [SegmentReceipt]. + pub fn v3_0() -> Self { + Self::v3_x::(Default::default()) + } + fn from_max_po2( resolver: &dyn Fn(&str, usize) -> Option, max_po2: usize, diff --git a/src/translate.rs b/src/translate.rs index 12371c8..3112e5e 100644 --- a/src/translate.rs +++ b/src/translate.rs @@ -35,6 +35,18 @@ impl Translate for risc0_zkp_v1::core::diges } } +impl Translate for risc0_zkp_v3::core::digest::Digest { + fn translate(self) -> risc0_zkp_v1::core::digest::Digest { + self.as_words().try_into().unwrap() + } +} + +impl Translate for risc0_zkp_v1::core::digest::Digest { + fn translate(self) -> risc0_zkp_v3::core::digest::Digest { + self.as_words().try_into().unwrap() + } +} + impl Translate for risc0_zkp_v1::adapter::ProtocolInfo { fn translate(self) -> risc0_zkp_v2::adapter::ProtocolInfo { risc0_zkp_v2::adapter::ProtocolInfo(self.0) @@ -47,6 +59,18 @@ impl Translate for risc0_zkp_v2::adapter::P } } +impl Translate for risc0_zkp_v1::adapter::ProtocolInfo { + fn translate(self) -> risc0_zkp_v3::adapter::ProtocolInfo { + risc0_zkp_v3::adapter::ProtocolInfo(self.0) + } +} + +impl Translate for risc0_zkp_v3::adapter::ProtocolInfo { + fn translate(self) -> risc0_zkp_v1::adapter::ProtocolInfo { + risc0_zkp_v1::adapter::ProtocolInfo(self.0) + } +} + impl Translate for risc0_zkp_v2::verify::VerificationError { fn translate(self) -> VerificationError { use risc0_zkp_v2::verify::VerificationError as VerificationErrorV2; @@ -103,3 +127,60 @@ impl Translate for risc0_zkp_v2::verify::VerificationError { } } } + +impl Translate for risc0_zkp_v3::verify::VerificationError { + fn translate(self) -> VerificationError { + use risc0_zkp_v3::verify::VerificationError as VerificationErrorV3; + match self { + VerificationErrorV3::ReceiptFormatError => VerificationError::ReceiptFormatError, + VerificationErrorV3::ControlVerificationError { control_id } => { + VerificationError::ControlVerificationError { + control_id: control_id.translate(), + } + } + VerificationErrorV3::ImageVerificationError => { + VerificationError::ImageVerificationError + } + VerificationErrorV3::MerkleQueryOutOfRange { idx, rows } => { + VerificationError::MerkleQueryOutOfRange { idx, rows } + } + VerificationErrorV3::InvalidProof => VerificationError::InvalidProof, + VerificationErrorV3::JournalDigestMismatch => VerificationError::JournalDigestMismatch, + VerificationErrorV3::ClaimDigestMismatch { expected, received } => { + VerificationError::ClaimDigestMismatch { + expected: expected.translate(), + received: received.translate(), + } + } + VerificationErrorV3::UnexpectedExitCode => VerificationError::UnexpectedExitCode, + VerificationErrorV3::InvalidHashSuite => VerificationError::InvalidHashSuite, + VerificationErrorV3::VerifierParametersMissing => { + VerificationError::VerifierParametersMissing + } + VerificationErrorV3::VerifierParametersMismatch { expected, received } => { + VerificationError::VerifierParametersMismatch { + expected: expected.translate(), + received: received.translate(), + } + } + VerificationErrorV3::ProofSystemInfoMismatch { expected, received } => { + VerificationError::ProofSystemInfoMismatch { + expected: expected.translate(), + received: received.translate(), + } + } + VerificationErrorV3::CircuitInfoMismatch { expected, received } => { + VerificationError::CircuitInfoMismatch { + expected: expected.translate(), + received: received.translate(), + } + } + VerificationErrorV3::UnresolvedAssumption { digest } => { + VerificationError::UnresolvedAssumption { + digest: digest.translate(), + } + } + _ => unreachable!("unknown VerificationError variant: {:?}", self), + } + } +} diff --git a/tests/integration.rs b/tests/integration.rs index 3d43033..9eb7923 100644 --- a/tests/integration.rs +++ b/tests/integration.rs @@ -14,7 +14,7 @@ // limitations under the License. use risc0_verifier::{ - v1_0, v1_1, v1_2, v2_0, v2_1, v2_2, v2_3, verify, CompositeReceipt, Journal, Proof, + v1_0, v1_1, v1_2, v2_0, v2_1, v2_2, v2_3, v3_0, verify, CompositeReceipt, Journal, Proof, SegmentInfo, SuccinctReceipt, Verifier, Vk, }; use risc0_zkp_v1::verify::VerificationError; @@ -83,6 +83,7 @@ mod legacy { #[rstest] #[case::v1(v1_0(), "./resources/cases/prover_1.0.3/vm_1.1.3/sha_16.json")] #[case::v2(v2_1(), "./resources/cases/prover_2.1.0/vm_2.1.0/poseidon2_16.json")] +#[case::v3(v3_0(), "./resources/cases/prover_3.0.0/vm_3.0.0/poseidon2_16.json")] fn verify_valid_proof(#[case] verifier: impl Verifier, #[case] path: &str) { let case: Case = read_all(path).unwrap(); @@ -94,6 +95,7 @@ fn verify_valid_proof(#[case] verifier: impl Verifier, #[case] path: &str) { #[rstest] #[case::v1(v1_0().boxed(), "./resources/cases/prover_1.0.3/vm_1.1.3/sha_16.json")] #[case::v2(v2_1().boxed(), "./resources/cases/prover_2.1.0/vm_2.1.0/poseidon2_16.json")] +#[case::v3(v3_0().boxed(), "./resources/cases/prover_3.0.0/vm_3.0.0/poseidon2_16.json")] fn verify_valid_proof_dynamic(#[case] verifier: Box, #[case] path: &str) { let case: Case = read_all(path).unwrap(); @@ -142,12 +144,32 @@ fn read_po2_segment_v2( assert_eq!(vec![SegmentInfo::new(hash.to_owned(), expected_po2)], po2s) } +#[rstest] +fn read_po2_segment_v3( + #[values(v3_0())] verifier: impl Verifier, + #[values(16, 17, 18, 19, 20, 21, 22)] expected_po2: u32, + #[values("poseidon2")] hash: &str, +) { + let case: Case = read_all(format!( + "./resources/cases/single_full_segment_v3/{hash}_{expected_po2}.json" + )) + .unwrap(); + let proof = case.get_proof().unwrap(); + + let po2s = verifier + .extract_composite_segments_info(proof.inner.composite().unwrap()) + .unwrap(); + + assert_eq!(vec![SegmentInfo::new(hash.to_owned(), expected_po2)], po2s) +} + #[rstest] #[case(v1_0(), "./resources/cases/prover_1.0.3/vm_1.0.5/sha_22.json", ("sha-256", [20,20,17].as_slice()))] #[case(v1_1(), "./resources/cases/prover_1.1.3/vm_1.1.1/sha_22.json", ("sha-256", [20,20,17].as_slice()))] #[case(v1_2(), "./resources/cases/prover_1.2.0/vm_1.2.0/sha_22.json", ("sha-256", [20,20,17].as_slice()))] #[case(v2_1(), "./resources/cases/prover_2.1.0/vm_2.1.0/poseidon2_16.json", ("poseidon2", [16].as_slice()))] #[case(v2_1(), "./resources/cases/prover_2.1.0/vm_2.1.0/poseidon2_22.json", ("poseidon2", [20,20,20,20].as_slice()))] +#[case(v3_0(), "./resources/cases/prover_3.0.0/vm_3.0.0/poseidon2_22.json", ("poseidon2", [20,20,20,20].as_slice()))] fn read_po2_segments( #[case] verifier: impl Verifier, #[case] path: &str, @@ -172,6 +194,7 @@ fn read_po2_segments( #[rstest] #[case(v1_2(), "./resources/cases/poseidon2_22_segment_20.json")] #[case(v2_1(), "./resources/cases/prover_2.1.0/vm_2.1.0/poseidon2_22.json")] +#[case(v3_0(), "./resources/cases/prover_3.0.0/vm_3.0.0/poseidon2_22.json")] fn read_po2_segments_case_limit_segments(#[case] verifier: impl Verifier, #[case] path: &str) { let case: Case = read_all(path).unwrap(); let proof = case.get_proof().unwrap(); @@ -346,6 +369,27 @@ mod v2_3 { } } +mod v3_0 { + use super::*; + + #[rstest] + #[case::should_pass(v3_0())] + #[should_panic] + #[case::should_fails_with_old_verifier(v2_1().boxed())] + fn verify_valid_proof( + #[case] verifier: impl Verifier, + #[files("./resources/cases/prover_3.0.*/**/*.json")] path: PathBuf, + ) { + let case: Case = read_all(path).unwrap(); + + let proof = case.get_proof().unwrap(); + + verifier + .verify(case.vk.into(), proof, case.journal) + .unwrap() + } +} + mod use_custom_local_implemented_hash_function { use super::*; @@ -414,6 +458,28 @@ mod use_custom_local_implemented_hash_function { "./resources/cases/prover_2.1.0/vm_2.1.0/succinct_22.json", FakePoseidon2 )] + #[case::v3( + v3_0(), + "./resources/cases/prover_3.0.0/vm_3.0.0/poseidon2_22.json", + LocPoseidon2 + )] + #[case::v3_succinct( + v3_0(), + "./resources/cases/prover_3.0.0/vm_3.0.0/succinct_22.json", + LocPoseidon2 + )] + #[should_panic(expected = "invalid")] + #[case::v3_with_fake( + v3_0(), + "./resources/cases/prover_3.0.0/vm_3.0.0/poseidon2_22.json", + FakePoseidon2 + )] + #[should_panic(expected = "invalid")] + #[case::v3_succinct_with_fake( + v3_0(), + "./resources/cases/prover_3.0.0/vm_3.0.0/succinct_22.json", + FakePoseidon2 + )] fn should_poseidon2_injected( #[case] mut verifier: impl Verifier, #[case] path: &str, @@ -567,6 +633,7 @@ fn fails_on_invalid_succinct_claim(#[case] verifier: impl Verifier, #[case] path #[case::poseidon_proof_v2_1(v2_1(), "./resources/cases/prover_2.1.0/vm_2.1.0/poseidon2_22.json")] #[case::poseidon_proof_v2_2(v2_2(), "./resources/cases/prover_2.2.0/vm_2.2.0/poseidon2_22.json")] #[case::poseidon_proof_v2_3(v2_3(), "./resources/cases/prover_2.3.0/vm_2.3.0/poseidon2_22.json")] +#[case::poseidon_proof_v3_0(v3_0(), "./resources/cases/prover_3.0.0/vm_3.0.0/poseidon2_22.json")] fn segments(#[case] verifier: impl Verifier, #[case] path: &str) {} #[rstest_reuse::template] @@ -577,6 +644,7 @@ fn segments(#[case] verifier: impl Verifier, #[case] path: &str) {} #[case::succinct_proof_v2_1(v2_1(), "./resources/cases/prover_2.1.0/vm_2.1.0/succinct_22.json")] #[case::succinct_proof_v2_2(v2_2(), "./resources/cases/prover_2.2.0/vm_2.2.0/succinct_22.json")] #[case::succinct_proof_v2_3(v2_3(), "./resources/cases/prover_2.3.0/vm_2.3.0/succinct_22.json")] +#[case::succinct_proof_v3_0(v3_0(), "./resources/cases/prover_3.0.0/vm_3.0.0/succinct_22.json")] fn succinct(#[case] verifier: impl Verifier, #[case] path: &str) {} #[rstest_reuse::template] @@ -590,12 +658,14 @@ fn succinct(#[case] verifier: impl Verifier, #[case] path: &str) {} #[case::poseidon_proof_v2_1(v2_1(), "./resources/cases/prover_2.1.0/vm_2.1.0/poseidon2_22.json")] #[case::poseidon_proof_v2_2(v2_2(), "./resources/cases/prover_2.2.0/vm_2.2.0/poseidon2_22.json")] #[case::poseidon_proof_v2_3(v2_3(), "./resources/cases/prover_2.3.0/vm_2.3.0/poseidon2_22.json")] +#[case::poseidon_proof_v3_0(v3_0(), "./resources/cases/prover_3.0.0/vm_3.0.0/poseidon2_22.json")] #[case::succinct_proof_v1_0(v1_0(), "./resources/cases/prover_1.0.3/vm_1.0.5/succinct_22.json")] #[case::succinct_proof_v1_1(v1_1(), "./resources/cases/prover_1.1.3/vm_1.1.3/succinct_22.json")] #[case::succinct_proof_v1_2(v1_2(), "./resources/cases/prover_1.2.0/vm_1.2.0/succinct_22.json")] #[case::succinct_proof_v2_1(v2_1(), "./resources/cases/prover_2.1.0/vm_2.1.0/succinct_22.json")] #[case::succinct_proof_v2_2(v2_2(), "./resources/cases/prover_2.2.0/vm_2.2.0/succinct_22.json")] #[case::succinct_proof_v2_3(v2_3(), "./resources/cases/prover_2.3.0/vm_2.3.0/succinct_22.json")] +#[case::succinct_proof_v3_0(v3_0(), "./resources/cases/prover_3.0.0/vm_3.0.0/succinct_22.json")] fn all(#[case] verifier: impl Verifier, #[case] path: &str) {} fn read_all(path: impl AsRef) -> anyhow::Result {